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Changes

Summary

  1. [clangd] Check if macro is already in the IdentifierTable before loading it (details)
  2. [MLIR][GPU][NVVM] Add warp synchronous matrix-multiply accumulate ops (details)
  3. [OpenMP] Make sure classes work on the device as they do on the host (details)
  4. [OpenMP] Ensure the DefaultMapperId has a location (details)
  5. [OpenMP] Overhaul `declare target` handling (details)
  6. [llvm][NFC] Remove deprecated Alignment::None() (details)
  7. [llvm][NFC] Remove deprecated DataLayout::getPreferredAlignment functions (details)
  8. [llvm][NFC] Remove deprecated InterleaveGroup::getAlignment() function. (details)
  9. [llvm][NFC] Remove SelectionDag alignment deprecated functions (details)
  10. [llvm][NFC] Remove CallingConvLower deprecated alignment functions (details)
  11. [llvm-objdump] Use std::make_unique (details)
  12. [lit] Report tool path from use_llvm_tool if found via env variable (details)
  13. [ARM] Transforming memcpy to Tail predicated Loop (details)
  14. [flang] Remove `%f18` from LIT configuration files (details)
  15. [AMDGPU] SIFoldOperands: clean up tryConstantFoldOp (details)
  16. [clang-format] Add more support for C# 8 nullables (details)
  17. [clang-format] Fix C# nullable-related errors (details)
  18. [clang-format] Rename common types between C#/JS (details)
  19. [SVE][LoopVectorize] Add support for scalable vectorization of first-order recurrences (details)
  20. [SystemZ] Support builtin_frame_address with packed stack without backchain. (details)
  21. [AMDGPU] Regenerate shift tests. NFCI. (details)
  22. [AMDGPU] Regenerate fp2int tests. NFCI. (details)
  23. [mlir] Add support for ops with regions in 'gpu-async-region' rewriter. (details)
  24. [LLD] Improve --strip-all help text (details)
  25. [LV] Account for tripcount when calculation vectorization profitability (details)
  26. [ORC] Silence unused variable warnings in Release builds. NFC. (details)
  27. Revert "[ARM] Transforming memcpy to Tail predicated Loop" (details)
  28. [AMDGPU] Fix WQM failure with single block inactive demote (details)
  29. [amdgpu-arch] Fix rpath to run from build dir (details)
  30. [OpenCL] Remove subgroups pragma in enqueue kernel and pipe builtins. (details)
  31. [TableGen] [Clang] Clean up Options.td and add asserts. (details)
  32. [PowerPC] Provide some P8-specific altivec overloads for P7 (details)
  33. [AMDGPU] SIInsertHardClauses: move more stuff into the class. NFC. (details)
  34. [lldb][NFC] Make assert in TestStaticVariables more expressive (details)
  35. Revert "[PowerPC] Provide some P8-specific altivec overloads for P7" (details)
  36. [AIX][TLS] Add support for TLSGD relocations to XCOFF objects (details)
  37. [libc++] Rewrite std::to_address to avoid relying on element_type (details)
  38. [OpenMP] Temporarily require X86 target for parallel_for_codegen.cpp test (details)
  39. [AMDGPU][NFC] Fix typos in SIFormMemoryClauses description (details)
  40. [PowerPC] Re-commit ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8 (details)
  41. [mlir][vector] add pattern to cast away lead unit dimension for broadcast op (details)
  42. [mlir][NFC] Fix warning in VectorTransforms.cpp (details)
  43. [lld-macho][nfc] Convert the mock libSystem.tbd to TBDv4 (details)
  44. [lld-macho] Support loading of zippered dylibs (details)
  45. [SLP] Use empty() instead of size() == 0. NFCI. (details)
  46. [SLP] Constify the TreeEntry* input into dumpTreeCosts(). NFCI. (details)
  47. [SLP] Constify the TreeEntry* input into getEntryCost() + setInsertPointAfterBundle(). NFCI. (details)
  48. [AMDGPU] Fix 64 bit DPP validation (details)
  49. [clangd][ObjC] Highlight Objc Ivar refs (details)
  50. [LangRef][VP] Fix typos in VP sdiv/udiv examples (details)
  51. [RISCV] Cleanup instruction formats used for B extension ternary operations. (details)
  52. [SystemZ] Don't use libcall for 128 bit shifts. (details)
  53. Fix array attribute in bindings for linalg.init_tensor (details)
  54. [AIX][Test][ORC] Skip unsupported ORC C API tests on AIX (details)
  55. [RISCV] Remove unused RISCV::VLEFF and VLEFF_MASK. NFC (details)
  56. [PowerPC][LLD] Make sure that the correct Thunks are used. (details)
  57. [WebAssembly] Fix argument types in SIMD narrowing intrinsics (details)
  58. [mlir][linalg][NFC] Make reshape folding control more fine grain (details)
  59. [mlir][vector] Fix typo (details)
  60. [gn build] Support compiler-rt/profile on Windows (details)
  61. [flang] Runtime must defer formatted/unformatted determination (details)
  62. Allow llvm-dis to disassemble multiple files (details)
  63. [flang] Fix race condition in runtime (details)
  64. [AArch64] Fix namespace issue. NFC (details)
  65. [flang] Implement NAMELIST I/O in the runtime (details)
  66. [RISCV] Minor vector instruction tablegen cleanup. NFC (details)
  67. [libunwind] NFC: Use macros to accommodate differences in representation of PowerPC assemblers (details)
  68. [Fuchsia][CMake] Update OSX deployment target (details)
  69. [flang][OpenMP] Add semantic check for occurrence of constructs nested inside a SIMD region (details)
  70. [RISCV] Remove unused ComplexPatterns. NFC (details)
  71. [NPM] Do not run function simplification pipeline unnecessarily (details)
  72. [PassManager] add helper function to hold set of vector passes (details)
  73. [mlir] Store the flag for dynamic operand storage in the low bits (details)
  74. [Index] Ignore nullptr decls for indexing (details)
  75. new altera ID dependent backward branch check (details)
  76. [gn build] Port 83af66e18e3d (details)
  77. Thread safety analysis: Eliminate parameter from intersectAndWarn (NFC) (details)
  78. When SendContinuePacketAndWaitForResponse returns eStateInvalid, don't fetch more packets. (details)
  79. [mlir][spirv] NFC: Replace OwningSPIRVModuleRef with OwningOpRef (details)
  80. [libomptarget][amdgpu][nfc] Remove dead code from amdgpu plugin (details)
  81. [ARM] Transforming memcpy to Tail predicated Loop (details)
  82. [mlir] Update dstNode after DenseMap insertion in loop fusion pass. (details)
  83. [libomptarget][nfc] Refactor amdgpu partial barrier to simplify adding a second one (details)
  84. [mlir][tosa] Added div op, variadic concat. Removed placeholder. Spec v0.22 alignment. (details)
  85. [AMDGPU] Expose __builtin_amdgcn_perm for v_perm_b32 (details)
  86. [llvm][TextAPI] add mapping from OS string to Platform (details)
  87. [dfsan] Rename and fix an internal test issue for mmap+calloc (details)
  88. [mlir][Linalg] Allow folding to rank-zero tensor when using rank-reducing subtensors. (details)
  89. [CGAtomic] Lift strong requirement for remaining compare_exchange combinations (details)
  90. [IR] Fix typo in comment of Intrinsics.td (NFC) (details)
  91. [TableGen] Use range-based for loops (NFC) (details)
  92. BPF: fix FIELD_EXISTS relocation with array subscripts (details)
  93. [PowerPC] Remove extra swap for extract+vperm on LE (details)
  94. [mlir][linalg] Add IndexedGenericOp to GenericOp canonicalization. (details)
  95. [XCOFF] handle string constants generation for AIX (details)
Commit 16c7829784f071d9fd4ae9da4cc8b3786a58018e by kadircet
[clangd] Check if macro is already in the IdentifierTable before loading it

Having nested macros in the C code could cause clangd to fail an assert in clang::Preprocessor::setLoadedMacroDirective() and crash.

#1 0x00000000007ace30 PrintStackTraceSignalHandler(void*) /qdelacru/llvm-project/llvm/lib/Support/Unix/Signals.inc:632:1
#2 0x00000000007aaded llvm::sys::RunSignalHandlers() /qdelacru/llvm-project/llvm/lib/Support/Signals.cpp:76:20
#3 0x00000000007ac7c1 SignalHandler(int) /qdelacru/llvm-project/llvm/lib/Support/Unix/Signals.inc:407:1
#4 0x00007f096604db20 __restore_rt (/lib64/libpthread.so.0+0x12b20)
#5 0x00007f0964b307ff raise (/lib64/libc.so.6+0x377ff)
#6 0x00007f0964b1ac35 abort (/lib64/libc.so.6+0x21c35)
#7 0x00007f0964b1ab09 _nl_load_domain.cold.0 (/lib64/libc.so.6+0x21b09)
#8 0x00007f0964b28de6 (/lib64/libc.so.6+0x2fde6)
#9 0x0000000001004d1a clang::Preprocessor::setLoadedMacroDirective(clang::IdentifierInfo*, clang::MacroDirective*, clang::MacroDirective*) /qdelacru/llvm-project/clang/lib/Lex/PPMacroExpansion.cpp:116:5

An example of the code that causes the assert failure:
```
...
```

During code completion in clangd, the macros will be loaded in loadMainFilePreambleMacros() by iterating over the macro names and calling PreambleIdentifiers->get(). Since these macro names are store in a StringSet (has StringMap underlying container), the order of the iterator is not guaranteed to be same as the order seen in the source code.

When clangd is trying to resolve nested macros it sometimes attempts to load them out of order which causes a macro to be stored twice. In the example above, ECHO2 macro gets resolved first, but since it uses another macro that has not been resolved it will try to resolve/store that as well. Now there are two MacroDirectives stored in the Preprocessor, ECHO and ECHO2. When clangd tries to load the next macro, ECHO, the preprocessor fails an assert in clang::Preprocessor::setLoadedMacroDirective() because there is already a MacroDirective stored for that macro name.

In this diff, I check if the macro is already inside the IdentifierTable and if it is skip it so that it is not resolved twice.

Reviewed By: kadircet

Differential Revision: https://reviews.llvm.org/D101870
The file was modifiedclang-tools-extra/clangd/CodeComplete.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CodeCompleteTests.cpp
Commit 875eb523c13249114507cb8facd797773e278d9e by uday
[MLIR][GPU][NVVM] Add warp synchronous matrix-multiply accumulate ops

Add warp synchronous matrix-multiply accumulate ops in GPU and NVVM
dialect. Add following three ops to GPU dialect :-
  1.) subgroup_mma_load_matrix
  2.) subgroup_mma_store_matrix
  3.) subgroup_mma_compute
Add following three ops to NVVM dialect :-
  1.) wmma.m16n16k16.load.[a,b,c].[f16,f32].row.stride
  2.) wmma.m16n16k16.store.d.[f16,f32].row.stride
  3.) wmma.m16n16k16.mma.row.row.[f16,f32].[f16,f32]

Reviewed By: bondhugula, ftynse, ThomasRaoux

Differential Revision: https://reviews.llvm.org/D95330
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUOps.td
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUBase.td
The file was modifiedmlir/test/Dialect/LLVMIR/invalid.mlir
The file was modifiedmlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUDialect.h
The file was modifiedmlir/test/Dialect/GPU/invalid.mlir
The file was modifiedmlir/test/Dialect/GPU/ops.mlir
The file was modifiedmlir/test/Target/LLVMIR/nvvmir.mlir
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
Commit 5d8d994dfbe38fe86b1d883daa9fd8e47cdc1376 by johannes
[OpenMP] Make sure classes work on the device as they do on the host

We do provide `operator delete(void*)` in `<new>` but it should be
available by default. This is mostly boilerplate to test it and the
unconditional include of `<new>` in the header we always in include
on the device.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D100620
The file was modifiedclang/lib/Headers/openmp_wrappers/new
The file was modifiedclang/lib/Headers/openmp_wrappers/__clang_openmp_device_functions.h
The file was addedclang/test/Headers/Inputs/include/new
The file was modifiedclang/test/Headers/Inputs/include/stdlib.h
The file was addedclang/test/Headers/target_include_new.cpp
Commit 3f14596700093bce436ae27178c307e842398b65 by johannes
[OpenMP] Ensure the DefaultMapperId has a location

A user reported an assertion (below) but without a reproducer. I failed to
create a test myself but from the assertion one can derive the problem.
I set the DefaultMapperId location now to make sure this doesn't cause
trouble.

```
clang-13: .../DeclTemplate.h:1940:
void clang::ClassTemplateSpecializationDecl::setPointOfInstantiation(clang::SourceLocation):
Assertion `Loc.isValid() && "point of instantiation must be valid!"' failed.
```

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D100621
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
Commit df729e2b82b3cfc602a2295b95b7fa55ab423e88 by johannes
[OpenMP] Overhaul `declare target` handling

This patch fixes various issues with our prior `declare target` handling
and extends it to support `omp begin declare target` as well.

This started with PR49649 in mind, trying to provide a way for users to
avoid the "ref" global use introduced for globals with internal linkage.
From there it went down the rabbit hole, e.g., all variables, even
`nohost` ones, were emitted into the device code so it was impossible to
determine if "ref" was needed late in the game (based on the name only).
To make it really useful, `begin declare target` was needed as it can
carry the `device_type`. Not emitting variables eagerly had a ripple
effect. Finally, the precedence of the (explicit) declare target list
items needed to be taken into account, that meant we cannot just look
for any declare target attribute to make a decision. This caused the
handling of functions to require fixup as well.

I tried to clean up things while I was at it, e.g., we should not "parse
declarations and defintions" as part of OpenMP parsing, this will always
break at some point. Instead, we keep track what region we are in and
act on definitions and declarations instead, this is what we do for
declare variant and other begin/end directives already.

Highlights:
  - new diagnosis for restrictions specificed in the standard,
  - delayed emission of globals not mentioned in an explicit
    list of a declare target,
  - omission of `nohost` globals on the host and `host` globals on the
    device,
  - no explicit parsing of declarations in-between `omp [begin] declare
    variant` and the corresponding end anymore, regular parsing instead,
  - precedence for explicit mentions in `declare target` lists over
    implicit mentions in the declaration-definition-seq, and
  - `omp allocate` declarations will now replace an earlier emitted
    global, if necessary.

---

Notes:

The patch is larger than I hoped but it turns out that most changes do
on their own lead to "inconsistent states", which seem less desirable
overall.

After working through this I feel the standard should remove the
explicit declare target forms as the delayed emission is horrible.
That said, while we delay things anyway, it seems to me we check too
often for the current status even though that is often not sufficient to
act upon. There seems to be a lot of duplication that can probably be
trimmed down. Eagerly emitting some things seems pretty weak as an
argument to keep so much logic around.

---

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D101030
The file was modifiedclang/include/clang/Parse/Parser.h
The file was modifiedclang/test/OpenMP/nvptx_target_codegen.cpp
The file was modifiedclang/test/OpenMP/task_codegen.cpp
The file was modifiedclang/test/Headers/nvptx_device_math_complex.c
The file was modifiedclang/test/OpenMP/nvptx_declare_variant_name_mangling.cpp
The file was modifiedclang/test/OpenMP/single_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/declare_target_codegen_globalization.cpp
The file was modifiedclang/test/OpenMP/irbuilder_nested_parallel_for.c
The file was modifiedclang/lib/CodeGen/CGDecl.cpp
The file was addedclang/test/OpenMP/declare_target_only_one_side_compilation.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.expected
The file was modifiedclang/test/OpenMP/declare_target_messages.cpp
The file was modifiedclang/test/OpenMP/irbuilder_for_rangefor.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
The file was modifiedclang/test/OpenMP/for_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/irbuilder_for_iterator.cpp
The file was modifiedclang/test/OpenMP/single_codegen.cpp
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
The file was modifiedclang/lib/AST/AttrImpl.cpp
The file was modifiedclang/include/clang/Basic/Attr.td
The file was modifiedclang/include/clang/Basic/DiagnosticParseKinds.td
The file was modifiedclang/test/OpenMP/remarks_parallel_in_target_state_machine.c
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/lib/Parse/ParseOpenMP.cpp
The file was modifiedclang/test/OpenMP/parallel_for_codegen.cpp
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMP.td
The file was modifiedclang/test/OpenMP/irbuilder_for_unsigned.c
The file was modifiedclang/test/OpenMP/remarks_parallel_in_multiple_target_state_machines.c
The file was modifiedclang/test/OpenMP/nvptx_declare_target_var_ctor_dtor_codegen.cpp
The file was modifiedclang/test/OpenMP/tile_codegen.cpp
The file was removedclang/test/OpenMP/declare_target_device_only_compilation.cpp
The file was modifiedclang/test/OpenMP/taskgroup_codegen.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.h
The file was modifiedclang/test/OpenMP/nvptx_multi_target_parallel_codegen.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_codegen.cpp
The file was modifiedclang/test/OpenMP/sections_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/irbuilder_nested_openmp_parallel_empty.c
The file was modifiedclang/test/OpenMP/nvptx_nested_parallel_codegen.cpp
The file was modifiedclang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.expected
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/test/OpenMP/threadprivate_codegen.cpp
Commit b4795544d42b4c3d49fdf63b797b07f40242a427 by gchatelet
[llvm][NFC] Remove deprecated Alignment::None()

Differential Revision: https://reviews.llvm.org/D101905
The file was modifiedllvm/include/llvm/Support/Alignment.h
Commit a065efa302f64f225d9187b49b4dd061b5c58b08 by gchatelet
[llvm][NFC] Remove deprecated DataLayout::getPreferredAlignment functions

Differential Revision: https://reviews.llvm.org/D101906
The file was modifiedllvm/include/llvm/IR/DataLayout.h
Commit 040f4a97cd400e8464478e9b7c1d7d94d2bad708 by gchatelet
[llvm][NFC] Remove deprecated InterleaveGroup::getAlignment() function.

Differential Revision: https://reviews.llvm.org/D101907
The file was modifiedllvm/include/llvm/Analysis/VectorUtils.h
Commit 1fa21bf9e999f8fcb6e9137acb69aa940ad0e3ab by gchatelet
[llvm][NFC] Remove SelectionDag alignment deprecated functions

Differential Revision: https://reviews.llvm.org/D101909
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAG.h
Commit 089ec047bea8f6a0a47d8c4ad5142e9ca8b5aed9 by gchatelet
[llvm][NFC] Remove CallingConvLower deprecated alignment functions

Differential Revision: https://reviews.llvm.org/D101910
The file was modifiedllvm/include/llvm/CodeGen/CallingConvLower.h
Commit ab5932ffbd91b3989e20344cf104abe7c0cad1ae by tim.renouf
[llvm-objdump] Use std::make_unique

Fix up my recent commit rG1128311a19179ceca799ff0fbc4dd206ab56e560 to
use std::make_unique instead of std::unique_ptr(new), as requested by
David Blaikie.

Differential Revision: https://reviews.llvm.org/D101822
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
Commit abe2c906ad4c34d257e63b067fe8514050ea77ff by james.henderson
[lit] Report tool path from use_llvm_tool if found via env variable

Previously, if the search_env argument was specified, and the tool was
found at that location, the path was not reported, unlike other
situations when this function was called. Adding the reporting makes the
function consistent.

Reviewed by: thopre

Differential Revision: https://reviews.llvm.org/D101896
The file was modifiedllvm/utils/lit/lit/llvm/config.py
The file was addedllvm/utils/lit/tests/Inputs/use-tool-search-env/test.tool
The file was addedllvm/utils/lit/tests/Inputs/use-tool-search-env/true.txt
The file was addedllvm/utils/lit/tests/Inputs/use-tool-search-env/lit.cfg
The file was addedllvm/utils/lit/tests/use-tool-search-env.py
Commit b856f4a232cbd43476e9b9f75c80aacfc6f5c152 by malhar.jajoo
[ARM] Transforming memcpy to Tail predicated Loop

This patch converts llvm.memcpy intrinsic into Tail Predicated
Hardware loops for a target that supports the Arm M-profile
Vector Extension (MVE).

From an implementation point of view, the patch

- adds an ARM specific SDAG Node (to which the llvm.memcpy intrinsic is lowered to, during first phase of ISel)
- adds a corresponding TableGen entry to generate a pseudo instruction, with a custom inserter,
  on matching the above node.
- Adds a custom inserter function that expands the pseudo instruction into MIR suitable
   to be (by later passes) into a WLSTP loop.

Note: A cli option is used to control the conversion of memcpy to TP
loop and this option is currently disabled by default. It may be enabled
in the future after further downstream testing.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D99723
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
The file was addedllvm/test/CodeGen/Thumb2/mve-tp-loop.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was addedllvm/test/CodeGen/Thumb2/mve-tp-loop.mir
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
Commit 65cd0d6be47730cefdd5be26c12f02ec59b4d08e by andrzej.warzynski
[flang] Remove `%f18` from LIT configuration files

`%f18` was originally introduced to represent the old Flang driver,
`f18`. With the introduction of the new driver, `flang-new`, we have
been switching to `%flang` (compiler driver) and `%flang_fc1` (frontend
driver) as more generic alternatives.

As most tests have been portend to use the new LIT variables instead of
`%f18`, this is good time to remove it from lit.cfg.py. There's only one
test left that requires the old driver to run. It's updated with:
```
! REQUIRES: old-flang-driver
```
This way we preserve its semantics while reducing the number of
variables in LIT configuration.

Differential Revision: https://reviews.llvm.org/D101281
The file was modifiedflang/test/Driver/help-f18.f90
The file was modifiedflang/test/lit.cfg.py
Commit 7c706af03b8634f1f2a64599037580e5f4785082 by jay.foad
[AMDGPU] SIFoldOperands: clean up tryConstantFoldOp

First clean up the strange API of tryConstantFoldOp where it took an
immediate operand value, but no indication of which operand it was the
value for.

Second clean up the loop that calls tryConstantFoldOp so that it does
not have to restart from the beginning every time it folds an
instruction.

This is NFCI but there are some minor changes caused by the order in
which things are folded.

Differential Revision: https://reviews.llvm.org/D100031
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFoldOperands.cpp
Commit a437befa8f8580b3b4f2226b208a05da078c8b20 by marek.kurdej+llvm.org
[clang-format] Add more support for C# 8 nullables

This adds support for the null-coalescing assignment and null-forgiving
operators.

https://docs.microsoft.com/en-us/dotnet/csharp/language-reference/operators/null-coalescing-operator

https://docs.microsoft.com/en-us/dotnet/csharp/language-reference/operators/null-forgiving

Reviewed By: krasimir, curdeius

Differential Revision: https://reviews.llvm.org/D101702
The file was modifiedclang/lib/Format/FormatToken.h
The file was modifiedclang/lib/Format/FormatTokenLexer.h
The file was modifiedclang/unittests/Format/FormatTestCSharp.cpp
The file was modifiedclang/lib/Format/FormatTokenLexer.cpp
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
Commit ec725b307f3fdc5656459047bab6e69669d9534f by marek.kurdej+llvm.org
[clang-format] Fix C# nullable-related errors

This fixes two errors:

Previously, clang-format was splitting up type identifiers from the
nullable ?. This changes this behavior so that the type name sticks with
the operator.

Additionally, nullable operators attached to return types in interface
functions were not parsed correctly. Digging deeper, it looks like
interface bodies were being parsed differently than classes and structs,
causing MustBeDeclaration to be incorrect for interface members. They
now share the same logic.

One other change is reintroducing the CSharpNullable type independent of
JsTypeOptionalQuestion. Despite having a similar semantic purpose, their
actual syntax differs quite a bit.

Reviewed By: MyDeveloperDay, curdeius

Differential Revision: https://reviews.llvm.org/D101860
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
The file was modifiedclang/lib/Format/UnwrappedLineParser.h
The file was modifiedclang/unittests/Format/FormatTestCSharp.cpp
The file was modifiedclang/lib/Format/FormatToken.h
The file was modifiedclang/lib/Format/UnwrappedLineParser.cpp
Commit cdf33962d9768fbd8d6b193aff463a21eaa984f3 by marek.kurdej+llvm.org
[clang-format] Rename common types between C#/JS

Reviewed By: curdeius

Differential Revision: https://reviews.llvm.org/D101862
The file was modifiedclang/lib/Format/FormatToken.h
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
The file was modifiedclang/lib/Format/FormatTokenLexer.cpp
The file was modifiedclang/lib/Format/UnwrappedLineParser.cpp
Commit 8c9742bd239af602ee2743baa3c4281f24d45df1 by kerry.mclaughlin
[SVE][LoopVectorize] Add support for scalable vectorization of first-order recurrences

Adds support for scalable vectorization of loops containing first-order recurrences, e.g:
```
for(int i = 0; i < n; i++)
  b[i] =  a[i] + a[i - 1]
```
This patch changes fixFirstOrderRecurrence for scalable vectors to take vscale into
account when inserting into and extracting from the last lane of a vector.
CreateVectorSplice has been added to construct a vector for the recurrence, which
returns a splice intrinsic for scalable types. For fixed-width the behaviour
remains unchanged as CreateVectorSplice will return a shufflevector instead.

The tests included here are the same as test/Transform/LoopVectorize/first-order-recurrence.ll

Reviewed By: david-arm, fhahn

Differential Revision: https://reviews.llvm.org/D101076
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll
The file was modifiedllvm/lib/IR/IRBuilder.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was addedllvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
Commit a0da66bc1330f9808ed9814aaa9c3c3d3244852d by paulsson
[SystemZ] Support builtin_frame_address with packed stack without backchain.

In order to use __builtin_frame_address(0) with packed stack and no
backchain, the address of where the backchain would have been written is
returned (like GCC).

This address may either contain a saved register or be unused.

Review: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D101897
The file was modifiedllvm/test/CodeGen/SystemZ/frameaddr-02.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
Commit 20e976e2487f5b52541772e6e92954ebf2dcf13e by llvm-dev
[AMDGPU] Regenerate shift tests. NFCI.
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sra.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/srl.ll
Commit 0fdce16efb281ab52e1aa5a7a760aebcb7a59163 by llvm-dev
[AMDGPU] Regenerate fp2int tests. NFCI.
The file was modifiedllvm/test/CodeGen/AMDGPU/fp_to_sint.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fp_to_uint.ll
Commit a0d019fc89c57736e54a476aa4db63027a2dace2 by csigg
[mlir] Add support for ops with regions in 'gpu-async-region' rewriter.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D101757
The file was modifiedmlir/lib/Dialect/GPU/Transforms/AsyncRegionRewriter.cpp
Commit 5dd9f44c17ec0d8b6b88bb015560b3c566622fdc by Ben.Dunbobbin
[LLD] Improve --strip-all help text

This is a slight improvement to the help text, as I was slightly
surprised when strip-all did more than remove the symbol table.

Currently, we match gold's help text for strip-all and strip-debug.
I think that the GNU documentation for these options is not particularly
clear. However, I have opted to make only a minor change here and keep
the help text similar to gold's as these are mature options that are
well understood.

ld.bfd (https://sourceware.org/binutils/docs/ld/Options.html) has a
similar implication although it defines strip-debug as a subset of
strip-all. However, felt that noting that strip-all implies strip-debug
is better; because, with the ld.bfd approach you have to read both the
--strip-debug and the --strip-all help text to understand the behaviour
of --strip-all (and the --strip-all help text doesn't indicate that he
--strip-debug help text is related).

Differential Revision: https://reviews.llvm.org/D101890
The file was modifiedlld/docs/ld.lld.1
The file was modifiedlld/ELF/Options.td
Commit 4979c90458628c9463815d81c637f8787f72fff0 by david.green
[LV] Account for tripcount when calculation vectorization profitability

The loop vectorizer will currently assume a large trip count when
calculating which of several vectorization factors are more profitable.
That is often not a terrible assumption to make as small trip count
loops will usually have been fully unrolled. There are cases however
where we will try to vectorize them, and especially when folding the
tail by masking can incorrectly choose to vectorize loops that are not
beneficial, due to the folded tail rounding the iteration count up for
the vectorized loop.

The motivating example here has a trip count of 5, so either performs 5
scalar iterations or 2 vector iterations (with VF=4). At a high enough
trip count the vectorization becomes profitable, but the rounding up to
2 vector iterations vs only 5 scalar makes it unprofitable.

This adds an alternative cost calculation when we know the max trip
count and are folding tail by masking, rounding the iteration count up
to the correct number for the vector width. We still do not account for
anything like setup cost or the mixture of vector and scalar loops, but
this is at least an improvement in a few cases that we have had
reported.

Differential Revision: https://reviews.llvm.org/D101726
The file was addedllvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 3d746962ed1831987c6a1ab54fe8f6cbb6477e0e by benny.kra
[ORC] Silence unused variable warnings in Release builds. NFC.
The file was modifiedllvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp
Commit fc690777fce0bf50a8f424b05993b1e218713ae5 by malhar.jajoo
Revert "[ARM] Transforming memcpy to Tail predicated Loop"

Reverting commit since it causes failure (10462).
This reverts commit b856f4a232cbd43476e9b9f75c80aacfc6f5c152.
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
The file was removedllvm/test/CodeGen/Thumb2/mve-tp-loop.ll
The file was modifiedllvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
The file was removedllvm/test/CodeGen/Thumb2/mve-tp-loop.mir
Commit 67cfefebbbbb3a5923c47c31293a8f76596de8be by carl.ritson
[AMDGPU] Fix WQM failure with single block inactive demote

Instruction test for inactive kill/demote needs to be based on
actual opcode not whether instruction would be lowered to demote.

Reviewed By: piotr

Differential Revision: https://reviews.llvm.org/D101966
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
Commit b24e9f82b71f325214c41fdc3f106207cc2244a6 by jonathanchesterfield
[amdgpu-arch] Fix rpath to run from build dir

[amdgpu-arch] Fix rpath to run from build dir

Prior to this, amdgpu-arch has RUNPATH set to $ORIGIN/../lib which works
for some installs, but not from the build directory where clang executes
the tool from when running tests.

This cmake option adds the location of the rocr runtime to the RUNPATH
(note, it amends RUNPATH here, despite the cmake option referring to RPATH)
to create a binary that runs from build or install location.

Before:
RUNPATH [$ORIGIN/../lib]
After:
RUNPATH [$ORIGIN/../lib:$HOME/llvm-install/lib]

Credit to Greg for knowing this trick and pointing to examples of it in use
for the aomp build scripts.

Reviewed By: pdhaliwal

Differential Revision: https://reviews.llvm.org/D101926
The file was modifiedclang/tools/amdgpu-arch/CMakeLists.txt
Commit c28a602329a78db5c02cc85679b5035aaf6753b4 by anastasia.stulova
[OpenCL] Remove subgroups pragma in enqueue kernel and pipe builtins.

This patch simplifies the parser and makes the language semantics
consistent. There is no extension pragma requirement in the spec
for the subgroup functions in enqueue kernel or pipes and all other
builtin functions are available without the pragama.

Differential Revision: https://reviews.llvm.org/D100984
The file was modifiedclang/test/SemaOpenCL/cl20-device-side-enqueue.cl
The file was modifiedclang/lib/Sema/SemaChecking.cpp
Commit d40a0b8af771f9b37dd2985fc692443c0ac5473e by Paul C. Anagnostopoulos
[TableGen] [Clang] Clean up Options.td and add asserts.

Differential Revision: https://reviews.llvm.org/D101766
The file was modifiedclang/include/clang/Driver/Options.td
Commit ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8 by nemanja.i.ibm
[PowerPC] Provide some P8-specific altivec overloads for P7

This adds additional support for XL compatibility. There are a number
of functions in altivec.h that produce a single instruction (or a
very short sequence) for Power8 but can be done on Power7 without
scalarization. XL provides these implementations.
This patch adds the following overloads for doubleword vectors:
vec_add
vec_cmpeq
vec_cmpgt
vec_cmpge
vec_cmplt
vec_cmple
vec_sl
vec_sr
vec_sra
The file was modifiedclang/test/CodeGen/builtins-ppc-vsx.c
The file was modifiedclang/lib/Headers/altivec.h
Commit 9e026273b030d77b5429e31fd2d7ce3ca6b68cd8 by jay.foad
[AMDGPU] SIInsertHardClauses: move more stuff into the class. NFC.
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
Commit 3026f75ed0f520f9be7ac354406687a549155ded by Raphael Isemann
[lldb][NFC] Make assert in TestStaticVariables more expressive
The file was modifiedlldb/test/API/lang/cpp/class_static/TestStaticVariables.py
Commit 3761b9a2345aff197707d23a68d4a178489f60e4 by thakis
Revert "[PowerPC] Provide some P8-specific altivec overloads for P7"

This reverts commit ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8.
Breaks check-clang, see e.g.
https://lab.llvm.org/buildbot/#/builders/139/builds/3818
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedclang/test/CodeGen/builtins-ppc-vsx.c
Commit bb113b984565b01355a7f6bb4a5fa2eb8284c2e1 by wei.huang
[AIX][TLS] Add support for TLSGD relocations to XCOFF objects

- Add branch absolute reloction R_RBA, R_TLS relocation for the variable offset
  for the tlsgd model and R_TLSM for the region handle for the tlsgd model
- Properly set the relocation fixed values for R_TLS and R_TLSM
- Emit the TCEntry with the variant kind in the XCOFFStreamer

Reviewed by: sfertile, nemanjai, DiggerLin

Differential Revision: https://reviews.llvm.org/D100214
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp
The file was modifiedllvm/lib/MC/XCOFFObjectWriter.cpp
The file was addedllvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
The file was addedllvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
Commit fe0e86e6026f79e0b18f877196fbddd1d9e140d8 by Louis Dionne
[libc++] Rewrite std::to_address to avoid relying on element_type

This is a rough reapplication of the change that fixed std::to_address
to avoid relying on element_type (da456167). It is somewhat different
because the fix to avoid breaking Clang (which caused it to be reverted
in 347f69c55) was a bit more involved.

Differential Revision: https://reviews.llvm.org/D101638
The file was addedlibcxx/test/std/utilities/memory/pointer.conversion/to_address_std_iterators.pass.cpp
The file was addedlibcxx/test/libcxx/utilities/memory/pointer.conversion/to_address.pass.cpp
The file was modifiedlibcxx/test/std/utilities/memory/pointer.conversion/to_address.pass.cpp
The file was addedlibcxx/test/libcxx/utilities/memory/pointer.conversion/to_address_std_iterators.pass.cpp
The file was modifiedlibcxx/include/iterator
The file was modifiedlibcxx/include/__memory/pointer_traits.h
Commit e4b790c5e3653053819182a67c593bc65de860ac by david.spickett
[OpenMP] Temporarily require X86 target for parallel_for_codegen.cpp test

Since https://reviews.llvm.org/D101849 this test has been failing
on bots that only enable either Arm or AArch64 targets.

See: https://lab.llvm.org/buildbot/#/builders/107/builds/7601

Temporarily requires X86 for this test while the difference is figured out.
The file was modifiedclang/test/OpenMP/parallel_for_codegen.cpp
Commit 172d746e167b958e80dfae7c113bfb44b974f7c6 by Austin.Kerbow
[AMDGPU][NFC] Fix typos in SIFormMemoryClauses description

NFC.
The file was modifiedllvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
Commit 1faf3b195e71dbc469d658d450949439dbf92f9f by nemanja.i.ibm
[PowerPC] Re-commit ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8

This was reverted in 3761b9a2345aff197707d23a68d4a178489f60e4 just
as I was about to commit the fix. This patch inlcudes the
necessary fix.
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedclang/test/CodeGen/builtins-ppc-p8vector.c
The file was modifiedclang/test/CodeGen/builtins-ppc-vsx.c
Commit 0b303da6f821dcbcb3f72135b2431aaf94045839 by thomasraoux
[mlir][vector] add pattern to cast away lead unit dimension for broadcast op

Differential Revision: https://reviews.llvm.org/D101955
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/test/Dialect/Vector/vector-transforms.mlir
Commit 933551eaeb08d42d7891c8fbb67cb805e24f9727 by thomasraoux
[mlir][NFC] Fix warning in VectorTransforms.cpp
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
Commit 7654d8e1a96cb9dda0318ff5489c17f3780f1944 by jezng
[lld-macho][nfc] Convert the mock libSystem.tbd to TBDv4

It doesn't seem like TBDv3 allows for specifying multiple platforms, so I'm
upgrading us to TBDv4. (We need to support multiple platforms in order to test
that we can handle zippered dylibs; that functionality will be added in an
upcoming diff.)

Differential Revision: https://reviews.llvm.org/D101953
The file was modifiedlld/test/MachO/Inputs/MacOSX.sdk/usr/lib/libSystem.tbd
Commit 9260760235261a5cd150b15a3499f7988da65a02 by jezng
[lld-macho] Support loading of zippered dylibs

ld64 can emit dylibs that support more than one platform (typically macOS and
macCatalyst). This diff allows LLD to read in those dylibs. Note that this is a
super bare-bones implementation -- in particular, I haven't added support for
LLD to emit those multi-platform dylibs, nor have I added a variety of
validation checks that ld64 does. Until we have a use-case for emitting zippered
dylibs, I think this is good enough.

Fixes PR49597.

Reviewed By: #lld-macho, oontvoo

Differential Revision: https://reviews.llvm.org/D101954
The file was modifiedlld/MachO/InputFiles.h
The file was modifiedlld/MachO/InputFiles.cpp
The file was addedlld/test/MachO/zippered.yaml
The file was modifiedlld/test/MachO/Inputs/MacOSX.sdk/usr/lib/libSystem.tbd
Commit 1b47489fd0e1c3ddbeabb421b668b7bc623fd622 by llvm-dev
[SLP] Use empty() instead of size() == 0. NFCI.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 2dab05902112042eb4cc2cd16adfbe0a9127c0af by llvm-dev
[SLP] Constify the TreeEntry* input into dumpTreeCosts(). NFCI.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 338c1b701f23888eed67ca7e3214db175940df21 by llvm-dev
[SLP] Constify the TreeEntry* input into getEntryCost() + setInsertPointAfterBundle(). NFCI.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 28f1d018b1c241968d3f426d81c6973b5cae7bcf by Stanislav.Mekhanoshin
[AMDGPU] Fix 64 bit DPP validation

AMDGPUAsmParser::isSupportedDPPCtrl() was failing to correctly
find a DPP register operand, regadless of the position it is
always src0. Moved this check into a new validateDPP() method
where we have full instruction already. In particular it was
failing to reject this case:

v_cvt_u32_f64 v5, v[0:1] quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf

Essentially it was broken for any case where size of dst and
src0 differ.

It also improves the diagnostics with a proper error message.

The check in the InstPrinter also drops verification of the dst
register as it does not have anything to do with the dpp operand.

Differential Revision: https://reviews.llvm.org/D101930
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modifiedllvm/test/MC/AMDGPU/gfx9-asm-err.s
The file was modifiedllvm/test/MC/AMDGPU/gfx90a_err.s
Commit 159dd447fe98f558879343d660b5bfe90779609f by davg
[clangd][ObjC] Highlight Objc Ivar refs

Treat them just like we do for properties - as a `property` semantic
token although ideally we could differentiate the two.

Differential Revision: https://reviews.llvm.org/D101785
The file was modifiedclang-tools-extra/clangd/FindTarget.cpp
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp
Commit 2e0ee68dc85c0a2b7e65e489a60ab363393b06a8 by fraser
[LangRef][VP] Fix typos in VP sdiv/udiv examples
The file was modifiedllvm/docs/LangRef.rst
Commit 58323be415ce0713fdd959edeab788252118c533 by craig.topper
[RISCV] Cleanup instruction formats used for B extension ternary operations.

Rename RVInstR4 as used by F/D/Zfh extensions to RVInstR4Frm.
Introduce new RVInstR4 that takes funct3 as a parameter.

Add new format classes for FSRI and FSRIW instead of trying to
bend RVInstR4 to use a shamt overlayed on rs2 and funct2.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D100427
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoF.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrFormats.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoB.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoD.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
Commit 1c4cb510b4daccc0f4763958567affc2b442f317 by paulsson
[SystemZ] Don't use libcall for 128 bit shifts.

Expand 128 bit shifts instead of using a libcall.

This patch removes the 128 bit shift libcalls and thereby causes
ExpandShiftWithUnknownAmountBit() to be called.

Review: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D101993
The file was modifiedllvm/lib/Target/SystemZ/SystemZISelLowering.cpp
The file was modifiedllvm/test/CodeGen/SystemZ/shift-12.ll
Commit 1f109f9d9cddbc90d97b50c154a8474e7e623356 by zinenko
Fix array attribute in bindings for linalg.init_tensor

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D101998
The file was modifiedmlir/python/mlir/dialects/_linalg_ops_ext.py
The file was modifiedmlir/test/python/dialects/linalg/ops.py
Commit e2d774a3dbbbbff21531289889f6906b22f04cfe by hubert.reinterpretcast
[AIX][Test][ORC] Skip unsupported ORC C API tests on AIX

As mentioned before in D78813, currently the XCOFF backend does not
support writing 64-bit object files, which the ORC JIT tests will try to
exercise if we are on AIX. This patch disables the tests on AIX for now.
This is consistent with what's been done, for example, regarding
`armv7`.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D101971
The file was modifiedllvm/unittests/ExecutionEngine/Orc/OrcCAPITest.cpp
Commit 6660319cef6edf114a4cc30013039fa5553ba408 by craig.topper
[RISCV] Remove unused RISCV::VLEFF and VLEFF_MASK. NFC

Looks like these got left behind when vleff isel was moved to
X86ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit f0adf3a24cdedb4c48e49a8792c5cfbd40ba3345 by stefanp
[PowerPC][LLD] Make sure that the correct Thunks are used.

This fixes an issue where mixed TOC / NOTOC calls can call the incorrect
thunks if a previous thunk already exists. The issue appears when a TOC
funciton calls a NOTOC callee and then a different NOTOC function calls the same
NOTOC callee. In this case the linker would sometimes incorrectly call the
same thunk for both cases.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D101837
The file was addedlld/test/ELF/ppc64-pcrel-cross-link.s
The file was modifiedlld/ELF/Thunks.cpp
Commit b198b9b8974b19c9e8493f8d70c85ac54182597a by tlively
[WebAssembly] Fix argument types in SIMD narrowing intrinsics

The builtins were updated to take signed parameters in 627a52695537, but the
intrinsics that use those builtins were not updated as well. The intrinsic test
did not catch this sign mismatch because it is only reported as an error under
-fno-lax-vector-conversions.

This commit fixes the type mismatch and adds -fno-lax-vector-conversions to the
test to catch similar problems in the future.

Differential Revision: https://reviews.llvm.org/D101979
The file was modifiedclang/test/Headers/wasm.c
The file was modifiedclang/lib/Headers/wasm_simd128.h
Commit 52525cb20ff300d634453fdb3986adf4801f205c by thomasraoux
[mlir][linalg][NFC] Make reshape folding control more fine grain

This expose a lambda control instead of just a boolean to control unit
dimension folding.
This however gives more control to user to pick a good heuristic.
Folding reshapes helps fusion opportunities but may generate sub-optimal
generic ops.

Differential Revision: https://reviews.llvm.org/D101917
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
Commit 71eb32d97ea0c8ccac36287f6c46e582f93dc1f3 by thomasraoux
[mlir][vector] Fix typo
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
Commit 642df18f1437b1fffea2343fa471aebfff128c6e by aeubanks
[gn build] Support compiler-rt/profile on Windows

Reviewed By: thakis

Differential Revision: https://reviews.llvm.org/D101961
The file was modifiedllvm/utils/gn/secondary/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/compiler-rt/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/compiler-rt/lib/BUILD.gn
The file was modifiedllvm/utils/gn/build/toolchain/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/compiler-rt/target.gni
Commit 199a623ebf808a01e920ebd9904c99e633c33a1f by pklausler
[flang] Runtime must defer formatted/unformatted determination

What the Fortran standard calls "preconnected" external I/O units
might not be known to be connected to unformatted or formatted files
until the first I/O data transfer statement is executed.
Support this deferred determination by representing the flag as
a tri-state Boolean and adapting its points of use.

Differential Revision: https://reviews.llvm.org/D101929
The file was modifiedflang/runtime/connection.h
The file was modifiedflang/runtime/unit.cpp
The file was modifiedflang/runtime/io-stmt.cpp
The file was modifiedflang/runtime/io-api.cpp
The file was modifiedflang/runtime/unit.h
Commit 22aece57beb6eab43f4f88d565d5cec1934fe36e by matthew.voss
Allow llvm-dis to disassemble multiple files

Differential Revision: https://reviews.llvm.org/D101110
The file was addedllvm/test/tools/llvm-dis/multiple-files.ll
The file was modifiedllvm/tools/llvm-dis/llvm-dis.cpp
Commit 4f41994c13741b8ffe0c0cc9f6474eabc1293d89 by pklausler
[flang] Fix race condition in runtime

The code that initializes the default units 5 & 6 had
a race condition that would allow threads access to the
unit map before it had been populated.

Also add some missing calls to va_end() that will never
be called (they're in program abort situations) but might
elicit warnings if absent.

Differential Revision: https://reviews.llvm.org/D101928
The file was modifiedflang/runtime/unit.cpp
The file was modifiedflang/runtime/io-error.cpp
The file was modifiedflang/runtime/terminator.cpp
Commit 306370be0bf2257124c262ae5c8a7a7180eb42a0 by i
[AArch64] Fix namespace issue. NFC
The file was modifiedllvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp
Commit 6a1c3efa051e012aaf102b7d9e7e428a58ea8ad9 by pklausler
[flang] Implement NAMELIST I/O in the runtime

Add InputNamelist and OutputNamelist as I/O data transfer APIs
to be used with internal & external list-directed I/O; delete the
needless original namelist-specific Begin... calls.
Implement NAMELIST output and input; add basic tests.

Differential Revision: https://reviews.llvm.org/D101931
The file was modifiedflang/runtime/descriptor.cpp
The file was modifiedflang/runtime/io-api.h
The file was modifiedflang/runtime/unit.cpp
The file was modifiedflang/unittests/RuntimeGTest/NumericalFormatTest.cpp
The file was modifiedflang/runtime/format.h
The file was addedflang/runtime/namelist.cpp
The file was addedflang/unittests/RuntimeGTest/Namelist.cpp
The file was modifiedflang/include/flang/ISO_Fortran_binding.h
The file was modifiedflang/runtime/connection.h
The file was modifiedflang/runtime/CMakeLists.txt
The file was modifiedflang/runtime/descriptor.h
The file was addedflang/runtime/namelist.h
The file was modifiedflang/runtime/connection.cpp
The file was modifiedflang/runtime/descriptor-io.h
The file was modifiedflang/unittests/RuntimeGTest/tools.h
The file was modifiedflang/runtime/edit-output.cpp
The file was modifiedflang/runtime/io-stmt.cpp
The file was modifiedflang/runtime/io-stmt.h
The file was modifiedflang/unittests/RuntimeGTest/CMakeLists.txt
The file was modifiedflang/lib/Lower/RTBuilder.h
The file was modifiedflang/runtime/edit-input.cpp
The file was modifiedflang/lib/Lower/IO.cpp
The file was modifiedflang/runtime/io-api.cpp
Commit a577d59db243c1be038f331e0057a37b777a4407 by craig.topper
[RISCV] Minor vector instruction tablegen cleanup. NFC

Use result_type for the IMPLICIT_DEF in masked vector patterns.
This doesn't matter today because result_type and op_type are
always the same.

Use multiclass inheritance to reduce repeated code.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Commit 8408d3f2d814b19da450ff162f47981b55a9703a by xingxue
[libunwind] NFC: Use macros to accommodate differences in representation of PowerPC assemblers

Summary:
This NFC patch replaces the representation of registers and the left shift operator in the PowerPC assembly code to allow it to be consumed by the GNU flavored assembler and the AIX assembler.

* Registers - change the representation of PowperPC registers from %rn, %fn, %vsn, and %vrn to the register number alone, e.g., n. The GNU flavored assembler and the AIX assembler are able to determine the register kind based on the context of the instruction in which the register is used.

* Left shift operator - use macro PPC_LEFT_SHIFT to represent the left shift operator. The left shift operator in the AIX assembly language is < instead of <<

Reviewed by: sfertile, MaskRay, compnerd

Differential Revision: https://reviews.llvm.org/D101179
The file was modifiedlibunwind/src/UnwindRegistersRestore.S
The file was modifiedlibunwind/src/assembly.h
The file was modifiedlibunwind/src/UnwindRegistersSave.S
Commit 8cb191b724b734a7432a63eb49f54cb9f4333d51 by phosek
[Fuchsia][CMake] Update OSX deployment target

Use correct spelling of CMAKE_OSX_DEPLOYMENT_TARGET and bump the
minimum version to 10.13 which matches what we use for host tools
in Fuchsia.

Differential Revision: https://reviews.llvm.org/D102013
The file was modifiedclang/cmake/caches/Fuchsia-stage2.cmake
The file was modifiedclang/cmake/caches/Fuchsia.cmake
Commit a40b609958828960ce55a5e266c157491772a67e by arnamoy.bhattacharyya
[flang][OpenMP] Add semantic check for occurrence of constructs nested inside a SIMD region

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D99757
The file was modifiedflang/lib/Semantics/check-directive-structure.h
The file was addedflang/test/Semantics/omp-nested-simd.f90
The file was modifiedflang/test/Semantics/omp-do05.f90
The file was modifiedflang/lib/Semantics/check-omp-structure.h
The file was modifiedflang/test/Semantics/omp-ordered-simd.f90
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
Commit 191ffda3f70b1a66794cbc8ce4e77b206041a18e by craig.topper
[RISCV] Remove unused ComplexPatterns. NFC
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
Commit 97ab068034161fb35e5c9a7b293bf1e569cf077b by mtrofin
[NPM] Do not run function simplification pipeline unnecessarily

The CGSCC pass manager interplay with the FunctionAnalysisManagerCGSCCProxy is 'special' in the sense that the former will rerun the latter if there are changes to a SCC structure; that being said, some of the functions in the SCC may be unchanged. In that case, the function simplification pipeline will be re-run, which impacts compile time[1].

This patch allows the function simplification pipeline be skipped if it was already run and the function was not modified since.

The behavior is currently disabled by default. This is because, currently, the rerunning of the function simplification pipeline on an unchanged function may still result in changes. The patch simplifies investigating and fixing those cases where repeated function pass runs do actually positively impact code quality, while offering an easy workaround for those impacted negatively by compile time regressions, and not impacting mainline scenarios.

[1] A [[ http://llvm-compile-time-tracker.com/compare.php?from=eb37d3546cd0c6e67798496634c45e501f7806f1&to=ac722d1190dc7bbdd17e977ef7ec95e69eefc91e&stat=instructions | compile time tracker ]] run with the option enabled.

Differential Revision: https://reviews.llvm.org/D98103
The file was modifiedllvm/lib/Analysis/CGSCCPassManager.cpp
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/unittests/Analysis/CGSCCPassManagerTest.cpp
The file was modifiedllvm/include/llvm/Analysis/CGSCCPassManager.h
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was addedllvm/test/Other/new-pass-manager-cgscc-fct-proxy.ll
Commit fefcb1f878c2dad435af604955661ca02a5302de by spatel
[PassManager] add helper function to hold set of vector passes

This is no-functional-change-intended (NFC) and split off from
D102002 (which proposes to eliminate the LTO-based differences).
The file was modifiedllvm/lib/Transforms/IPO/PassManagerBuilder.cpp
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/include/llvm/Passes/PassBuilder.h
The file was modifiedllvm/include/llvm/Transforms/IPO/PassManagerBuilder.h
Commit 6304c0836a4dd2d77373d45716092b2a088fa948 by riddleriver
[mlir] Store the flag for dynamic operand storage in the low bits

It is currently stored in the high bits, which is disallowed on certain
platforms (e.g. android). This revision switches the representation to use
the low bits instead, fixing crashes/breakages on those platforms.

Differential Revision: https://reviews.llvm.org/D101969
The file was modifiedmlir/lib/IR/OperationSupport.cpp
The file was modifiedmlir/include/mlir/IR/OperationSupport.h
Commit a3a8a1a15b524d91b5308db68e9d293b34cd88dd by kyrtzidis
[Index] Ignore nullptr decls for indexing

We can end up with a call to `indexTopLevelDecl(D)` with `D == nullptr` in non-assert builds e.g. when indexing a module in `indexModule` and
- `ASTReader::GetDecl` returns `nullptr` if `Index >= DeclsLoaded.size()`, thus returning `nullptr`
=> `ModuleDeclIterator::operator*` returns `nullptr`
=> we call `IndexCtx.indexTopLevelDecl` with `nullptr`

Be resilient and just ignore the `nullptr` decls during indexing.

Reviewed By: akyrtzi

Differential Revision: https://reviews.llvm.org/D102001
The file was modifiedclang/lib/Index/IndexDecl.cpp
Commit 83af66e18e3d3760d56ea7e3bdbff3428ae7730d by aaron
new altera ID dependent backward branch check

This lint check is a part of the FLOCL (FPGA Linters for OpenCL) project
out of the Synergy Lab at Virginia Tech.

FLOCL is a set of lint checks aimed at FPGA developers who write code
in OpenCL.

The altera ID dependent backward branch lint check finds ID dependent
variables and fields used within loops, and warns of their usage. Using
these variables in loops can lead to performance degradation.
The file was addedclang-tools-extra/clang-tidy/altera/IdDependentBackwardBranchCheck.h
The file was modifiedclang-tools-extra/clang-tidy/altera/AlteraTidyModule.cpp
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/list.rst
The file was addedclang-tools-extra/test/clang-tidy/checkers/altera-id-dependent-backward-branch.cpp
The file was addedclang-tools-extra/clang-tidy/altera/IdDependentBackwardBranchCheck.cpp
The file was modifiedclang-tools-extra/docs/ReleaseNotes.rst
The file was addedclang-tools-extra/docs/clang-tidy/checks/altera-id-dependent-backward-branch.rst
The file was modifiedclang-tools-extra/clang-tidy/altera/CMakeLists.txt
Commit fca10c8808ff22f3069359b2f6b2d410612c70c1 by llvmgnsyncbot
[gn build] Port 83af66e18e3d
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clang-tidy/altera/BUILD.gn
Commit d21e1b79ff7d40bca537c30da706e31e48483f21 by aaron.puchert
Thread safety analysis: Eliminate parameter from intersectAndWarn (NFC)

We were modifying precisely when intersecting the lock sets of multiple
predecessors without back edge. That's no coincidence: we can't modify
on back edges, it doesn't make sense to modify at the end of a function,
and otherwise we always want to intersect on forward edges, because we
can build a new lock set for those.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D101755
The file was modifiedclang/lib/Analysis/ThreadSafety.cpp
Commit 72ba78c29e923cb6e5d89eb5ea8180bf723188be by jingham
When SendContinuePacketAndWaitForResponse returns eStateInvalid, don't fetch more packets.

This looks like just an oversight in the AsyncThread function.  It gets a result of
eStateInvalid, and then marks the process as exited, but doesn't set "done" to true,
so we go to fetch another event.  That is not safe, since you don't know when that
extra packet is going to arrive.  If it arrives while you are tearing down the
process, the internal-state-thread might try to handle it when the process in not
in a good state.

Rather than put more effort into checking all the shutdown paths to make sure this
extra packet doesn't cause problems, just don't fetch it.  We weren't going to do
anything useful with it anyway.

The main part of the patch is setting "done = true" when we get the eStateInvalid.
I also added a check at the beginning of the while(done) loop to prevent another error
from getting us to fetch packets for an exited process.

I added a test case to ensure that if an Interrupt fails, we call the process
exited.  I can't test exactly the error I'm fixing, there's no good way to know
that the stop reply for the failed interrupt wasn't fetched.  But at least this
asserts that the overall behavior is correct.

Differential Revision: https://reviews.llvm.org/D101933
The file was modifiedlldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
The file was addedlldb/test/API/functionalities/gdb_remote_client/TestHaltFails.py
Commit 41bc54cc56fd9e9cdaaeb9ca630f0c690e1a28e4 by antiagainst
[mlir][spirv] NFC: Replace OwningSPIRVModuleRef with OwningOpRef

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D102009
The file was modifiedmlir/include/mlir/Dialect/SPIRV/Linking/ModuleCombiner.h
The file was modifiedmlir/unittests/Dialect/SPIRV/SerializationTest.cpp
The file was modifiedmlir/unittests/Dialect/SPIRV/DeserializationTest.cpp
The file was removedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVModule.h
The file was modifiedmlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
The file was modifiedmlir/lib/Target/SPIRV/TranslateRegistration.cpp
The file was modifiedmlir/include/mlir/Target/SPIRV/Deserialization.h
The file was modifiedmlir/lib/Target/SPIRV/Deserialization/Deserializer.h
The file was modifiedmlir/lib/Dialect/SPIRV/Linking/ModuleCombiner/ModuleCombiner.cpp
The file was modifiedmlir/test/lib/Dialect/SPIRV/TestModuleCombiner.cpp
The file was modifiedmlir/lib/Target/SPIRV/Deserialization/Deserialization.cpp
The file was modifiedmlir/test/lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp
Commit 7e9351b9dee225b9ab12ee9bbfc9f8b96ddd1a1d by jonathanchesterfield
[libomptarget][amdgpu][nfc] Remove dead code from amdgpu plugin

[libomptarget][amdgpu][nfc] Remove dead code from amdgpu plugin

Drops an enum that was identical to a HSA one, localises some functions where
they were only called from one TU. Covers everything internalize + adce can
identify as dead, except for msgpack::dump which is useful when debugging.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D102014
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/atmi.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/system.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/internal.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/data.cpp
Commit 9ff38e2d9dd791383fbaa80e02d65e9c1f0463ff by malhar.jajoo
[ARM] Transforming memcpy to Tail predicated Loop

This patch converts llvm.memcpy intrinsic into Tail Predicated
Hardware loops for a target that supports the Arm M-profile
Vector Extension (MVE).

From an implementation point of view, the patch

- adds an ARM specific SDAG Node (to which the llvm.memcpy intrinsic is lowered to, during first phase of ISel)
- adds a corresponding TableGen entry to generate a pseudo instruction, with a custom inserter,
  on matching the above node.
- Adds a custom inserter function that expands the pseudo instruction into MIR suitable
   to be (by later passes) into a WLSTP loop.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D99723
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was addedllvm/test/CodeGen/Thumb2/mve-tp-loop.mir
The file was modifiedllvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.h
The file was addedllvm/test/CodeGen/Thumb2/mve-tp-loop.ll
The file was modifiedllvm/lib/Target/ARM/ARMSubtarget.h
Commit 5dc1ed3f627ecfad119ada84d3534cc21b80f810 by sergei.grechanik
[mlir] Update dstNode after DenseMap insertion in loop fusion pass.

Reviewed By: vinayaka-polymage

Differential Revision: https://reviews.llvm.org/D101794
The file was modifiedmlir/lib/Transforms/LoopFusion.cpp
The file was modifiedmlir/test/Transforms/loop-fusion.mlir
Commit 44ee974e2f3ef120e1890d8aafb02fedc3c135e9 by jonathanchesterfield
[libomptarget][nfc] Refactor amdgpu partial barrier to simplify adding a second one

[libomptarget][nfc] Refactor amdgpu partial barrier to simplify adding a second one

D101976 would require a second barrier instance. This NFC to amdgpu makes it
simpler to add one (an extra global, one more line in init). Also renames the
current barrier to L0.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D102016
The file was modifiedopenmp/libomptarget/deviceRTLs/amdgcn/src/target_impl.hip
Commit d3e987c38917758fe5cf1e27ed26d08f0e9c0fe3 by rob.suderman
[mlir][tosa] Added div op, variadic concat. Removed placeholder. Spec v0.22 alignment.

Nearly complete alignment to spec v0.22
- Adds Div op
- Concat inputs now variadic
- Removes Placeholder op

Note: TF side PR https://github.com/tensorflow/tensorflow/pull/48921 deletes Concat legalizations to avoid breaking TensorFlow CI. This must be merged only after the TF PR has merged.

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D101958
The file was modifiedmlir/test/Dialect/Tosa/ops.mlir
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
Commit c714d037857f9c8e3bbe32e22ec22279121c378d by Stanislav.Mekhanoshin
[AMDGPU] Expose __builtin_amdgcn_perm for v_perm_b32

Differential Revision: https://reviews.llvm.org/D102022
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
The file was modifiedclang/test/SemaOpenCL/builtins-amdgcn-error-vi.cl
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedclang/include/clang/Basic/BuiltinsAMDGPU.def
The file was addedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.perm.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsAMDGPU.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit c4ed142e695f14ba5675ec6d12226ee706329a0f by Cyndy Ishida
[llvm][TextAPI] add mapping from OS string to Platform

* add utility for matching target triple OS value strings  to PlatformKind

This was reviewed offline by ributzka, steven_wu
The file was modifiedllvm/include/llvm/TextAPI/Platform.h
The file was modifiedllvm/lib/TextAPI/Platform.cpp
The file was modifiedllvm/unittests/TextAPI/TextStubV4Tests.cpp
Commit 87a6325fbe4315f3f24555797f216e96539a9397 by jianzhouzh
[dfsan] Rename and fix an internal test issue for mmap+calloc

The linker suggests using -Wl,-z,notext.

Replaced assert by exit also fixed this.

After renaming, interceptor.c would be used to test interceptors in general by D101204.

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D101649
The file was removedcompiler-rt/test/dfsan/interceptors.c
The file was addedcompiler-rt/test/dfsan/mmap_at_init.c
Commit 05a89312d812bb5dcec6deca8f1e28a198ce1167 by ravishankarm
[mlir][Linalg] Allow folding to rank-zero tensor when using rank-reducing subtensors.

The pattern to convert subtensor ops to their rank-reduced versions
(by dropping unit-dims in the result) can also convert to a zero-rank
tensor. Handle that case.
This also fixes a OOB access bug in the existing pattern for such
cases.

Differential Revision: https://reviews.llvm.org/D101949
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
The file was modifiedmlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
Commit 819e0d105e84c6081cfcfa0e38fd257b6124553a by bruno.cardoso
[CGAtomic] Lift strong requirement for remaining compare_exchange combinations

Follow up on 431e3138a and complete the other possible combinations.

Besides enforcing the new behavior, it also mitigates TSAN false positives when
combining orders that used to be stronger.
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedclang/test/CodeGen/atomic-ops.c
The file was modifiedclang/test/CodeGenOpenCL/atomic-ops.cl
The file was modifiedclang/lib/CodeGen/CGAtomic.cpp
The file was modifiedllvm/lib/IR/Instructions.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
Commit e388b9399b03a78219adb3488ec8b2e2a6abcf46 by qixingxue
[IR] Fix typo in comment of Intrinsics.td (NFC)
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
Commit e6cf3d64412c1ddd2fcece337fe0a5f80e386a48 by coelacanthus
[TableGen] Use range-based for loops (NFC)

Use range-based for loops in TableGen.

Reviewed By: Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D101994
The file was modifiedllvm/utils/TableGen/DFAPacketizerEmitter.cpp
The file was modifiedllvm/utils/TableGen/FixedLenDecoderEmitter.cpp
The file was modifiedllvm/utils/TableGen/AsmWriterEmitter.cpp
The file was modifiedllvm/utils/TableGen/FastISelEmitter.cpp
The file was modifiedllvm/utils/TableGen/RegisterInfoEmitter.cpp
The file was modifiedllvm/utils/TableGen/GICombinerEmitter.cpp
The file was modifiedllvm/utils/TableGen/AsmMatcherEmitter.cpp
The file was modifiedllvm/utils/TableGen/CodeGenRegisters.cpp
The file was modifiedllvm/utils/TableGen/InstrInfoEmitter.cpp
The file was modifiedllvm/utils/TableGen/RISCVCompressInstEmitter.cpp
The file was modifiedllvm/utils/TableGen/CodeGenSchedule.cpp
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was modifiedllvm/utils/TableGen/X86DisassemblerTables.cpp
Commit 605c811d2b0f71c576740c9a54629804353bf67a by yhs
BPF: fix FIELD_EXISTS relocation with array subscripts

Lorenz Bauer reported an issue in bpf mailing list ([1]) where
for FIELD_EXISTS relocation, if the object is an array subscript,
the patched immediate is the object offset from the base address,
instead of 1.

Currently in BPF AbstractMemberAccess pass, the final offset
from the base address is the patched offset except FIELD_EXISTS
which is 1 unconditionally. In this particular case, the last
data structure access is not a field (struct/union offset)
so it didn't hit the place to set patched immediate to be 1.

This patch fixed the issue by checking the relocation type.
If the type is FIELD_EXISTS, just set to 1.
Tested by modifying some bpf selftests, libbpf is okay with
such types with FIELD_EXISTS relocation.

[1] https://lore.kernel.org/bpf/CACAyw99n-cMEtVst7aK-3BfHb99GMEChmRLCvhrjsRpHhPrtvA@mail.gmail.com/

Differential Revision: https://reviews.llvm.org/D102036
The file was addedllvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-4.ll
The file was modifiedllvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
Commit f7294ac8093a2fbd8c00254580eaac6c4e1f7b24 by qiucofan
[PowerPC] Remove extra swap for extract+vperm on LE

This is a simple fix on LE. On BE, vector shuffles are categorized into
different ops. We may need more work to eliminate these in
tablegen/pre-isel.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D101605
The file was modifiedllvm/test/CodeGen/PowerPC/vec_extract_p9.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
Commit 26e916334ebc3cb34f1c020e00c731bd60b0323a by gysit
[mlir][linalg] Add IndexedGenericOp to GenericOp canonicalization.

Replace all `linalg.indexed_generic` ops by `linalg.generic` ops that access the iteration indices using the `linalg.index` op.

Differential Revision: https://reviews.llvm.org/D101612
The file was modifiedmlir/test/Dialect/Linalg/fusion-tensor.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
The file was modifiedmlir/test/Dialect/Linalg/fusion-indexed-generic.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/tile-indexed-generic.mlir
The file was modifiedmlir/test/Dialect/Linalg/canonicalize-duplicate-inputs.mlir
The file was modifiedmlir/test/Dialect/Linalg/tile-tensors.mlir
The file was modifiedmlir/test/Dialect/Linalg/bufferize.mlir
The file was modifiedmlir/test/Dialect/Linalg/reshape_fusion.mlir
Commit a95473c563bf5b6d657f5e5fa99bd551b2df339b by czhengsz
[XCOFF] handle string constants generation for AIX

This follows https://www.ibm.com/docs/en/aix/7.2?topic=constants-string

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D101280
The file was modifiedllvm/lib/MC/MCAsmInfoXCOFF.cpp
The file was modifiedllvm/lib/MC/MCAsmStreamer.cpp
The file was addedllvm/test/CodeGen/PowerPC/aix-filename-special-character-double-quotation.ll
The file was modifiedllvm/include/llvm/MC/MCAsmInfo.h
The file was addedllvm/test/CodeGen/PowerPC/aix-filename-special-character-single-quotation.ll