Build #1848 (May 10, 2021 10:01:58 PM)

1. [MLIR][SPIRV] Properly (de-)serialize BranchConditionalOp. (details)
2. [GlobalISel] Micro-optimize the conditional branch optimization. (details)
3. [Debug-Info][NFC] add a wrapper for Die.addValue (details)
4. [LazyValueInfo] Insert an Overdefined placeholder to prevent infinite recursion (details)
5. [libcxx] Fix a case of -Wundef warnings. NFC. (details)
6. [lit][test] Attempt fix when paths include symlink (details)
7. [LoopVectorize][SVE] Remove assert for scalable vector in InnerLoopVectorizer::fixReduction (details)
8. [flang] Add tests for MIN for character arrays. NFC (details)
9. [flang] Remove redundant reallocation (details)
10. [AMDGPU] Serialize MFInfo::ScavengeFI (details)
11. [gn build] Port 98e5ede60499 (details)
12. [AsmParser][ARM] Make .thumb_func imply .thumb (details)
13. [llvm][NFC] Remove deprecated TargetFrameLowering and InstrTypes alignment functions (details)
14. [llvm][NFC] Remove remaining deprecated alignment functions from CodeGen (details)
15. [llvm-dwarfdump] Help option output should be consistent with the command guide (details)
16. [DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST (details)
17. [NFC][X86][MCA] AMD Zen 3: add tests with eliminatible GPR moves (details)
18. [X86] AMD Zen 3: 32/64 -bit GPR register moves are zero-cycle (details)
19. [NFC][X86][MCA] AMD Zen 3: add tests with non-eliminatible MMX moves (details)
20. AMDGPU: Correct const_index_stride for wave 32 for PAL ABI (details)
21. [NFC] (test commit) Changed example invocation of C++ for OpenCL (details)
22. [X86] Ensure we pass DebugLoc by const reference where possible. NFCI. (details)
23. [SLP] Regenerate tests to reduce diff in D98714. NFCI. (details)
24. Revert "AMDGPU: Correct const_index_stride for wave 32 for PAL ABI" (details)
25. [DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts (details)
26. [DebugInfo] Fix crash when emitting an invalidated SDDbgValue (details)
27. [NFC] Correctly assert the indents for printEnumValHelpStr. (details)
28. [OpenCL] Fix optional image types. (details)
29. [ARM] Transforming memset to Tail predicated Loop (details)
30. Fix: [DebugInfo] Fix crash when emitting an invalidated SDDbgValue (details)
31. AMDGPU: Correct const_index_stride for wave 32 for PAL ABI (details)
32. [AMDGPU] Restrict immediate scratch offsets (details)
33. Retire TargetRegisterInfo::getSpillAlignment (details)
34. [DAG] Ensure all SD classes consistently return a const reference with getDebugLoc(). NFCI. (details)
35. [CodeGen] Ensure UserValue::getDebugLoc() and UserLabel::getDebugLoc() consistently return a const reference NFCI. (details)
36. Reapply "[DebugInfo] Drop DBG_VALUE_LISTs with an excessive number of debug operands" (details)
37. [libc++] [test] Test that list::swap/move/move-assign does not invalidate iterators. (details)
38. [libc++] [test] Simplify arithmetic in list.special/swap.pass.cpp. NFCI. (details)
39. [libc++] [test] Test that unordered_*::swap/move/assign does not invalidate iterators. (details)
40. [NFC][X86][MCA] Increase iteration count in reg move elimination tests (details)
41. [NFC][X86] AMD Zen 3: move sched classes for renameables moves togeter (details)
42. [X86] AMD Zen 3: throughput for renameable GPR moves is 6 (details)
43. [NFC][X86][MCA] AMD Zen 3: Add tests for renameable SSE XMM moves (details)
44. [NFC][X86][MCA] AMD Zen 3: Add tests for renameable AVX XMM moves (details)
45. [NFC][X86][MCA] AMD Zen 3: Add tests for renameable AVX YMM moves (details)
46. [X86] AMD Zen 3: SSE XMM moves are zero-cycle (details)
47. [X86] AMD Zen 3: AVX XMM moves are zero-cycle (details)
48. [X86] AMD Zen 3: AVX YMM moves are zero-cycle (details)
49. [X86] AMD Zen 3: throughput for renameable XMM/YMM moves is 6 (details)
50. [NFC][X86][MCA] AMD Zen3 Decrease iteration count in reg-move-elimination tests (details)
51. [PowerPC] Provide MMA builtins for compatibility (details)
52. [mlir] Rename BufferAliasAnalysis to BufferViewFlowAnalysis (details)
53. [mlir][linalg] Remove redundant indexOp builder. (details)
54. [libomptarget] Add support for target memory allocators to cuda RTL (details)
55. [AArch64] add test for missed vectorization; NFC (details)
56. BasicAA: Recognize inttoptr as isEscapeSource (details)
57. [mlir][spirv] add support lowering of extract_slice to scalar type (details)
58. [mlir][vector] add pattern to cast away leading unit dim for elementwise op (details)
59. [libFuzzer] Fix stack overflow detection (details)
60. [NFC][X86][MCA] AMD Zen3: add test for zero-cycle X87 move (details)
61. [X86] AMD Zen 3: _REV variants of zero-cycles moves are also zero-cycles (PR50261) (details)
62. [X86] combineXor - limit fold to non-opaque constants (PR50254) (details)
63. [LoopNest] Consider loop nest with inner loop guard using outer loop (details)
64. [libFuzzer] Fix stack-overflow-with-asan.test. (details)
65. [AArch64][ELF] Prefer to lower MC_GlobalAddress operands to .Lfoo$local (details)
66. [X86] AMD Zen 3: MOVSX32rr32 is a zero-cycle move (details)
67. [X86] AMD Zen 3: mark XMM/YMM (but not MMX!) reg moves as eliminatible in RegisterFile (details)
68. lit: revert 134b103fc0f3a995d76398bf4b029d72bebe8162 (details)
69. [libc++][ci] Run longer CI jobs first (details)
70. Internalize some cl::opt global variables or move them under namespace llvm (details)
71. Allow empty value list in propagateMetadata(Inst, ArrayOf...) (details)
72. [unittest] Fix -Wunused-variable after D94717 (details)
73. [WebAssembly] Use functions instead of macros for const SIMD intrinsics (details)
74. [SCEV] By more careful when traversing phis in isImpliedViaMerge. (details)
75. Revert "[DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST" (details)
76. [mlir][docs] remove stale statement about index type in vectors (details)
77. [mlir] Add a pattern to bufferize linalg.tensor_reshape. (details)
78. [mlir] Add a pattern to bufferize std.index_cast. (details)
79. An attempt to abandon omptarget out-of-tree builds. (details)
80. [RISCV] Consider scalar types for required extensions. (details)
81. [BareMetal] Ensure that sysroot always comes after library paths (details)
82. [flang] Implement NORM2 in the runtime (details)
83. [LV] Rename Region to TargetRegion, similar to SinkRegion (NFC). (details)
84. [LV] Assert if trying to sink replicate region into another region (NFC) (details)
85. [SEH] Fix regression with SEH in noexpect functions (details)
86. [MCA][RegisterFile] Fix register class check for move elimination (PR50265) (details)
87. [LV] Remove reference of PHI from comment, they are not recorded (NFC). (details)
88. Revert "[BareMetal] Ensure that sysroot always comes after library paths" (details)
89. [mlir][vector] Extend pattern to trim lead unit dimension to Splat Op (details)
90. [mlir] Missed clang-format (details)
91. [lld/mac] Write every weak symbol only once in the output (details)
92. [BareMetal] Ensure that sysroot always comes after library paths (details)
93. Fix the module-enabled build by removing a redundant type definition. (details)
94. [AArch64][GlobalISel] Legalize narrow type G_CTPOPs (details)
95. [NewPM] Move analysis invalidation/clearing logging to instrumentation (details)
96. NFC: Move TypeList implementation up the file (details)
97. Make `hasTypeLoc` matcher support more node types. (details)
98. [GlobalISel] Don't form zero/sign extending loads for atomics. (details)
99. [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0. (details)
100. [mlir][vector] Fix warning (details)
101. [gn build] Manually port 5b158093e (details)
102. Revert "lit: revert 134b103fc0f3a995d76398bf4b029d72bebe8162" (details)
103. [mlir] Add hover support to mlir-lsp-server (details)
104. [lit] Bump up the Windows process cap from 32 to 60 (details)
105. [mlir] Refactor the representation of function-like argument/result attributes. (details)
106. [DebugInfo] UnwindTable::create() should not add empty rows to CFI unwind table (details)
107. [NewPM] Hide pass manager debug logging behind -debug-pass-manager-verbose (details)
108. Replace a remaining CRLF with LF. NFC. (details)
109. [X86] Support AMX fast register allocation (details)
110. Revert "[X86] Support AMX fast register allocation" (details)
111. Fix build after 34a8a437b (details)
112. [X86] Support AMX fast register allocation (details)
113. [mlir] Debug print pattern before and after matchAndRewrite call (details)
114. [VectorCombine] Simplify to scalar store if only one element updated (details)
115. [libc++] Use Xcode's CMake if it's present (details)
116. [X86] Improve costmodel for scalar byte swaps (details)
117. Revert "[LICM] Hoist loads with invariant.group metadata" (details)
118. [MLIR][NFC] Remove unused MLIRContext declaration (details)
119. [MLIR] Add memref dialect dependency for affine fusion pass (details)
120. [libc++] Move handling of the target triple to the DSL (details)
121. [X86] combineHorizOpWithShuffle - generalize HOP(SHUFFLE(X),SHUFFLE(Y)) -> SHUFFLE(HOP(X,Y)) fold. (details)
122. [GlobalISel] Ensure MachineIRBuilder::getDebugLoc() returns a const reference. NFCI. (details)
123. [VPlan] Add test for sink scalars and merging using VPlan. (details)
124. [libc++] NFC: Refactor Lit annotations (details)
125. [lld/mac] Copy some of the commit message of d5a70db193 into a comment (details)
126. [MCA][RegisterFile] Refactor the move elimination logic to address PR50258. (details)
127. [lld-macho] Explicitly undefine literal exported symbols (details)
128. [llvm-mca][View] Update the Register File statistics. (details)
129. [Hexagon] Propagate metadata in Hexagon Vector Combine (details)
130. [test] Fix tools/gold/X86/new-pm.ll after D101797 (details)
131. [NFCI][X86] Mark a few lately-added system instructions as such for Scheduling purposes (details)
132. [NFCI][X86] Mark Znver3 scheduling model as complete (details)
133. [NFC][LoopIdiom] Add some tests for 'lshr until zero' ('count active bits') "on steroids" idiom (details)
134. [lld-macho][NFC] Purge stale test-output trees prior to split-file (details)
135. [libc++][doc] Update the Format library status. (details)
136. [SROA] Regenerate test checks (NFC) (details)
137. [SelectionDAG] Regenerate test checks (NFC) (details)
138. [X86] AMD Zen 3: XCHG is a zero-cycle instruction (details)
139. [NFC][X86] Znver3: drop obsolete fixme (details)
140. [SCEV] Add additional loop guard and/or tests (NFC) (details)
141. [SCEV] Handle and/or in applyLoopGuards() (details)
142. [ARM] Fix postinc of vst1xN (details)
143. [NFC][X86][MCA] AMD Zen3: add GPR zero-idiom dependency breaking tests (details)
144. [X86] AMD Zen 3: same-register XOR/SUB are GPR dependency breaking zero-idioms (details)
145. [NFC][X86][MCA] AMD Zen 3: add tests for SBB dependency breaking (details)
146. [X86] AMD Zen 3: same-reg SBB is a dependency-breaking instruction (details)
147. [NFC][X86][MCA] AMD Zen 3: add tests for CMP dependency breaking (details)
148. [X86] AMD Zen 3: same-reg CMP is a zero-cycle dependency-breaking instruction (details)
149. [Demangle][Rust] Print special namespaces (details)
150. [lld-macho] Don't reference entry symbol for non-executables (details)
151. [lld/mac] Fix alignment on subsections (details)
152. [lld-macho] Add llvm-otool as a test dependency (details)
153. Support NativeCodeCall binding in rewrite pattern. (details)
154. [RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter. (details)
155. [NFC][Coroutines] Fix two tests by removing hardcoded SSA value. (details)
156. [SimplifyCFG] Ignore ephemeral values when counting insts for threading (details)
157. [ORC] Generalize materialization dispatch to task dispatch. (details)
158. [ORC] Use the new dispatchTask API to run query callbacks. (details)
159. [AArch64][SVE] Remove index_vector node. (details)
160. [mlir] Fix compile error. (details)
161. [LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion (details)
162. [amdgpu-arch] Guard hsa.h with __has_include (details)
163. [AMDGPU][OpenMP] Disable tests when amdgpu-arch fails (details)
164. [libc] Allow target architecture customization (details)
165. [AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S (details)
166. [mlir] OpenMP-to-LLVM: properly set outer alloca insertion point (details)
167. AMDGPU/GlobalISel: Add regbankselect test for vgpr(dest) sgpr(address) load (details)
168. AMDGPU/GlobalISel: Use destination register bank in applyMappingLoad (details)
169. [libc] Simplifies multi implementations and benchmarks (details)
170. [MLIR][Shape] Concretize broadcast result type if possible (details)
171. [compiler-rt] Handle None value when polling addr2line pipe (details)
172. Fixed bug in buffer deallocation pass using unranked memref types. (details)
173. [OpenMP][MLIR]Add support for guided, auto and runtime scheduling (details)
174. [clang][PreProcessor] Cutoff parsing after hitting completion point (details)
175. HexagonVectorCombine.cpp - don't negate a bool value. NFCI. (details)
176. [AArch64][SVE] Fix isel failure for FP-extending loads (details)
177. [GlobalISel] Fix wrong invocation of `getParamStackAlign` (NFC) (details)
178. [AArch64][SVE] Better utilisation of unpredicated forms of arithmetic intrinsics (details)
179. [AArch64][SVE] Better utilisation of unpredicated forms of remaining intrinsics (details)
180. clang: Fix tests after 7f78e409d028 if clang is not called clang-13 (details)
181. [NFC][llvm-dwarfdump] Code clean up for inlined var loc stats (details)
182. [clangd] Fix data type of WorkDoneProgressReport::percentage (details)
183. [Constant] Allow ConstantAggregateZero a scalable element count (details)
184. X86LoadValueInjectionLoadHardening.cpp - use const-reference in for-range loops to avoid unnecessary copies. NFCI. (details)
185. X86FlagsCopyLowering.cpp - try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies. NFCI. (details)
186. [TableGen] Remove redundant `Error:` in msg (NFC) (details)
187. [OPENMP]Fix PR48851: the locals are not globalized in SPMD mode. (details)
188. [AArch64][SVE] Improve SVE codegen for fixed length BITCAST (details)
189. [libc++][AIX] Define _LIBCPP_ELAST (details)
190. [SLP]Do not count perfect diamond matches for gathers several times. (details)
191. [PowerPC] Enable safe for 32bit vins* P10 instructions (details)
192. [libomptarget] Add support for target allocators to dynamic cuda RTL (details)
193. Revert "[PassManager] add helper function to hold set of vector passes" (details)
194. [clang][AArch32] Correctly align HA arguments when passed on the stack (details)
195. [NFC] Synchronize reserved identifier code between macro and variables / symbols (details)
196. [X86] Fix position-independent TType encoding (details)
197. [libc++][NFC] Remove _VSTD:: when not needed. (details)
198. [llvm-objdump][MachO] Print a newline before lazy bind/bind/weak/exports trie (details)
199. [X86][SSE] Merge equal X32/X64 check prefixes. NFCI. (details)
200. [X86][SSE] Add tests for missing shuffle(pack(x,y),pack(z,w)) -> permute(pack()) folds. (details)
201. [llvm-symbolizer] Update Command Guide (details)
202. [llvm-nm] Help option output should be consistent with the command guide (details)
203. [ORC] Update SpeculativeJIT example for dispatchTask changes in 5344c88dcb2. (details)
204. [clang] Support -fpic -fno-semantic-interposition for AArch64 (details)
205. [Demangle][Rust] Parse basic types (details)
206. [RISCV] Correct VL for fixed length masked scatter. (details)
207. [X86][SSE] Add examples of failures to remove a permute(pack(pack(),pack())) shuffle by reordering the packed operands. (details)
208. [mlir][CAPI] Add CAPI bindings for the sparse_tensor dialect. (details)
209. [cmake] Enable -Wmisleading-indentation (details)
210. [lld][WebAssembly] Disallow exporting of TLS symbols (details)
211. [mlir][Python] Upstream the PybindAdaptors.h helpers and use it to implement sparse_tensor.encoding. (details)
212. [Dependence Analysis] Enable delinearization of fixed sized arrays (details)
213. [lld-macho] Improve an external weak def test (details)
214. [X86][SSE] canonicalizeShuffleMaskWithHorizOp - add TODO for better 256/512-bit shuffle+hop folding support. NFC. (details)
215. [X86][AVX] Add example of failure to remove a 256-bit permute(hadd(hadd(),hadd())) shuffle by reordering the packed operands. (details)
216. [NFC][X86][MCA] AMD Zen 3: add tests for sub-32-bit CMP dep breaking (details)
217. [X86] AMD Zen 3: sub-32-bit CMP also break dependencies (details)
218. [mlir][Python] Re-export cext sparse_tensor module to the public namespace. (details)
219. [PassManager] add helper function to hold set of vector passes (2nd try) (details)
220. [GlobalISel][IRTranslator] Fix bit-test lowering dropping phi edges. (details)
221. [RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max) (details)
222. [scudo] [GWP-ASan] Add GWP-ASan variant of scudo benchmarks. (details)
223. [libc] Rever "Simplifies multi implementations and benchmarks". (details)
224. [mlir][linalg] Restrict distribution to parallel dims (details)
225. [TargetLowering] Only inspect attributes in the arguments for ArgListEntry (details)
226. [PowerPC] Spilling to registers does not require frame index scavenging (details)
227. [lld-macho][nfc] Clean up tests (details)
228. [lld-macho] Treat undefined symbols uniformly (details)
229. [lld-macho] Fix order file arch filtering (details)
230. [mlir][sparse] complete migration to sparse tensor type (details)
231. [Scudo] Use GWP-ASan's aligned allocations and fixup postalloc hooks. (details)
232. [Inliner] Fix noalias metadata handling for instructions simplified during cloning (PR50270) (details)
233. [ORC] Use a unique_function rather than std::function for dispatchTask. (details)
234. [NFC] Use ArgListEntry indirect types more in ISel lowering (details)
235. [lld][WebAssembly] Initial support merging string data (details)
236. [VecLib] Add support for vector fns from Darwin's libsystem. (details)
237. [InstCombine] Fold comparison of integers by parts (details)
238. [mlir][Python] Finish adding RankedTensorType support for encoding. (details)
239. [mlir] Fix windows build bot break due to use of `alloca` in a test. (details)
240. [test] Put aix-xcoff-huge-relocs.ll under expensive checks (details)
241. [libcxx] removes `weak_equality` and `strong_equality` from <compare> (details)
242. [NFC][X86][MCA] AMD Zen 3: add tests for same-reg MMX PCMPEQ (details)
243. [X86] AMD Zen 3: same-reg PCMPEQ is an MMX all-ones dep breaking idiom (details)
244. [NFC][X86][MCA] AMD Zen 3: add tests for same-reg XMM SSE PCMP (details)
245. [X86] AMD Zen 3: same-reg SSE XMM PCMP is dep breaking one-idiom (details)
246. [NFC][X86][MCA] AMD Zen 3: add tests for same-re AVX XMM VPCMP (details)
247. [X86] AMD Zen 3: same-reg AVX XMM VPCMP is dep breaking one-idiom (details)
248. [NFC][X86][MCA] AMD Zen 3: add tests for same-re AVX YMM VPCMP (details)
249. [X86] AMD Zen 3: same-reg AVX YMM VPCMP is dep breaking one-idiom (details)
250. [clang-tidy] Aliasing: Add support for captures. (details)
251. [clang-tidy] Aliasing: Add more support for captures. (details)
252. [clang-tidy] Aliasing: Add support for aggregates with references. (details)
253. [InstCombine] add tests for extract-subvector of insert; NFC (details)
254. [InstCombine] fold extract subvector of bitcast insertelt (details)
255. Remove some unnecessary explicit defaulted copy ctors to cleanup -Wdeprecated-copy (details)
256. Clangd Matchers.h: Fix -Wdeprecated-copy by making the defaulted copy ctor and deleted copy assignment operators explicit (details)
257. [Hexagon] Handle loads and stores of scalar predicate vectors (details)
258. Pre-commit test case for D101970 (details)
259. [AArch64][GlobalISel] Enable memcpy family combines on minsize functions (details)
260. Revert "[lld][WebAssembly] Initial support merging string data" (details)
261. [AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps (details)
262. [mlir][Tensor] Add folding for tensor.from_elements (details)
263. Reland: "[lld][WebAssembly] Initial support merging string data" (details)
264. [gn build] Port 3b8d2be52725 (details)
265. [AMDGPU] Constant fold Intrinsic::amdgcn_perm (details)
266. [mlir][linalg] remove the -now- obsolete sparse support in linalg (details)
267. [libcxx][ranges] Add ranges::empty CPO. (details)
268. [ORC-RT] Add unit test infrastructure, extensible_rtti implementation, unit test (details)
269. [gn build] Port e5d483f28a3a (details)
270. [NFC][LSAN] Fix flaky multithreaded test (details)
271. Enable export of FIR includes into the install tree (details)
272. [RISCV] Fix the calculation of the offset of Zvlsseg spilling. (details)
273. [AMDGPU] Pre-commit tests for D102211 (details)
274. [OpAsmParser] Refactor parseOptionalInteger to support wide integers, NFC. (details)
275. [LLD] Improve reporting unresolved symbols in shared libraries (details)
276. [mlir][linalg] Remove IndexedGenericOp support from Tiling... (details)
277. [clangd][index-sever] Limit results in repsonse (details)
278. [clangd][remote-client] Set HasMore to true for failure (details)
279. [libcxx] removes operator!= and globally guards against no spaceship operator (details)
280. [libcxx] makes comparison operators for `std::*_ordering` types hidden friends (details)
281. [libcxx] deprecates/removes `std::raw_storage_iterator` (details)
282. [mlir][linalg] Remove IndexedGenericOp support from Fusion... (details)

Started by timer

This run spent:

• 2 hr 31 min waiting;
• 4 hr 24 min build duration;
• 4 hr 24 min total from scheduled to completion.

• refs/remotes/origin/main

• refs/remotes/origin/main

• refs/remotes/origin/main

• lldb-unit.Core/_/LLDBCoreTests.DumpDataExtractorTest.Formats

Identified problems

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 1

Ninja target failed

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Indication 2