Changes

Summary

  1. [Zorg][OpenMP] Add CUDA offloading worker. (details)
Commit e4aa8a2773fe76c427a91229f021ab067eafc8e7 by llvm-zorg
[Zorg][OpenMP] Add CUDA offloading worker.

This worker tests OpenMP offloading for the x86_64 and NVIDIA GPU. In
addition to check-openmp, it runs the SOLLVE Validation & Verification Suite
via the LLVM test-suite External builder. The builder is configured to
only warn if the SOLLVE suite fails, as it also tests features that
have not been implemented in Clang yet.

CUDA is intentionally not installed in a default location (/opt/cuda) to
resemble setups often found in computing clusters with multiple versions
of CUDA to choose from.

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D101268
The file was modifiedbuildbot/osuosl/master/config/workers.py (diff)
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)
The file was modifiedzorg/buildbot/builders/OpenMPBuilder.py (diff)

Summary

  1. [mlir][linalg] Remove IndexedGenericOp support from LinalgToLoops... (details)
  2. [llvm-dwarfdump] Fix abstract origin vars location stats calculation (details)
  3. [libcxx][test] Make string.modifiers/clear_and_shrink_db1.pass.cpp a regular mode test (details)
  4. Support VectorTransfer splitting on writes also. (details)
  5. [OpenCL] [NFC] Fixed underline being too short in rst (details)
  6. Fix -Wdocumentation warnings. NFCI. (details)
  7. * Add support for JSON output style to llvm-symbolizer (details)
  8. [flang][cmake] Enable the new driver by default (details)
  9. [WebAssembly] Support for WebAssembly globals in LLVM IR (details)
  10. [VP] Improve the VP intrinsic unittests (details)
  11. [CodeGen][WebAssembly] Better lowering for WASM_SYMBOL_TYPE_GLOBAL symbols (details)
  12. [LLD] [COFF] Add an assert regarding the RVA of exported symbols. NFC. (details)
  13. [MLIR] Switch llvm.noalias to a unit attribute (details)
  14. [AMDGPU] Add some GFX10.3 testing. NFC. (details)
  15. [RegAllocFast] properly handle STATEPOINT instruction. (details)
  16. [PowerPC][Bug] Fix Bug in Stack Frame Update Code (details)
  17. [LLDB] Don't use the local python to set a default for LLDB_PYTHON_RELATIVE_PATH when cross compiling. (details)
  18. [libomptarget][nfc] Drop stringify in macro (details)
  19. [OpenCL] Allow use of double type without extension pragma. (details)
  20. [AMDGPU] Move code sinking before structurizer (details)
  21. [SLP] restrict matching of load combine candidates (details)
  22. [X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again (details)
  23. CodeGen: Fix null dereference before null check (details)
  24. [X86][SSE] Replace foldShuffleOfHorizOp with generalized version in canonicalizeShuffleMaskWithHorizOp (details)
  25. [X86] Replace repeated isa/cast<ConstantSDNode> calls with single single dyn_cast<>. NFCI. (details)
  26. [TableGen] Make the NUL character invalid in .td files (details)
  27. [X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost() (details)
  28. [VPlan] Register recipe for instr if the simplified value is recipe. (details)
  29. [OpenMP] Fix hidden helper + affinity (details)
  30. Revert "[TableGen] Make the NUL character invalid in .td files" (details)
  31. Fix typo "Execpt" in comments (details)
  32. [LoopInterchange] Fix legality for triangular loops (details)
  33. Revert "[AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S" (details)
  34. [NFC][AMDGPU] Correct product name for gfx908 (details)
  35. [IR][AutoUpgrade] Drop align attribute from void return types (details)
  36. Produce warning for performing pointer arithmetic on a null pointer. (details)
  37. [NFC][X86] Precommit another testcase for D101944 (details)
  38. Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation (details)
  39. Change Target::ReadMemory to ensure the amount of memory read from the file-cache is the amount requested. (details)
  40. Add null-pointer checks when accessing a TypeSystem's SymbolFile (details)
  41. [mlir] Use static shape knowledge when lowering memref.reshape (details)
  42. [libomptarget][nfc] Add hook to easily disable building amdgcn bclib (details)
  43. [libc++] s/_VSTD::declval/declval/g. NFCI. (details)
  44. [libc++] s/std::size_t/size_t/g. NFCI. (details)
  45. [libc++] s/_VSTD::chrono/chrono/g. NFCI. (details)
  46. [libc++] s/_VSTD::is_unsigned/is_unsigned/ in <random>. NFCI. (details)
  47. [libc++] Remove more unnecessary _VSTD:: from type names. NFCI. (details)
  48. Revert "Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation" (details)
  49. [RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl. (details)
  50. [X86][Codegen] Shift amount mod: sh? i64 x, (32-y) --> sh? i64 x, -(y+32) (details)
  51. [RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min. (details)
  52. [libcxx][tests] Fix incomplte.verify tests by disabling them on clang-10. (details)
  53. [X86][SSE] Add tests for permute(phaddw(phaddw(x,y),phaddw(z,w))) -> phaddw(phaddw(),phaddw()) folds. (details)
  54. Reland "[Coverage] Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation"" (details)
  55. Revert "[ORC-RT] Add unit test infrastructure, extensible_rtti..." (details)
  56. [TextAPI] Reformat llvm_unreachable message (details)
  57. [flang] Allow large and erroneous ac-implied-do's (details)
  58. Re-apply "[ORC-RT] Add unit test infrastructure, extensible_rtti..." (details)
  59. [lld/mac] Implement -sectalign (details)
  60. [git-clang-format] Do not apply clang-format to symlinks (details)
  61. [libcxx] [test] Fix filesystem permission tests for windows (details)
  62. [mlir][ODS]: Add per-op cppNamespace. (details)
  63. [ArgumentPromotion] Fix byval alignment handling. (details)
  64. [RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local (details)
  65. [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. (details)
  66. [GlobalOpt] Remove heap SROA (details)
  67. [X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): canonicalize to integer type (details)
  68. [lld][WebAssembly] Convert test to assembly. NFC. (details)
  69. [clang] Support -fpic -fno-semantic-interposition for RISCV (details)
  70. [OpenMP] Use compound operators for reduction combiner if available. (details)
  71. [libc++] Run `substitutes-in-compile-flags.sh.cpp` test on Windows. (details)
  72. Add an "interrupt timeout" to Process, and pipe that through the (details)
  73. [lld][WebAssembly] Remove relocation target verification (details)
  74. [mlir] Move move capture in SparseElementsAttr::getValues (details)
  75. [NFC][LSAN] Limit the number of concurrent threads is the test (details)
  76. [AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects. (details)
  77. [PowerPC] Improve codegen for int-to-fp conversion of subword vector extract (details)
  78. [OpenMP] Changes to enable MSVC ARM64 build of libomp (details)
  79. [RISCV] Regenerate stepvector.ll. NFC (details)
  80. [hwasan] Stress test for thread creation. (details)
  81. [AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2 (details)
  82. Removed unnecessary introduction of semi-colons. (details)
  83. [mlir] Elide large elements attrs when printing Operations in diagnostics (details)
  84. [mlir][tosa] Tosa elementwise broadcasting had some minor bugs (details)
  85. [InstCombine] Clean up one-hot merge optimization (NFC) (details)
  86. [RISCV] Move instruction information into the RISCVII namespace (NFC) (details)
  87. [llvm-cov] Support for v4 format in convert-for-testing (details)
  88. Revert "[LoopInterchange] Fix legality for triangular loops" (details)
  89. [AIX][TLS] Diagnose use of unimplemented TLS models (details)
  90. [JITLink] Make LinkGraph debug dumps more readable. (details)
  91. [JITLink][x86-64] Add an x86_64 PointerSize constexpr. (details)
  92. [JITLink][MachO/x86_64] Expose API for creating eh-frame fixing passes. (details)
  93. [Coverage] Support overriding compilation directory (details)
  94. [LoopInterchange] Fix legality for triangular loops (details)
  95. [clang][Fuchsia] Introduce compat multilibs (details)
  96. [JITLink] Fix bogus format string. (details)
  97. Revert "[GVN] Clobber partially aliased loads." (details)
  98. GlobalISel: Move AArch64 AssignFnVarArg to base class (details)
  99. GlobalISel: Split ValueHandler into assignment and emission classes (details)
  100. GlobalISel: Make constant fields const (details)
  101. AMDGPU: Fix assert on constant load from addrspacecasted pointer (details)
  102. GlobalISel: Don't hardcode varargs=false in resultsCompatible (details)
  103. Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope. (details)
  104. Add test for PR50039. (details)
  105. Revert "Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope." (details)
  106. [lld][WebAssembly] Fix for string merging + negative addends (details)
  107. This test is failing on Linux, skip while I investigate. (details)
  108. AMDGPU: Fix SILoadStoreOptimizer for gfx90a (details)
  109. Removing test... (details)
  110. [LoopInterchange] Handle lcssa PHIs with multiple predecessors (details)
  111. [NFC][msan] Move setlocale test into sanitizer_common (details)
  112. [mlir][AsmPrinter] Remove recursion while SSA naming (details)
  113. tsan: add a simple syscall test (details)
  114. tsan: mark sigwait as blocking (details)
  115. [VectorComine] Restrict single-element-store index to inbounds constant (details)
  116. tsan: declare annotations in test.h (details)
  117. sanitizer_common: fix SIG_DFL warning (details)
  118. [symbolizer] Fix leak after D96883 (details)
  119. sanitizer_common: don't write into .rodata (details)
  120. [libcxx][test] Split more debug mode tests (details)
  121. [PowerPC] [Clang] Enable float128 feature on VSX targets (details)
  122. sanitizer_common: deduplicate CheckFailed (details)
  123. [COFF] Fix ARM and ARM64 REL32 relocations to be relative to the end of the relocation (details)
  124. tsan: fix syscall test on aarch64 (details)
  125. [mlir] Support alignment in LLVM dialect GlobalOp (details)
  126. [MLIR] Enable conversion from llvm::SMLoc to mlir::Location with OpAsmParser. (details)
  127. scudo: fix CheckFailed-related build breakage (details)
  128. [libc] Simplifies multi implementations (details)
  129. [NFC][llvm-dwarfdump] Avoid passing std::string by value in collectStatsForDie() (details)
  130. Fixed llvm-objcopy to add correct symbol table for ELF with program headers. (details)
  131. [ARM] Precommit test for D101898 (details)
  132. [ARM] Prevent spilling between ldrex/strex pairs (details)
  133. Revert "[PowerPC] [Clang] Enable float128 feature on VSX targets" (details)
  134. [AMDGPU] Skip invariant loads when avoiding WAR conflicts (details)
  135. Remove Windows editline from LLDB (details)
  136. Reapply "[DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST" (details)
  137. [lldb] [Process/elf-core] Fix reading FPRs from FreeBSD/i386 cores (details)
  138. [Process/elf-core] Read PID from FreeBSD prpsinfo (details)
  139. [AArch64][SVE] Improve sve.convert.to.svbool lowering (details)
  140. [LoopVectorize] Fix scalarisation crash in widenPHIInstruction for scalable vectors (details)
  141. [llvm-symbolizer] Place Mach-O options into the Mach-O option group. (details)
  142. [llvm-readelf] Unhide short options to match the command guide (details)
  143. [X86][AVX] canonicalizeShuffleMaskWithHorizOp - improve support for 256/512-bit vectors (details)
  144. [libcxx] NFC. Correct wordings of _LIBCPP_ASSERT debug messages (details)
  145. [mlir][linalg] Remove IndexedGenericOp support from LinalgToStandard... (details)
  146. [clang-tidy] Enable the use of IgnoreArray flag in pro-type-member-init rule (details)
  147. Revert "[scudo] Enable arm32 arch" (details)
  148. [mlir][linalg] Remove IndexedGenericOp support from LinalgBufferize... (details)
  149. [clang-tidy][NFC] Simplify a lot of bugprone-sizeof-expression matchers (details)
  150. [x86] add test for pcmpeq with 0; NFC (details)
  151. [x86] try harder to lower to PCMPGT instead of not-of-PCMPEQ (details)
  152. [AMDGPU] Remove assert (details)
  153. [mlir][linalg] Remove IndexedGenericOp support from LinalgInterchangePattern... (details)
  154. [TargetRegisterInfo] Speed up getAllocatableSet. NFCI. (details)
  155. [InstCombine] ~(C + X) --> ~C - X (PR50308) (details)
  156. [AMDGPU] Improve Codegen for build_vector (details)
  157. [llvm-objdump] Exclude __mh_*_header symbols during MachO disassembly (details)
  158. [Passes] Reenable the relative lookup table converter pass for ELF and COFF on aarch64 (details)
  159. [NFC] Use variable GEP index in vec_demanded_elts tests (details)
  160. [clang][AVR] Redefine some types to be compatible with avr-gcc (details)
  161. [CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr (details)
  162. [DAGCombiner] Add test exposing bug in DAG combine. (details)
  163. [DAGCombiner] Fix DAG combine store elimination, different address space. (details)
  164. Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics" (details)
  165. [ValueTypes] Rename MVT::getVectorNumElements() to MVT::getVectorMinNumElements(). Fix some misuses of getVectorNumElements() (details)
  166. [CUDA][HIP] Fix device template variables (details)
  167. [llvm-cov][test] Add test coverage for "gcov" implying "llvm-cov gcov" compatibility. (details)
  168. [OpenCL] Remove pragma requirement from Arm dot extension. (details)
  169. [mlir][openacc] Conversion of data operand to LLVM IR dialect (details)
  170. [TargetLowering] Improve legalization of scalable vector types (details)
  171. [X86][AVX] Add v4i64 shift-by-32 tests (details)
  172. [X86][AVX] combineConcatVectorOps - add ConcatSubOperand helper. NFCI. (details)
  173. Fix grammar in README.md (details)
  174. [AMDGPU] Disable the SIFormMemoryClauses pass at -O1 (details)
  175. [PowerPC] Fix definitions of CMPRB8, CMPEQB, CMPRB, SETB in PPCInstr64Bit.td and PPCInstrInfo.td (details)
  176. [MLIR] Factor pass timing out into a dedicated timing manager (details)
  177. [docs] Fix documentation for bugprone-dangling-handle (details)
  178. [SystemZ][z/OS] Fix warning caused by umask returning a signed integer type (details)
  179. [libomptarget][amdgpu][nfc] Expand errorcheck macros (details)
  180. [lld-macho] Implement branch-range-extension thunks (details)
  181. [AArch64][GlobalISel] Add MMOs to constant pool loads to allow LICM hoisting. (details)
  182. [mlir][sparse] keep runtime support library signature consistent (details)
  183. [X86][AVX] Fold concat(ps*lq(x,32),ps*lq(y,32)) -> shuffle(concat(x,y),zero) (PR46621) (details)
  184. Update static bound checker for Linalg to cover decreasing cases (details)
  185. [CMake][ELF] Add -fno-semantic-interposition and -Bsymbolic-functions (details)
  186. [X86] Fix -Wunused-lambda-capture (details)
  187. [NFCI][clang][Codegen] CodeGenVTables::addVTableComponent(): use getGlobalDecl (details)
  188. [NFC][clang][Codegen] Split ThunkInfo into it's own header (details)
  189. [mlir][openacc] Add OpenACC translation to LLVM IR (enter_data op create/copyin) (details)
  190. Remove AST inclusion from Basic include (details)
  191. [mlir][linalg] Fixed issue generating reassociation map with Rank-0 types (details)
  192. [cmake] Add support for multiple distributions (details)
  193. [LoopFlatten] Simplify loops so that the pass can operate on unsimplified loops. (details)
  194. [SCEV] Add loop-guard pessimizing test with step = 2. (details)
  195. [PhaseOrdering] Add test for missing vectorization with NewPM. (details)
  196. [clang-tidy] Allow opt-in or out of some commonly occuring patterns in NarrowingConversionsCheck. (details)
  197. Revert "Produce warning for performing pointer arithmetic on a null pointer." (details)
  198. Add type information to integral template argument if required. (details)
  199. [InstCombine] Support one-hot merge for logical and/or (details)
  200. [libc++][nfc] remove duplicated __to_unsigned. (details)
  201. [cmake] Fix typo in function name (details)
  202. [libcxx] [test] Fix fs.op.last_write_time for Windows (details)
  203. [LLD] [COFF] Fix including the personality function for DWARF EH when linking with --gc-sections (details)
  204. [ELF][AVR] Add explicit relocation types to getRelExpr (details)
  205. [mlir][tosa] Remove tosa.identityn operator (details)
  206. Suppress Deferred Diagnostics in discarded statements. (details)
  207. [flang] Fix standalone builds (details)
  208. [mlir-lsp-server] Add support for sending diagnostics to the client (details)
  209. [mlir-lsp-server][NFC] Add newline between Protocol JSON serialization methods and class definitions. (details)
  210. Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope. (details)
  211. [RISCV] Remove RISCVII:VSEW enum. Make encodeVYPE operate directly on SEW. (details)
  212. [WebAssembly] Allow Wasm EH with Emscripten SjLj (details)
  213. [WebAssembly] Add TLS data segment flag: WASM_SEG_FLAG_TLS (details)
  214. [lld][WebAssembly] Allow data symbols to extend past end of segment (details)
  215. [mlir] Fix ssa values naming bug (details)
  216. Optimize GSymCreator::finalize. (details)
  217. Change the context instruction for computeKnownBits in LoadStoreVectorizer pass (details)
  218. [mlir][Linalg] Add interface methods to get lhs and rhs of contraction (details)
  219. [AMDGPU] Refactor shouldExpandAtomicRMWInIR(). NFC. (details)
  220. [mlir][sparse][capi][python] add sparse tensor passes (details)
  221. [libcxx] modifies `_CmpUnspecifiedParam` ignore types outside its domain (details)
  222. scudo: Require fault address to be in bounds for UAF. (details)
  223. [AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S (details)
  224. Add test for substitutability of variable templates in closure type (details)
  225. Clean up handling of constrained parameters in lambdas. (details)
  226. PR50306: When instantiating a generic lambda with a constrained 'auto', (details)
  227. Handle unexpanded packs appearing in type-constraints. (details)
  228. Rename human-readable name for DW_LANG_Mips_Assembler (details)
  229. [clang] Minor fix for MarkVarDeclODRUsed (details)
  230. [mlir] Fix masked vector transfer ops with broadcasts (details)
  231. Revert "[mlir] Fix masked vector transfer ops with broadcasts" (details)
  232. [Debug-Info] add -gstrict-dwarf support in backend (details)
  233. [mlir] Fix masked vector transfer ops with broadcasts (details)
  234. [mlir] Allow empty position in vector.insert and vector.extract (details)
  235. [mlir] Unrolled progressive-vector-to-scf. (details)
  236. [mlir] Support memref layout maps in vector transfer ops (details)
  237. [clang-repl] Land initial infrastructure for incremental parsing (details)
  238. [SLP][Test] Fix and precommit tests for D98714 (details)
  239. [SLP][Test] Fix and precommit tests for D98714 (details)
  240. [SLP] Add insertelement instructions to vectorizable tree (details)
  241. [Coroutines] Enable printing coroutine frame when dbg info is available (details)
  242. Revert "[clang-repl] Land initial infrastructure for incremental parsing" (details)
  243. [mlir][tosa] Fix tosa.cast semantics to perform rounding/clipping (details)
Commit 7bc6df2528f60920ae8aaa90ef2351df4676232a by gysit
[mlir][linalg] Remove IndexedGenericOp support from LinalgToLoops...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102187
The file was modifiedmlir/test/Dialect/Linalg/loops.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Loops.cpp
Commit 1ed296360041c3091fa8d7348efde729f0d9c754 by djtodoro
[llvm-dwarfdump] Fix abstract origin vars location stats calculation

There are cases where a concrete DIE with DW_TAG_subprogram can have
abstract_origin attribute, so we handle that situation as well.

Differential Revision: https://reviews.llvm.org/D101025
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/stats-scope-bytes-covered.yaml
The file was addedllvm/test/tools/llvm-dwarfdump/X86/locstats-for-absctract-origin-vars.yaml
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/statistics.ll
The file was modifiedllvm/tools/llvm-dwarfdump/Statistics.cpp
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/statistics-v3.test
The file was removedllvm/test/tools/llvm-dwarfdump/X86/locstats-for-inlined-vars.yaml
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/statistics-dwo.test
Commit 65e40f0b265d13bde397db41303ac08d214a6559 by kbessonova
[libcxx][test] Make string.modifiers/clear_and_shrink_db1.pass.cpp a regular mode test

Turn this test into a normal mode as it contains well-formed code and
checks for defined behavior. It still can be run in debug mode as of D100866.

Differential Revision: https://reviews.llvm.org/D102192
The file was removedlibcxx/test/libcxx/strings/basic.string/string.modifiers/clear_and_shrink_db1.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/clear_and_shrink.pass.cpp
Commit 88a48999d249a5478d813596d1cfac6ba82126dc by tpopp
Support VectorTransfer splitting on writes also.

VectorTransfer split previously only split read xfer ops. This adds
the same logic to write ops. The resulting code involves 2
conditionals for write ops while read ops only needed 1, but the created
ops are built upon the same patterns, so pattern matching/expectations
are all consistent other than in regards to the if/else ops.

Differential Revision: https://reviews.llvm.org/D102157
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/test/Dialect/Vector/vector-transfer-full-partial-split.mlir
Commit 7d20f709ea6da8442a153beda7ecdda07440f046 by olemarius.strohm
[OpenCL] [NFC] Fixed underline being too short in rst
The file was modifiedclang/docs/LanguageExtensions.rst
Commit 33399405f4423429ec92c98a116c9ddc486864ec by llvm-dev
Fix -Wdocumentation warnings. NFCI.
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPConstants.h
Commit 05d1ae4e18fa565ea522e02d2497ec68d1dbdd80 by aorlov
* Add support for JSON output style to llvm-symbolizer

This patch adds JSON output style to llvm-symbolizer to better support CLI automation by providing a machine readable output.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D96883
The file was modifiedllvm/lib/DebugInfo/Symbolize/DIPrinter.cpp
The file was modifiedllvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
The file was addedllvm/test/tools/llvm-symbolizer/output-style-json-code.test
The file was modifiedllvm/docs/CommandGuide/llvm-symbolizer.rst
The file was modifiedllvm/tools/llvm-symbolizer/llvm-symbolizer.cpp
The file was addedllvm/test/tools/llvm-symbolizer/output-style-json-frame.ll
The file was addedllvm/test/tools/llvm-symbolizer/output-style-json-data.test
The file was modifiedllvm/tools/llvm-symbolizer/Opts.td
Commit 04adfb660987072ad31756e0d04803f96c3c39f7 by andrzej.warzynski
[flang][cmake] Enable the new driver by default

With this patch, `FLANG_BUILD_NEW_DRIVER` is set to `On` by default
(i.e. the new driver is enabled). Note that the new driver depends on
Clang and hence with this change you will need to add `clang` to
`LLVM_ENABLE_PROJECTS`.

If you don't want to build the new driver, set `FLANG_BUILD_NEW_DRIVER`
to `Off`. This way you won't be required to include `clang` in
`LLVM_ENABLE_PROJECTS`.

Differential Revision: https://reviews.llvm.org/D101842
The file was modifiedflang/README.md
The file was modifiedllvm/CMakeLists.txt
The file was modifiedflang/CMakeLists.txt
Commit d7086af2143d58a6535e0837c4d8789c69c6985f by wingo
[WebAssembly] Support for WebAssembly globals in LLVM IR

This patch adds support for WebAssembly globals in LLVM IR, representing
them as pointers to global values, in a non-default, non-integral
address space.  Instruction selection legalizes loads and stores to
these pointers to new WebAssemblyISD nodes GLOBAL_GET and GLOBAL_SET.
Once the lowering creates the new nodes, tablegen pattern matches those
and converts them to Wasm global.get/set of the appropriate type.

Based on work by Paulo Matos in https://reviews.llvm.org/D95425.

Reviewed By: pmatos

Differential Revision: https://reviews.llvm.org/D101608
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedclang/lib/Basic/Targets/WebAssembly.h
The file was addedllvm/test/CodeGen/WebAssembly/global-set.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISD.def
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
The file was addedllvm/test/CodeGen/WebAssembly/global-get.ll
The file was modifiedllvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrRef.td
The file was modifiedclang/test/CodeGen/target-data.c
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Commit b159987054e12ad9f5b5e373249cbdba90047b84 by simon.moll
[VP] Improve the VP intrinsic unittests

Test that all VP intrinsics are tested.
Test intrinsic id -> opcode -> intrinsic id round tripping.
Test property scopes in the include/llvm/IR/VPIntrinsics.def file.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D93534
The file was modifiedllvm/unittests/IR/VPIntrinsicTest.cpp
Commit b2f21b145aecbf5bc1af63b79de395897fc2e6f4 by wingo
[CodeGen][WebAssembly] Better lowering for WASM_SYMBOL_TYPE_GLOBAL symbols

As we have been missing support for WebAssembly globals on the IR level,
the lowering of WASM_SYMBOL_TYPE_GLOBAL to IR was incomplete.  This
commit fleshes out the lowering support, lowering references to and
definitions of addrspace(1) values to correctly typed
WASM_SYMBOL_TYPE_GLOBAL symbols.

Depends on D101608.

Differential Revision: https://reviews.llvm.org/D101913
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/global-set.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/global-get.ll
Commit 518b7f913526b5d002751edfa88869d10f5412fc by martin
[LLD] [COFF] Add an assert regarding the RVA of exported symbols. NFC.

As this isn't handled as a regular relocation, the normal handling of
maybeReportRelocationToDiscarded in Chunks.cpp doesn't apply here.

This would have caught the issue fixed by
82de4e075339f5ad8d68cfe31eb45b771d4750ae.

Differential Revision: https://reviews.llvm.org/D102115
The file was modifiedlld/COFF/DLL.cpp
Commit 1c777ab459d7ee181d7aba62af8bc35a572a2290 by uday
[MLIR] Switch llvm.noalias to a unit attribute

Switch llvm.noalias attribute from a boolean attribute to a unit
attribute.

Differential Revision: https://reviews.llvm.org/D102225
The file was modifiedmlir/test/Dialect/LLVMIR/func.mlir
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/test/Target/LLVMIR/llvmir-invalid.mlir
The file was modifiedmlir/test/Target/LLVMIR/llvmir.mlir
The file was modifiedmlir/test/Conversion/StandardToLLVM/convert-static-memref-ops.mlir
The file was modifiedmlir/test/Dialect/LLVMIR/invalid.mlir
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
Commit 3b873831c439021da736fdc7c2c54bd0da2869ea by jay.foad
[AMDGPU] Add some GFX10.3 testing. NFC.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/readcyclecounter.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/readcyclecounter.ll
Commit df47368d406aa4b9aaa7dd49026a0eff9763e6ca by dantrushin
[RegAllocFast] properly handle STATEPOINT instruction.

STATEPOINT is a fancy and complex pseudo instruction which
has both tied defs and regmask operand.

Basic FastRA algorithm is as follows:

1. Mark registers used by defs as free
2. If instruction has regmask operand displace clobbered registers
   according to regmask.
3. Assign registers for use operands.

In case of tied defs step 1 is replaced with allocation of registers
for them. But regmask is still processed, which may displace already
allocated registers. As a result, tied use and def will get assigned
to different registers.

This patch makes FastRA to process instruction's RegMask (if any) when
checking for physical registers interference.
That way tied operands won't get registers clobbered by regmask.

Reviewed By: arsenm, skatkov
Differential Revision: https://reviews.llvm.org/D99284
The file was addedllvm/test/CodeGen/X86/statepoint-fastregalloc.mir
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
Commit c79bc5942d0efd4740c7a6d36ad951c59ef3bc0e by stefanp
[PowerPC][Bug] Fix Bug in Stack Frame Update Code

The stack frame update code does not take into consideration spilling
to registers for callee saved registers. The option -ppc-enable-pe-vector-spills
turns on spilling to registers for callee saved registers and may expose a bug
in the code that moves a stack frame pointer update instruction.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D101366
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/stack_pointer_vec_spills.mir
Commit 3f03877f5a838973d0d22f6b45c112228319f4da by martin
[LLDB] Don't use the local python to set a default for LLDB_PYTHON_RELATIVE_PATH when cross compiling.

Differential Revision: https://reviews.llvm.org/D101903
The file was modifiedlldb/CMakeLists.txt
Commit dedca78d486e6532ad0d01f670c409c7339e6387 by jonathanchesterfield
[libomptarget][nfc] Drop stringify in macro

[libomptarget][nfc] Drop stringify in macro
A step towards deleting the macros entirely.

Differential Revision: https://reviews.llvm.org/D102228
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/internal.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/data.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/system.cpp
Commit 13ea238b1e1db96ef5fd409e869d9a8ebeef1332 by anastasia.stulova
[OpenCL] Allow use of double type without extension pragma.

Simply use of extensions by allowing the use of supported
double types without the pragma. Since earlier standards
instructed that the pragma is used explicitly a new warning
is introduced in pedantic mode to indicate that use of
type without extension pragma enable can be non-portable.

This patch does not break backward compatibility since the
extension pragma is still supported and it makes the behavior
of the compiler less strict by accepting code without extra
pragma statements.

Differential Revision: https://reviews.llvm.org/D100980
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/test/Misc/warning-flags.c
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaOpenCL/extensions.cl
Commit 09fe84abb4ee71f707c3ec8e960a42d8292f6211 by Piotr Sobczak
[AMDGPU] Move code sinking before structurizer

Moving code sinking pass before structurizer creates more sinking
opportunities.

The extra flow edges introduced by the structurizer can have adverse
effects on sinking, because the sinking pass prefers moving instructions
to blocks with unique predecessors and the structurizer destroys that
property in some cases.

A notable example is moving high-latency image instructions across kills.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D101115
The file was addedllvm/test/CodeGen/AMDGPU/sink-image-sample.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/multilevel-break.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Commit 49950cb1f6f699cbb9d8f141c0c043d4795c3417 by spatel
[SLP] restrict matching of load combine candidates

The test example from https://llvm.org/PR50256 (and reduced here)
shows that we can match a load combine candidate even when there
are no "or" instructions. We can avoid that by confirming that we
do see an "or". This doesn't apply when matching an or-reduction
because that match begins from the operands of the reduction.

Differential Revision: https://reviews.llvm.org/D102074
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/widen.ll
Commit c02476f3158f2908ef0a6f628210b5380bd33695 by lebedev.ri
[X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again

Instead of handling power-of-two sized vector chunks,
try handling the large vector in a stream mode,
decreasing the operational vector size
once it no longer works for the elements left to process.

Notably, this improves costs for overaligned loads - loading padding is fine.
This more directly tracks when we need to insert/extract the YMM/XMM subvector,
some costs fluctuate because of that.

Reviewed By: RKSimon, ABataev

Differential Revision: https://reviews.llvm.org/D100684
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/load_store.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
Commit bce3cca4889a9e4ab7b9652b0c44bb49ca8f3bad by Matthew.Arsenault
CodeGen: Fix null dereference before null check
The file was modifiedllvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
Commit 9acc03ad92c66b856f67bf11ff4460c7da45f413 by llvm-dev
[X86][SSE] Replace foldShuffleOfHorizOp with generalized version in canonicalizeShuffleMaskWithHorizOp

foldShuffleOfHorizOp only handled basic shufps(hop(x,y),hop(z,w)) folds - by moving this to canonicalizeShuffleMaskWithHorizOp we can work with more general/combined v4x32 shuffles masks, float/integer domains and support shuffle-of-packs as well.

The next step will be to support 256/512-bit vector cases.
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/horizontal-sum.ll
Commit 759b97e55a4bd7b0d89493686f4a769718e385ee by llvm-dev
[X86] Replace repeated isa/cast<ConstantSDNode> calls with single single dyn_cast<>. NFCI.

Noticed while looking at D101944
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 6ca2bdb03c0fdb6736ed5c6a30d7bec6b557d1a0 by Paul C. Anagnostopoulos
[TableGen] Make the NUL character invalid in .td files

Differential Revision: https://reviews.llvm.org/D101923
The file was addedllvm/test/TableGen/nul-char.td
The file was modifiedllvm/lib/TableGen/TGLexer.cpp
Commit 69ed93a4355123a45c1d7216aea7cd53d07a361b by lebedev.ri
[X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost()

Now that getMemoryOpCost() correctly handles all the vector variants,
we should no longer hand-roll our own version of it, but use it directly.

The AVX512 variant probably needs a similar change,
but there it is less obvious.
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i8.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i8.ll
Commit faebc6bf108eccdfd75917636c64137f73a7bda7 by flo
[VPlan] Register recipe for instr if the simplified value is recipe.

If the simplified VPValue is a recipe, we need to register it for Instr,
in case it needs to be recorded. The way this is handled in general may
change soon, following some post-commit comments.

This fixes PR50298.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction.ll
Commit c765d140fe45906fb503d843acccf5838e775245 by jonathan.l.peyton
[OpenMP] Fix hidden helper + affinity

When KMP_AFFINITY is set, each worker thread's gtid value is used as an
index into the place list to determine the thread's placement. With hidden
helpers enabled, this gtid value is shifted down leading to unexpected
shifted thread placement. This patch restores the previous behavior by
adjusting the mask index to take the number of hidden helper threads
into account.

Hidden helper threads are given the full initial mask and do not
participate in any of the other affinity mechanisms (place partitioning,
balanced affinity). Their affinity is only printed for debug builds.

Differential Revision: https://reviews.llvm.org/D101882
The file was modifiedopenmp/runtime/src/kmp.h
The file was modifiedopenmp/runtime/src/kmp_affinity.cpp
The file was modifiedopenmp/runtime/src/kmp_runtime.cpp
Commit 46402eb103d06b1e695ecfd6f6c9571615042a9c by Paul C. Anagnostopoulos
Revert "[TableGen] Make the NUL character invalid in .td files"

At least one build uses a 'sed' that does not understand \x00.

This reverts commit cf9647011c4f05e1eb4423c6637d84e2f26b2042.
The file was removedllvm/test/TableGen/nul-char.td
The file was modifiedllvm/lib/TableGen/TGLexer.cpp
Commit c58912eca743c612fd2a22c03b64a1bda3d2180f by aakanksha555
Fix typo "Execpt" in comments

Differential Revision: https://reviews.llvm.org/D101858
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit 29342291d25b83da97e74d75004b177ba41114fc by congzhecao
[LoopInterchange] Fix legality for triangular loops

This is a bug fix in legality check.

When we encounter triangular loops such as the following form:
    for (int i = 0; i < m; i++)
      for (int j = 0; j < i; j++), or

    for (int i = 0; i < m; i++)
      for (int j = 0; j*i < n; j++),

we should not perform interchange since the number of executions of the loop body
will be different before and after interchange, resulting in incorrect results.

Reviewed By: bmahjour

Differential Revision: https://reviews.llvm.org/D101305
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
The file was addedllvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
Commit eca3d68399246765bc6e8c94ffb4d5927b1add12 by Pushpinder.Singh
Revert "[AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S"

This reverts commit 7f78e409d0280c62209e1a7dc8c6d1409acc9184.
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/amdgpu-openmp-toolchain.c
Commit d6a228cba47ffb33d4f6814af1feaf49b34568d0 by Tony.Tye
[NFC][AMDGPU] Correct product name for gfx908

The product name for gfx908 is "AMD Instinct MI100 Accelerator".

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D102209
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit 4eff9469475384a59a9da407e78aa00262edcdd0 by Steven Wu
[IR][AutoUpgrade] Drop align attribute from void return types

Since D87304, `align` become an invalid attribute on none pointer types and
verifier will reject bitcode that has invalid `align` attribute.

The problem is before the change, DeadArgumentElimination can easily
turn a pointer return type into a void return type without removing
`align` attribute. Teach Autograde to remove invalid `align` attribute
from return types to maintain bitcode compatibility.

rdar://77022993

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D102201
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was addedllvm/test/Bitcode/upgrade-void-ret-attr-11.0.ll.bc
The file was addedllvm/test/Bitcode/upgrade-void-ret-attr-11.0.ll
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
Commit dfc1e31d49fe1380c9bab43373995df5fed15e6d by schmeise
Produce warning for performing pointer arithmetic on a null pointer.

Summary:
Test and produce warning for subtracting a pointer from null or subtracting
null from a pointer.  Reuse existing warning that this is undefined
behaviour.  Also add unit test for both warnings.

Reformat to satisfy clang-format.

Respond to review comments:  add additional test.

Respond to review comments:  Do not issue warning for nullptr - nullptr
in C++.

Fix indenting to satisfy clang-format.

Respond to review comments:  Add C++ tests.

Author: Jamie Schmeiser <schmeise@ca.ibm.com>
Reviewed By: efriedma (Eli Friedman), nickdesaulniers (Nick Desaulniers)
Differential Revision: https://reviews.llvm.org/D98798
The file was addedclang/test/Sema/pointer-addition.cpp
The file was modifiedclang/test/Sema/pointer-addition.c
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit 2c1f9f390b0a5dd308e2e925fe250d19a29c103f by lebedev.ri
[NFC][X86] Precommit another testcase for D101944
The file was modifiedllvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
Commit 6400905a615282c83a2fc6e49e57ff716aa8b4de by a-phipps
Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation
groups.

This change corrects the implementation for the branch coverage
summary to do the same thing for branches that is done for lines and regions.
That is, across function instantiations in an instantiation group, the maximum
branch coverage found in any of those instantiations is returned, with the
total number of branches being the same across instantiations.

Differential Revision: https://reviews.llvm.org/D102193
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.h
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.cpp
The file was modifiedllvm/test/tools/llvm-cov/branch-templates.cpp
Commit 6c82b8a378a6f59e94a81d91225db4fabf6e2bff by augusto2112
Change Target::ReadMemory to ensure the amount of memory read from the file-cache is the amount requested.

This change ensures that if for whatever reason we read less bytes than expected (for example, when trying to read memory that spans multiple sections), we try reading from the live process as well.

Reviewed By: jasonmolenda

Differential Revision: https://reviews.llvm.org/D101390
The file was modifiedlldb/source/Target/Target.cpp
Commit ec28e43e01540a57f8822b2efb8638996873f945 by augusto2112
Add null-pointer checks when accessing a TypeSystem's SymbolFile

A type system is not guaranteed to have a symbol file. This patch adds null-pointer checks so we don't crash when trying to access a type system's symbol file.

Reviewed By: aprantl, teemperor

Differential Revision: https://reviews.llvm.org/D101539
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
The file was modifiedlldb/unittests/Symbol/TestTypeSystemClang.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/PDB/PDBASTParser.cpp
The file was modifiedlldb/source/Symbol/Type.cpp
Commit b20e150c9be16f69c73f4cd2986053d13d0f376a by benny.kra
[mlir] Use static shape knowledge when lowering memref.reshape

This is actually necessary for correctness, as memref.reinterpret_cast
doesn't verify if the output shape doesn't match the static sizes.

Differential Revision: https://reviews.llvm.org/D102232
The file was modifiedmlir/lib/Dialect/StandardOps/Transforms/ExpandOps.cpp
The file was modifiedmlir/test/Dialect/Standard/expand-ops.mlir
Commit 72995a4bdf7d95887883ccfa04567b723f2b342a by jonathanchesterfield
[libomptarget][nfc] Add hook to easily disable building amdgcn bclib

[libomptarget][nfc] Add hook to easily disable building amdgcn bclib

This is useful when building LLVM with a toolchain that can't emit code
for amdgcn, e.g. because it overrides the include search path with headers
from another architecture, or the clang compiler is missing builtins.

Reviewed By: tianshilei1992

Differential Revision: https://reviews.llvm.org/D102229
The file was modifiedopenmp/libomptarget/deviceRTLs/amdgcn/CMakeLists.txt
Commit ab3fcc5065a895f88ec8a020bc3c2f7e54cc4561 by arthur.j.odwyer
[libc++] s/_VSTD::declval/declval/g. NFCI.
The file was modifiedlibcxx/include/concepts
The file was modifiedlibcxx/include/istream
The file was modifiedlibcxx/include/optional
The file was modifiedlibcxx/include/ostream
The file was modifiedlibcxx/include/scoped_allocator
The file was modifiedlibcxx/include/experimental/propagate_const
The file was modifiedlibcxx/include/type_traits
The file was modifiedlibcxx/include/__functional_base
The file was modifiedlibcxx/include/__memory/shared_ptr.h
The file was modifiedlibcxx/include/variant
The file was modifiedlibcxx/include/memory
The file was modifiedlibcxx/include/__memory/construct_at.h
The file was modifiedlibcxx/include/algorithm
Commit 0b8da5fa5915f1cea790c7e246195e30afd9e391 by arthur.j.odwyer
[libc++] s/std::size_t/size_t/g. NFCI.
The file was modifiedlibcxx/include/experimental/functional
The file was modifiedlibcxx/include/type_traits
Commit aa5e3beea3d4d4e00cb2b0f2d103b4bd52239384 by arthur.j.odwyer
[libc++] s/_VSTD::chrono/chrono/g. NFCI.
The file was modifiedlibcxx/include/chrono
Commit 866b27950aaf2c38f4ecfc8a0f18945fff3b8542 by arthur.j.odwyer
[libc++] s/_VSTD::is_unsigned/is_unsigned/ in <random>. NFCI.
The file was modifiedlibcxx/test/std/numerics/rand/rand.eng/rand.eng.lcong/params.fail.cpp
The file was modifiedlibcxx/include/random
Commit 6491d99e330c38b33b9cb6acb19afa3a464febeb by arthur.j.odwyer
[libc++] Remove more unnecessary _VSTD:: from type names. NFCI.

Differential Revision: https://reviews.llvm.org/D102181
The file was modifiedlibcxx/include/experimental/functional
The file was modifiedlibcxx/include/functional
The file was modifiedlibcxx/include/algorithm
The file was modifiedlibcxx/include/memory
The file was modifiedlibcxx/include/random
The file was modifiedlibcxx/include/__memory/allocator_traits.h
The file was modifiedlibcxx/include/experimental/type_traits
The file was modifiedlibcxx/include/type_traits
Commit 668dccc396da4f593ac87c92dc0eb7bc983b5762 by a-phipps
Revert "Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation"

This reverts commit 6400905a615282c83a2fc6e49e57ff716aa8b4de.
The file was modifiedllvm/test/tools/llvm-cov/branch-templates.cpp
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.cpp
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.h
Commit dc00cbb5053895356955a6dc03632d4fa05048e3 by craig.topper
[RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl.

Limited to splats because we would need to truncate the shift
amount vector otherwise.

I tried to do this with new ISD nodes and a DAG combine to
avoid such a large pattern, but we don't form the splat until
LegalizeDAG and need DAG combine to remove a scalable->fixed->scalable
cast before it becomes visible to the shift node. By the time that
happens we've already visited the truncate node and won't revisit it.

I think I have an idea how to improve i64 on RV32 I'll save for a
follow up.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D102019
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll
Commit 5f78ba001ca23ab826b9be823fc8ac0a0e5d2237 by lebedev.ri
[X86][Codegen] Shift amount mod: sh? i64 x, (32-y) --> sh? i64 x, -(y+32)

I've seen this in the RawSpeed's BitPumpMSB*::push() hotpath,
after fixing the buffer abstraction to a more sane one,
when looking into a +5% runtime regression.
I was hoping that this would fix it, but it does not look it does.

This seems to be at least not worse than the original pattern.
But i'm actually mainly interested in the case where we already
compute `(y+32)` (see last test),

https://alive2.llvm.org/ce/z/ZCzJio

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D101944
The file was modifiedllvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit ce6e4f27dd72f834502f47176d84869a1f509d7b by craig.topper
[RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.

My thought process is that if v2i64 is an LMUL=1 type then v2i32
should be an LMUL=1/2 type. We limit the fractional LMUL so that
SEW=64 clips to LMUL=1, SEW=32 clips to LMUL=1/2, etc. This
ensures there's always a fractional LMUL available to truncate a type.
This does reduce the number of vsetvlis in some cases.

Some tests increase vsetvlis because the best container type for a
mask type is dependent on the LMUL+SEW that the mask was produced
from, but you can't tell that from the type. I think this is
something we need to solve this in the machine IR when optimizing
vsetvlis.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D101215
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
The file was modifiedllvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
Commit db13f832a1eec7427762c1ef1f56f169518f1abe by zoecarver
[libcxx][tests] Fix incomplte.verify tests by disabling them on clang-10.

For some reason clang-10 can't match the expected errors produced by
passing icomplete arrays to range access functions. Disabling the tests
is a stop-gap solution to fix the bots.
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.begin/incomplete.compile.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.prim/empty.incomplete.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.cend/incomplete.compile.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.end/incomplete.compile.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.cbegin/incomplete.compile.verify.cpp
Commit 4f80340fb6712f5f1e97e7667bfd5cffa7d684b7 by llvm-dev
[X86][SSE] Add tests for permute(phaddw(phaddw(x,y),phaddw(z,w))) -> phaddw(phaddw(),phaddw()) folds.

We currently only fold if NumEltsPerLane == 4
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle-4.ll
Commit eccb925147d5f262a3e74cc050d0665dd4e6d8db by a-phipps
Reland "[Coverage] Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation""

Originally landed in: 6400905a615282c83a2fc6e49e57ff716aa8b4de
Reverted in: 668dccc396da4f593ac87c92dc0eb7bc983b5762

Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation
groups.

This change corrects the implementation for the branch coverage summary to do
the same thing for branches that is done for lines and regions.  That is,
across function instantiations in an instantiation group, the maximum branch
coverage found in any of those instantiations is returned, with the total
number of branches being the same across instantiations.

Differential Revision: https://reviews.llvm.org/D102193
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.cpp
The file was modifiedllvm/test/tools/llvm-cov/branch-templates.cpp
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.h
Commit 1c7c6f2b106250d63905d7cde99a4559f0bb4978 by Lang Hames
Revert "[ORC-RT] Add unit test infrastructure, extensible_rtti..."

This reverts commit 6d263b6f1c9 while I investigate the CMake failures that it
causes in some configurations.
The file was removedcompiler-rt/lib/orc/unittests/orc_unit_test_main.cpp
The file was removedcompiler-rt/lib/orc/extensible_rtti.cpp
The file was removedcompiler-rt/lib/orc/unittests/CMakeLists.txt
The file was modifiedcompiler-rt/lib/orc/CMakeLists.txt
The file was modifiedcompiler-rt/cmake/config-ix.cmake
The file was removedcompiler-rt/lib/orc/unittests/extensible_rtti_test.cpp
The file was removedcompiler-rt/lib/orc/extensible_rtti.h
The file was addedcompiler-rt/lib/orc/placeholder.cpp
Commit cba508fb678798094a4fd668ce6bf4225fc73509 by Jonas Devlieghere
[TextAPI] Reformat llvm_unreachable message

Change llvm_unreachable message from "Unknown llvm.MachO.PlatformKind
enum" to "Unknown llvm::MachO::PlatformKind enum".

Differential revision: https://reviews.llvm.org/D102250
The file was modifiedllvm/lib/TextAPI/Platform.cpp
Commit 5a9497d6890145da74325dfcb032ad2963b5da3f by psteinfeld
[flang] Allow large and erroneous ac-implied-do's

We sometimes unroll an ac-implied-do of an array constructor into a flat list
of values.  We then re-analyze the array constructor that contains the
resulting list of expressions.  Such a list may or may not contain errors.

But when processing an array constructor with an unrolled ac-implied-do, the
compiler was building an expression to represent the extent of the resulting
array constructor containing the list of values.  The number of operands
in this extent expression was based on the number of elements in the
unrolled list of values.  For very large lists, this created an
expression so large that it could not be evaluated by the compiler
without overflowing the stack.

I fixed this by continuously folding the extent expression as each operand is
added to it.  I added the test .../flang/test/Semantics/array-constr-big.f90
that will cause the compiler to seg fault without this change.

Also, when the unrolled ac-implied-do expression contains errors, we were
repeating the same error message referencing the same source line for every
instance of the erroneous expression in the unrolled list.  This potentially
resulted in a very long list of messages for a single error in the source code.

I fixed this by comparing the message being emitted to the previously emitted
message.  If they are the same, I do not emit the message.  This change is also
tested by the new test array-constr-big.f90.

Several of the existing tests had duplicate error messages for the same source
line, and this change caused differences in their output.  So I adjusted the
tests to match the new message emitting behavior.

Differential Revision: https://reviews.llvm.org/D102210
The file was addedflang/test/Semantics/array-constr-big.f90
The file was modifiedflang/include/flang/Evaluate/shape.h
The file was modifiedflang/test/Semantics/omp-flush01.f90
The file was modifiedflang/lib/Parser/message.cpp
The file was modifiedflang/test/Semantics/omp-atomic.f90
The file was modifiedflang/include/flang/Parser/message.h
The file was modifiedflang/test/Semantics/allocate02.f90
The file was modifiedflang/test/Semantics/io06.f90
The file was modifiedflang/test/Semantics/resolve70.f90
The file was modifiedflang/test/Semantics/omp-clause-validity01.f90
Commit e0b6c99288bf1798ccc80aa0c5c7940c17665e69 by Lang Hames
Re-apply "[ORC-RT] Add unit test infrastructure, extensible_rtti..."

This reapplies 6d263b6f1c9 (which was reverted in 1c7c6f2b106) with a fix for a
CMake issue.
The file was addedcompiler-rt/lib/orc/unittests/orc_unit_test_main.cpp
The file was addedcompiler-rt/lib/orc/unittests/CMakeLists.txt
The file was removedcompiler-rt/lib/orc/placeholder.cpp
The file was addedcompiler-rt/lib/orc/unittests/extensible_rtti_test.cpp
The file was addedcompiler-rt/lib/orc/extensible_rtti.h
The file was modifiedcompiler-rt/cmake/config-ix.cmake
The file was modifiedcompiler-rt/lib/orc/CMakeLists.txt
The file was addedcompiler-rt/lib/orc/extensible_rtti.cpp
Commit 9ab49ae55dd7b928c2b806adccf6d07a89e59102 by thakis
[lld/mac] Implement -sectalign

clang sometimes passes this flag along (see D68351), so we should implement it.

Differential Revision: https://reviews.llvm.org/D102247
The file was modifiedlld/MachO/OutputSegment.cpp
The file was modifiedlld/MachO/Config.h
The file was addedlld/test/MachO/sectalign.s
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/MachO/Options.td
Commit 0fd0a010a1ed2ce761d20bfc6378e5bbaa75c8de by pirama
[git-clang-format] Do not apply clang-format to symlinks

This fixes PR46992.

Git stores symlinks as text files and we should not format them even if
they have one of the requested extensions.

(Move the call to `cd_to_toplevel()` up a few lines so we can also print
the skipped symlinks during verbose output.)

Differential Revision: https://reviews.llvm.org/D101878
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/tools/clang-format/git-clang-format
Commit 68de58cd649cb3a3e94a1c9552ebf2a18bb9d040 by martin
[libcxx] [test] Fix filesystem permission tests for windows

On Windows, the permission bits are mapped down to essentially only
two possible states; readonly or readwrite. Normalize the checked
permission bitmask to match what the implementation will return.

Differential Revision: https://reviews.llvm.org/D101728
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.permissions/permissions.pass.cpp
The file was modifiedlibcxx/test/support/filesystem_test_helper.h
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.copy_file/copy_file.pass.cpp
Commit 49755871ad0c24ed970c0a4f2c51f90488b0ddd2 by silvasean
[mlir][ODS]: Add per-op cppNamespace.

This is useful for dialects that have logical subparts.

Differential Revision: https://reviews.llvm.org/D102200
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/test/mlir-tblgen/dialect.td
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/include/mlir/TableGen/CodeGenHelpers.h
The file was modifiedmlir/include/mlir/TableGen/Operator.h
The file was modifiedmlir/lib/TableGen/Operator.cpp
Commit 61cbbba7a645a1d87db9a80867c84a788ab2ea9c by efriedma
[ArgumentPromotion] Fix byval alignment handling.

Make sure the alignment of the generated operations matches the
alignment of the byval argument.  Previously, we were just ignoring
alignment and getting lucky.

While I'm here, also delete the unnecessary "tail" handling.
Passing a pointer to a byval argument to a "tail" call is UB, so
rewriting to an alloca doesn't require any special handling.

Differential Revision: https://reviews.llvm.org/D89819
The file was modifiedllvm/test/Transforms/ArgumentPromotion/byval.ll
The file was modifiedllvm/test/Transforms/ArgumentPromotion/dbg.ll
The file was removedllvm/test/Transforms/ArgumentPromotion/tail.ll
The file was modifiedllvm/lib/Transforms/IPO/ArgumentPromotion.cpp
The file was modifiedllvm/test/Transforms/ArgumentPromotion/byval-2.ll
The file was modifiedllvm/test/Transforms/ArgumentPromotion/attrs.ll
Commit ec27c5f170441ab54295830aa9f7d376406c6a0f by i
[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local

Similar to X86 D73230 and AArch64 D101872

With this change, we can set dso_local in clang's -fpic -fno-semantic-interposition mode,
for default visibility external linkage non-ifunc-non-COMDAT definitions.

For such dso_local definitions, variable access/taking the address of a
function/calling a function will go through a local alias to avoid GOT/PLT.

Reviewed By: jrtc27, luismarques

Differential Revision: https://reviews.llvm.org/D101875
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp
The file was addedllvm/test/CodeGen/RISCV/elf-preemption.ll
Commit ae2b36e8bdfa612649c6f2d8b6b9079679cb2572 by Amara Emerson
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs.

This needs some tablegen changes so that we can actually import the patterns properly.

Differential Revision: https://reviews.llvm.org/D102204
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
Commit 129f466e222e13fdf680356831bb935e1229bdf4 by i
[GlobalOpt] Remove heap SROA

GlobalOpt implements a heap SROA (SROA for an malloc allocatated struct or array
of structs) which is largely undertested (heap-sra-[1234].ll are basically the
same test with very little difference) and does not trigger at all when
bootstrapping clang (it only supports the case of one single store).

The heap SROA implementation causes PR50027 (GEP is not properly handled; crash or miscompile).
Just drop the implementation. I have deleted some obviously duplicated tests
but kept `heap-sra-[12]{,-no-nullopt}.ll`.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D102257
The file was modifiedllvm/test/Transforms/GlobalOpt/MallocSROA-section.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-1.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-3.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-4-no-null-opt.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-2.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-phi.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-3-no-null-opt.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-4.ll
The file was modifiedllvm/lib/Transforms/IPO/GlobalOpt.cpp
Commit 97e04d41e646aa13b0cc5ff3812bfb7305fa4756 by lebedev.ri
[X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): canonicalize to integer type

This way we don't have to duplicate i32/f32 and i64/f64 entries,
which was already forgotten to be done for a few tuples.
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
Commit b2f227c6c87c16fa593e643a487efd9326249066 by sbc
[lld][WebAssembly] Convert test to assembly. NFC.

Differential Revision: https://reviews.llvm.org/D102264
The file was addedlld/test/wasm/reloc-addend.s
The file was removedlld/test/wasm/reloc-addend.ll
Commit 2075f2b296b0fa90cb7597f0f318232940d29e95 by i
[clang] Support -fpic -fno-semantic-interposition for RISCV

-fno-semantic-interposition (only effective with -fpic) can optimize default
visibility external linkage (non-ifunc-non-COMDAT) variable access and function
calls to avoid GOT/PLT, by using local aliases, e.g.
```
int var;
__attribute__((optnone)) int fun(int x) { return x * x; }
int test() { return fun(var); }
```

-fpic (var and fun are dso_preemptable)
```
test:
.LBB1_1:
        auipc   a0, %got_pcrel_hi(var)
        ld      a0, %pcrel_lo(.LBB1_1)(a0)
        lw      a0, 0(a0)
// fun is preemptible by default in ld -shared mode. ld will create a PLT.
        tail    fun@plt
```

vs -fpic -fno-semantic-interposition (var and fun are dso_local)
```
test:
.Ltest$local:
.LBB1_1:
        auipc   a0, %pcrel_hi(.Lvar$local)
        addi    a0, a0, %pcrel_lo(.LBB1_1)
        lw      a0, 0(a0)
// The assembler either resolves .Lfun$local at assembly time (-mno-relax
// -fno-function-sections), or produces a relocation referencing a non-preemptible
// local symbol (which can avoid PLT).
        tail    .Lfun$local
```

Note: Clang's default -fpic is more aggressive than GCC -fpic: interprocedural
optimizations (including inlining) are available but local aliases are not used.
-fpic -fsemantic-interposition can disable interprocedural optimizations.

Depends on D101875

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D101876
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/fsemantic-interposition.c
Commit f90abac6caab3b44e6a000de8cb72d204e74eb76 by michael.p.rice
[OpenMP] Use compound operators for reduction combiner if available.

The OpenMP spec seems to require the compound operators be used for
+, *, &, |, and ^ reduction.  So use these if a class has those operators.
If not try the simple operators as we did previously to limit the impact
to existing code.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=48584

Differential Revision: https://reviews.llvm.org/D101941
The file was modifiedclang/test/OpenMP/parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskgroup_task_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_master_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_reduction_messages.cpp
The file was addedclang/test/OpenMP/reduction_compound_op.cpp
The file was modifiedclang/test/OpenMP/target_teams_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/sections_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskloop_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/task_in_reduction_message.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskloop_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_sections_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_simd_reduction_messages.cpp
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/test/OpenMP/target_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
The file was modifiedclang/test/OpenMP/for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/distribute_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_reduction_messages.cpp
Commit 384dd9ddaf616a1563ee1c1a8a1347b7658e7a70 by vvereschaka
[libc++] Run `substitutes-in-compile-flags.sh.cpp` test on Windows.

Fix for substitutes-in-compile-flags.sh.cpp to run it properly on Windows platform.

Differential Revision: https://reviews.llvm.org/D102048
The file was modifiedlibcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-compile-flags.sh.cpp
Commit 9558b602b22cb7d681757c5f56d941e39a9d9d19 by jingham
Add an "interrupt timeout" to Process, and pipe that through the
ProcessGDBRemote plugin layers.

Also fix a bug where if we tried to interrupt, but the ReadPacket
wakeup timer woke us up just after the timeout, we would break out
the switch, but then since we immediately check if the response is
empty & fail if it is, we could end up actually only giving a
small interval to the interrupt.

Differential Revision: https://reviews.llvm.org/D102085
The file was modifiedlldb/test/API/functionalities/gdb_remote_client/TestHaltFails.py
The file was modifiedlldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
The file was modifiedlldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
The file was modifiedlldb/source/Target/Process.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteClientBase.cpp
The file was modifiedlldb/include/lldb/Target/Process.h
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
The file was modifiedlldb/unittests/Process/gdb-remote/GDBRemoteClientBaseTest.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteClientBase.h
The file was modifiedlldb/unittests/tools/lldb-server/tests/TestClient.cpp
The file was modifiedlldb/source/Target/TargetProperties.td
The file was modifiedlldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
Commit b49a798e71f922a68628ad9e31ca12fdb864c2f5 by sbc
[lld][WebAssembly] Remove relocation target verification

We have this extra step in wasm-ld that doesn't exist in other lld
backend which verifies the existing contents of the relocation targets.
This was originally intended as an extra form of double checking and an
aid to compiler developers.   However it has always been somewhat
controversial and there have been suggestions in the past the we simply
remove it.

My motivation for removing it now is that its causing me a headache
when trying to fix an issue with negative addends.  In the case of
negative addends that final result can be wrapped/negative but this
checking code would require significant modification to be able to deal
with that case.  For example with some test cases I'm looking at I'm
seeing error like this:

```
wasm-ld: warning: /usr/local/google/home/sbc/dev/wasm/llvm-build/tools/lld/test/wasm/Output/merge-string.s.tmp.o:(.rodata_relocs): unexpected existing value for R_WASM_MEMORY_ADDR_I32: existing=FFFFFFFA expected=FFFFFFFFFFFFFFFA
```

Rather than try to refactor `calcExpectedValue` to somehow return two
different types of results (32 and 64-bit) depending on the relocation
type, I think we can just remove this code.

Differential Revision: https://reviews.llvm.org/D102265
The file was modifiedlld/wasm/InputFiles.cpp
The file was modifiedlld/wasm/InputFiles.h
The file was modifiedlld/test/wasm/reloc-addend.s
The file was modifiedlld/wasm/InputChunks.cpp
Commit 731206f3684af5979e3a794970db83f9a34b4541 by riddleriver
[mlir] Move move capture in SparseElementsAttr::getValues

This was a TODO for the move to C++14. Now that the move has been completed, we can resolve it.
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.h
Commit 2a73b7bd8cf7620fc0e478ac838b07ee6649dd8a by Vitaly Buka
[NFC][LSAN] Limit the number of concurrent threads is the test

Test still fails with D88184 reverted.

The test was flaky on https://bugs.chromium.org/p/chromium/issues/detail?id=1206745 and
https://lab.llvm.org/buildbot/#/builders/sanitizer-x86_64-linux

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D102218
The file was modifiedcompiler-rt/test/lsan/TestCases/many_threads_detach.cpp
Commit 69069509b2d3cb0e0bcf6e38e0ab05c432adc763 by Amara Emerson
[AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.

One test needed updating because the newly side-effect-free instructions were
now being DCE'd.
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
Commit ffbffaf6b6b0fc06abb7b43ec8de8bc61d941bc7 by albionapc
[PowerPC] Improve codegen for int-to-fp conversion of subword vector extract

When an integer is converted into floating point in subword vector extract,
it can be done in 2 instructions instead of the 3+ instructions it generates
right now. This patch removes the uncessary generation.

Differential: https://reviews.llvm.org/D100604
The file was addedllvm/test/CodeGen/PowerPC/vec-extract-itofp.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
Commit 4fb0aaf03381473ec8af727edb4b5d59b64b0d60 by Andrey.Churbanov
[OpenMP] Changes to enable MSVC ARM64 build of libomp

This is the first in a series of changes to the OpenMP runtime
that have been done internally by Microsoft. This patch makes
the necessary changes to enable libomp.dll to build with
the MSVC compiler targeting ARM64.

Differential Revision: https://reviews.llvm.org/D101173
The file was modifiedopenmp/runtime/src/kmp.h
The file was modifiedopenmp/runtime/src/z_Windows_NT-586_util.cpp
The file was modifiedopenmp/runtime/src/dllexports
The file was modifiedopenmp/runtime/src/kmp_os.h
The file was modifiedopenmp/runtime/src/CMakeLists.txt
The file was modifiedopenmp/runtime/src/kmp_atomic.cpp
The file was modifiedopenmp/runtime/src/kmp_platform.h
Commit d092dd56aed8af64425446544ca7c9a0616d86ce by craig.topper
[RISCV] Regenerate stepvector.ll. NFC

It looks like the RV32 and RV64 prefixes were removed from the
RUN lines while another patch was in review that added check
lines that used them.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/stepvector.ll
Commit a7757f6c22e45e84e56da79af67fe29dd1c224f5 by eugenis
[hwasan] Stress test for thread creation.

This test has two modes - testing reused threads with multiple loops of
batch create/join, and testing new threads with a single loop of
create/join per fork.

The non-reuse variant catches the problem that was fixed in D101881 with
a high probability.

Differential Revision: https://reviews.llvm.org/D101936
The file was addedcompiler-rt/test/hwasan/TestCases/Linux/create-thread-stress.cpp
Commit 4433f4601e8a8e36ddd9bb6f6ed394bda353b828 by Austin.Kerbow
[AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2

The waitcnt pass would increment the number of vmem events for some buffer
invalidates that were not handled by the pass.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D102252
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Commit ebdcebfcb4b522a81290f67dcbb7222ff7f9d052 by aorlov
Removed unnecessary introduction of semi-colons.
The file was modifiedllvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
Commit a9bbbaaa8810b22c9672694d576e3a0a210af54a by riddleriver
[mlir] Elide large elements attrs when printing Operations in diagnostics

Diagnostics are intended to be read by users, and in most cases displayed in a terminal. When not eliding huge element attributes, in some cases we end up dumping hundreds of megabytes(gigabytes) to the terminal (or logs), completely obfuscating the main diagnostic being shown.

Differential Revision: https://reviews.llvm.org/D102272
The file was modifiedmlir/lib/IR/Diagnostics.cpp
Commit 764ad3b3fafbf57ca916715625fffb7df5dbeb92 by rob.suderman
[mlir][tosa] Tosa elementwise broadcasting had some minor bugs

Updated tests to include broadcast of left and right. Includes
bypass if in-type and out-type match shape (no broadcasting).

Differential Revision: https://reviews.llvm.org/D102276
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
Commit 15565403722ec37d8b1a3ee8625ee2e8efcd96ee by nikita.ppv
[InstCombine] Clean up one-hot merge optimization (NFC)

Remove the requirement that the instruction is a BinaryOperator,
make the predicate check more compact and use slightly more
meaningful naming for the and operands.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
Commit 3a64b7080d5033b3bd6f28fbac4a24d9490dc3c3 by evandro.menezes
[RISCV] Move instruction information into the RISCVII namespace (NFC)

Move instruction attributes into the `RISCVII` namespace and add associated helper functions.

Differential Revision: https://reviews.llvm.org/D102268
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp
Commit 489a3531a42fe97c7fa00255fc5e8d31a610492d by phosek
[llvm-cov] Support for v4 format in convert-for-testing

v4 moves function records to a dedicated section so we need to write
and read it separately.

https://reviews.llvm.org/D100535
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
The file was modifiedllvm/tools/llvm-cov/TestingSupport.cpp
Commit d3f89d4d16883b2bcf5f032152f10e384b53d92a by congzhecao
Revert "[LoopInterchange] Fix legality for triangular loops"

This reverts commit 29342291d25b83da97e74d75004b177ba41114fc.

The test case requires an assert build. Will add REQUIRES and re-commit.
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
The file was removedllvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
Commit 46475a79f85b230fde3e7de8966c96bef14f0d24 by wei.huang
[AIX][TLS] Diagnose use of unimplemented TLS models

Add front end diagnostics to report error for unimplemented TLS models set by
- compiler option `-ftls-model`
- attributes like `__thread int __attribute__((tls_model("local-exec"))) var_name;`

Reviewed by: aaron.ballman, nemanjai, PowerPC

Differential Revision: https://reviews.llvm.org/D102070
The file was addedclang/test/CodeGen/aix-tls-model.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was addedclang/test/Sema/aix-attr-tls_model.c
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
Commit cbcfca343f02876cef2b5ca3f27a037bab8fa90f by Lang Hames
[JITLink] Make LinkGraph debug dumps more readable.

This commit reorders some fields and fixes the width of others to try to
maintain more consistent columns. It also switches to long-hand scope
and linkage names, since LinkGraph dumps aren't read often enough for
single-character codes to be memorable.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/JITLink.cpp
Commit 74a96b4c98434e328eeca0afc85dc7053133a7d2 by Lang Hames
[JITLink][x86-64] Add an x86_64 PointerSize constexpr.

This can be used in place of magic '8' values in generic x86-64 utilities.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/x86_64.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
Commit a0162a81b1377331c3e0ebb58ac349b2ffd7b598 by Lang Hames
[JITLink][MachO/x86_64] Expose API for creating eh-frame fixing passes.

These can be used to create eh-frame section fixing passes outside the usual
linker pipeline, which can be useful for tests and tools that just want to
verify or dump graphs.
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/MachO_x86_64.h
The file was modifiedllvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
Commit 8280ece0c972db24e51aae5074ca5433002f1071 by phosek
[Coverage] Support overriding compilation directory

When making compilation relocatable, for example in distributed
compilation scenarios, we want to set compilation dir to a relative
value like `.` but this presents a problem when generating reports
because if the file path is relative as well, for example `..`, you
may end up writing files outside of the output directory.

This change introduces a flag that allows overriding the compilation
directory that's stored inside the profile with a different value that
is absolute.

Differential Revision: https://reviews.llvm.org/D100232
The file was addedllvm/test/tools/llvm-cov/Inputs/compilation_dir.covmapping
The file was modifiedllvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
The file was modifiedllvm/include/llvm/ProfileData/Coverage/CoverageMappingReader.h
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMapping.cpp
The file was modifiedllvm/tools/llvm-cov/CoverageViewOptions.h
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
The file was modifiedllvm/unittests/ProfileData/CoverageMappingTest.cpp
The file was addedllvm/test/tools/llvm-cov/Inputs/compilation_dir.proftext
The file was addedllvm/test/tools/llvm-cov/compilation_dir.c
The file was modifiedllvm/tools/llvm-cov/CodeCoverage.cpp
Commit 40e3aa39bd68b554808ddcb096a63919f53f2e43 by congzhecao
[LoopInterchange] Fix legality for triangular loops

This is a bug fix in legality check.

When we encounter triangular loops such as the following form:
    for (int i = 0; i < m; i++)
      for (int j = 0; j < i; j++), or

    for (int i = 0; i < m; i++)
      for (int j = 0; j*i < n; j++),

we should not perform interchange since the number of executions
of the loop body will be different before and after interchange,
resulting in incorrect results.

Reviewed By: bmahjour

Differential Revision: https://reviews.llvm.org/D101305
The file was addedllvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
Commit 5cb17728d19408725d4ced928ff3276dd4ffd1c9 by leonardchan
[clang][Fuchsia] Introduce compat multilibs

These are GCC-compatible multilibs that use the generic Itanium C++ ABI
instead of the Fuchsia C++ ABI.

Differential Revision: https://reviews.llvm.org/D102030
The file was addedclang/test/Driver/Inputs/basic_fuchsia_tree/lib/x86_64-unknown-fuchsia/compat/libc++.so
The file was modifiedclang/lib/Driver/ToolChains/Fuchsia.cpp
The file was modifiedclang/test/Driver/fuchsia.cpp
Commit d63860a05226d89f840a665134e2cb52c30ce4c4 by Lang Hames
[JITLink] Fix bogus format string.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/JITLink.cpp
Commit fec2945998947f04d672e9c5f33b57f7177474c0 by rupprecht
Revert "[GVN] Clobber partially aliased loads."

This reverts commit 6c570442318e2d3b8b13e95c2f2f588d71491acb.

It causes assertion errors due to widening atomic loads, and potentially causes miscompile elsewhere too. Repro, also posted to D95543:

```
$ cat repro.ll
; ModuleID = 'repro.ll'
source_filename = "repro.ll"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.widget = type { i32 }
%struct.baz = type { i32, %struct.snork }
%struct.snork = type { %struct.spam }
%struct.spam = type { i32, i32 }

@global = external local_unnamed_addr global %struct.widget, align 4
@global.1 = external local_unnamed_addr global i8, align 1
@global.2 = external local_unnamed_addr global i32, align 4

define void @zot(%struct.baz* %arg) local_unnamed_addr align 2 {
bb:
  %tmp = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1
  %tmp1 = bitcast %struct.snork* %tmp to i64*
  %tmp2 = load i64, i64* %tmp1, align 4
  %tmp3 = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1, i32 0, i32 1
  %tmp4 = icmp ugt i64 %tmp2, 4294967295
  br label %bb5

bb5:                                              ; preds = %bb14, %bb
  %tmp6 = load i32, i32* %tmp3, align 4
  %tmp7 = icmp ne i32 %tmp6, 0
  %tmp8 = select i1 %tmp7, i1 %tmp4, i1 false
  %tmp9 = zext i1 %tmp8 to i8
  store i8 %tmp9, i8* @global.1, align 1
  %tmp10 = load i32, i32* @global.2, align 4
  switch i32 %tmp10, label %bb11 [
    i32 1, label %bb12
    i32 2, label %bb12
  ]

bb11:                                             ; preds = %bb5
  br label %bb14

bb12:                                             ; preds = %bb5, %bb5
  %tmp13 = load atomic i32, i32* getelementptr inbounds (%struct.widget, %struct.widget* @global, i64 0, i32 0) acquire, align 4
  br label %bb14

bb14:                                             ; preds = %bb12, %bb11
  br label %bb5
}
$ opt -O2 repro.ll -disable-output
opt: /home/rupprecht/src/llvm-project/llvm/lib/Transforms/Utils/VNCoercion.cpp:496: llvm::Value *llvm::VNCoercion::getLoadValueForLoad(llvm::LoadInst *, unsigned int, llvm::Type *, llvm::Instruction *, const llvm::DataLayout &): Assertion `SrcVal->isSimple() && "Cannot widen volatile/atomic load!"' failed.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.      Program arguments: /home/rupprecht/dev/opt -O2 repro.ll -disable-output
...
```
The file was modifiedllvm/lib/Analysis/MemoryDependenceAnalysis.cpp
The file was modifiedllvm/test/Transforms/GVN/PRE/rle.ll
The file was modifiedllvm/lib/Transforms/Scalar/GVN.cpp
The file was modifiedllvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
Commit 2bdfcf0cac148ada8d3ec36f551c45efb604ac49 by Matthew.Arsenault
GlobalISel: Move AArch64 AssignFnVarArg to base class

We can handle the distinction easily enough in the generic code, and
this makes it easier to abstract the selection of type/location from
the code to insert code.
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
Commit 24e2e5df0e7eb017c64142c1f5899146fa52abba by Matthew.Arsenault
GlobalISel: Split ValueHandler into assignment and emission classes

Currently the ValueHandler handles both selecting the type and
location for arguments, as well as inserting instructions needed to
handle them. Split this so that the determination of the argument
handling is independent of the function state. Currently the checks
for tail call compatibility do not follow the full assignment logic,
so it misses cases where arguments require nontrivial legalization.

This should help avoid targets ending up in a buggy state where the
argument evaluation may change in different contexts.
The file was modifiedllvm/lib/Target/X86/X86CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMCallLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
Commit 6ecbdb761ffd684dc5fe624c0058fe7527a01881 by Matthew.Arsenault
GlobalISel: Make constant fields const
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
Commit a15ed701ab30d0073f46139df850fe23b03fd3ac by Matthew.Arsenault
AMDGPU: Fix assert on constant load from addrspacecasted pointer

This was trying to create a bitcast between different address spaces.
The file was addedllvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
Commit 6f5ddf67319b50664f3f5a4001723454696594b4 by Matthew.Arsenault
GlobalISel: Don't hardcode varargs=false in resultsCompatible
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit 697ac15a0fc71888c372667bdbc5583ab42d4695 by richard
Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope.

This implements the direction proposed in
https://github.com/itanium-cxx-abi/cxx-abi/pull/126.

Differential Revision: https://reviews.llvm.org/D101968
The file was modifiedclang/test/CodeGenCXX/mangle-lambda-explicit-template-params.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.h
The file was modifiedclang/test/CodeGenCXX/clang-abi-compat.cpp
The file was modifiedclang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.h
Commit 3978333b71bff3516ad69aac484b808617976c7a by richard
Add test for PR50039.

I believe Clang's behavior is correct according to the standard here,
but this is an unusual situation for which we had no test coverage, so
I'm adding some.
The file was modifiedclang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp
Commit bb726383ac7554857c62edd2d19e83dc713165ee by richard
Revert "Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope."

This reverts commit 697ac15a0fc71888c372667bdbc5583ab42d4695, for which
review was not complete. That change was accidentally pushed when
an unrelated change was pushed.
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/test/CodeGenCXX/clang-abi-compat.cpp
The file was modifiedclang/test/CodeGenCXX/mangle-lambda-explicit-template-params.cpp
The file was modifiedclang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.h
Commit 19cedd3cd3ab2144f7e477bb90d5f7ba8e500abb by sbc
[lld][WebAssembly] Fix for string merging + negative addends

Don't include the relocation addend when calculating the
virtual address of a symbol.  Instead just pass the symbol's
offset and add the addend afterwards.

Without this fix we hit the `offset is outside the section`
error in MergeInputSegment::getSegmentPiece.

This fixes a real world error we were are seeing in emscripten.

Differential Revision: https://reviews.llvm.org/D102271
The file was modifiedlld/test/wasm/merge-string.s
The file was modifiedlld/wasm/Symbols.cpp
The file was modifiedlld/wasm/InputFiles.cpp
The file was modifiedlld/wasm/Symbols.h
Commit 0f2eb7e6e5dc2c1b5d1080160733b3a49e00c99c by jingham
This test is failing on Linux, skip while I investigate.

The gdb-remote tests are a bit artificial, depending on
Python threading, and sleeps.  So I'm not 100% surprised it doesn't
work straight up on another XSsystem.
The file was modifiedlldb/test/API/functionalities/gdb_remote_client/TestHaltFails.py
Commit cc79aaced0a405c7448c832a0974a694494496ca by Matthew.Arsenault
AMDGPU: Fix SILoadStoreOptimizer for gfx90a

This was hardcoding the register class to use for the newly created
pointer registers, violating the aligned VGPR requirement.
The file was modifiedllvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
The file was addedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
Commit 10c309ad81e2be156ab44a83ee56cddea20637cc by jingham
Removing test...

Actually, I don't think this test is going to be stable enough
to be worthwhile.  Let me see if I can think of a better way to
test this.
The file was removedlldb/test/API/functionalities/gdb_remote_client/TestHaltFails.py
Commit 3f8be15f2911a3d3645030911be83a115bfe9e5c by congzhecao
[LoopInterchange] Handle lcssa PHIs with multiple predecessors

This is a bugfix in the transformation phase.

If the original outer loop header branches to both the inner loop
(header) and the outer loop latch, and if there is an lcssa PHI
node outside the loop nest, then after interchange the new outer latch
will have an lcssa PHI node inserted which has two predecessors, i.e.,
the original outer header and the original outer latch. Currently
the transformation assumes it has only one predecessor (the original
outer latch) and crashes, since the inserted lcssa PHI node does
not take both predecessors as incoming BBs.

Reviewed By: Whitney

Differential Revision: https://reviews.llvm.org/D100792
The file was modifiedllvm/test/Transforms/LoopInterchange/lcssa.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
Commit 7d101e0f6a38b95f512dc5d78bc9b508f4ee6da0 by Vitaly Buka
[NFC][msan] Move setlocale test into sanitizer_common
The file was addedcompiler-rt/test/sanitizer_common/TestCases/setlocale.cpp
The file was removedcompiler-rt/test/msan/setlocale.cpp
Commit f653313d4aec6f92b224ef996a8ac236dbb48baf by chiahungduan
[mlir][AsmPrinter] Remove recursion while SSA naming

Address the TODO of removing recursion while SSA naming.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D102226
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
Commit 04b2ada51c90a76b153eedafd8d52a2649695a7f by dvyukov
tsan: add a simple syscall test

Add a simple test that uses syscall annotations.
Just to ensure at least basic functionality works.
Also factor out annotated syscall wrappers into a separate
header file as they may be useful for future tests.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102223
The file was addedcompiler-rt/test/tsan/Linux/syscall.cpp
The file was modifiedcompiler-rt/test/tsan/Linux/fork_syscall.cpp
The file was addedcompiler-rt/test/tsan/Linux/syscall.h
Commit 5dad3d1ba9ad01152be21e94cfbbfb31659ea3e1 by dvyukov
tsan: mark sigwait as blocking

Add a test case reported in:
https://github.com/google/sanitizers/issues/1401
and fix it.
The code assumes sigwait will process other signals.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102057
The file was addedcompiler-rt/test/tsan/signal_block2.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Commit 6d2df181638a34f5d4ebc0c92cfb6a30abf8588d by qiucofan
[VectorComine] Restrict single-element-store index to inbounds constant

Vector single element update optimization is landed in 2db4979. But the
scope needs restriction. This patch restricts the index to inbounds and
vector must be fixed sized. In future, we may use value tracking to
relax constant restrictions.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D102146
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll
Commit 8214764f35e1b764fb939e18f16e11aa43073469 by dvyukov
tsan: declare annotations in test.h

We already declare subset of annotations in test.h.
But some are duplicated and declared in tests.
Move all annotation declarations to test.h.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102152
The file was modifiedcompiler-rt/test/tsan/thread_name.cpp
The file was modifiedcompiler-rt/test/tsan/annotate_happens_before.cpp
The file was modifiedcompiler-rt/test/tsan/mutexset5.cpp
The file was modifiedcompiler-rt/test/tsan/ignore_sync.cpp
The file was modifiedcompiler-rt/test/tsan/thread_end_with_ignore3.cpp
The file was modifiedcompiler-rt/test/tsan/thread_end_with_ignore2.cpp
The file was modifiedcompiler-rt/test/tsan/test.h
The file was modifiedcompiler-rt/test/tsan/mutex_bad_read_lock.cpp
The file was modifiedcompiler-rt/test/tsan/mutex_bad_read_unlock.cpp
The file was modifiedcompiler-rt/test/tsan/mutex_bad_unlock.cpp
The file was modifiedcompiler-rt/test/tsan/mutex_double_lock.cpp
The file was modifiedcompiler-rt/test/tsan/thread_end_with_ignore.cpp
The file was modifiedcompiler-rt/test/tsan/benign_race.cpp
The file was modifiedcompiler-rt/test/tsan/signal_sync2.cpp
Commit 53558ed8a0abaf2f457cfa3d98c85d0fa1e84b22 by dvyukov
sanitizer_common: fix SIG_DFL warning

Currently we have:

sanitizer_posix_libcdep.cpp:146:27: warning: cast between incompatible
  function types from ‘__sighandler_t’ {aka ‘void (*)(int)’} to ‘sa_sigaction_t’
  146 |     sigact.sa_sigaction = (sa_sigaction_t)SIG_DFL;

We don't set SA_SIGINFO, so we need to assign to sa_handler.
And SIG_DFL is meant for sa_handler, so this gets rid of both
compiler warning, type cast and potential runtime misbehavior.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102162
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_posix_libcdep.cpp
Commit 85a96d82ca76819df56c97b6b3b5d5d98a030d5d by Vitaly Buka
[symbolizer] Fix leak after D96883
The file was modifiedllvm/lib/DebugInfo/Symbolize/DIPrinter.cpp
Commit 23596fece043fa04206dcd5b26b4ca832e6741db by dvyukov
sanitizer_common: don't write into .rodata

setlocale interceptor imitates a write into result,
which may be located in .rodata section.
This is the only interceptor that tries to do this and
I think the intention was to initialize the range for msan.
So do that instead. Writing into .rodata shouldn't happen
(without crashing later on the actual write) and this
traps on my local tsan experiments.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102161
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Commit f8306647fa05b7bf84dff12d731d03abf53b45fe by kbessonova
[libcxx][test] Split more debug mode tests

Split a few more debug mode tests missed in D100592.

Differential Revision: https://reviews.llvm.org/D102194
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db2.pass.cpp
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db3.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db6.pass.cpp
The file was addedlibcxx/test/libcxx/containers/sequences/vector/db_cindex_2.pass.cpp
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_db2.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_db4.pass.cpp
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db1.pass.cpp
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db4.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db8.pass.cpp
The file was modifiedlibcxx/test/libcxx/containers/sequences/vector/db_cindex.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db5.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_db3.pass.cpp
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_db1.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db7.pass.cpp
Commit febbe4b5a0ab0cb6f8ada6cd1ead4bb1f565bda8 by qiucofan
[PowerPC] [Clang] Enable float128 feature on VSX targets

Reviewed By: nemanjai, steven.zhang

Differential Revision: https://reviews.llvm.org/D92815
The file was modifiedclang/test/Driver/ppc-f128-support-check.c
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
Commit 2721e27c3aa34841db3fc0b4da25890288652d50 by dvyukov
sanitizer_common: deduplicate CheckFailed

We have some significant amount of duplication around
CheckFailed functionality. Each sanitizer copy-pasted
a chunk of code. Some got random improvements like
dealing with recursive failures better. These improvements
could benefit all sanitizers, but they don't.

Deduplicate CheckFailed logic across sanitizers and let each
sanitizer only print the current stack trace.
I've tried to dedup stack printing as well,
but this got me into cmake hell. So let's keep this part
duplicated in each sanitizer for now.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102221
The file was modifiedcompiler-rt/lib/hwasan/hwasan.h
The file was modifiedcompiler-rt/lib/memprof/memprof_rtl.cpp
The file was modifiedcompiler-rt/test/msan/check-handler.cpp
The file was modifiedcompiler-rt/lib/hwasan/hwasan.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
The file was modifiedcompiler-rt/lib/asan/asan_stack.h
The file was modifiedcompiler-rt/lib/msan/msan.cpp
The file was modifiedcompiler-rt/lib/asan/asan_rtl.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_termination.cpp
The file was modifiedcompiler-rt/lib/msan/msan.h
The file was modifiedcompiler-rt/lib/memprof/memprof_stack.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
Commit 382c505d9cfca8adaec47aea2da7bbcbc00fc05c by martin
[COFF] Fix ARM and ARM64 REL32 relocations to be relative to the end of the relocation

This matches how they are defined on X86.

This should fix the relative lookup tables pass for COFF, allowing
it to be reenabled.

Differential Revision: https://reviews.llvm.org/D102217
The file was modifiedllvm/test/MC/ARM/coff-relocations.s
The file was modifiedllvm/test/MC/AArch64/coff-relocations.s
The file was modifiedllvm/lib/MC/WinCOFFObjectWriter.cpp
Commit 1dc838717a294ed7bfd7d597d427886ce61df122 by dvyukov
tsan: fix syscall test on aarch64

Add missing includes and use SYS_pipe2 instead of SYS_pipe
as it's not present on some arches.

Differential Revision: https://reviews.llvm.org/D102311
The file was modifiedcompiler-rt/test/tsan/Linux/syscall.h
Commit 9a0ea5994bdc477d77fd4d9f4eb5d34b1ac4184a by zinenko
[mlir] Support alignment in LLVM dialect GlobalOp

First step in adding alignment as an attribute to MLIR global definitions. Alignment can be specified for global objects in LLVM IR. It can also be specified as a named attribute in the LLVMIR dialect of MLIR. However, this attribute has no standing and is discarded during translation from MLIR to LLVM IR. This patch does two things: First, it adds the attribute to the syntax of the llvm.mlir.global operation, and by doing this it also adds accessors and verifications. The syntax is "align=XX" (with XX being an integer), placed right after the value of the operation. Second, it allows transforming this operation to and from LLVM IR. It is checked whether the value is an integer power of 2.

Reviewed By: ftynse, mehdi_amini

Differential Revision: https://reviews.llvm.org/D101492
The file was modifiedmlir/test/Dialect/LLVMIR/invalid.mlir
The file was modifiedmlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
The file was modifiedmlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
The file was modifiedmlir/test/Dialect/LLVMIR/global.mlir
The file was modifiedmlir/test/Target/LLVMIR/import.ll
The file was modifiedmlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
The file was modifiedmlir/test/Target/LLVMIR/llvmir.mlir
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
The file was modifiedmlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
The file was modifiedmlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
The file was modifiedmlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
Commit 27b2bd76017f5b486b96ad782bfb28e1b28b5088 by zinenko
[MLIR] Enable conversion from llvm::SMLoc to mlir::Location with OpAsmParser.

DialectAsmParser already allows converting an llvm::SMLoc location to a
mlir::Location location. This commit adds the same functionality to OpAsmParser.
Implementation is copied from DialectAsmParser.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D102165
The file was modifiedmlir/include/mlir/IR/OpImplementation.h
The file was modifiedmlir/lib/Parser/Parser.cpp
Commit 8aa7f28497b6794ca659f1b729a6e8ce312c54e2 by dvyukov
scudo: fix CheckFailed-related build breakage

I was running:

$ ninja check-sanitizer check-msan check-asan \
  check-tsan check-lsan check-ubsan check-cfi \
  check-profile check-memprof check-xray check-hwasan

but missed check-scudo...

Differential Revision: https://reviews.llvm.org/D102314
The file was modifiedcompiler-rt/lib/scudo/scudo_termination.cpp
Commit 6351993da72e298b3f79218e4f129a9bbde3e679 by gchatelet
[libc] Simplifies multi implementations

This is a roll forward of D101895 with two additional fixes:

Original Patch description:
> This is a follow up on D101524 which:
>
> - simplifies cpu features detection and usage,
> - flattens target dependent optimizations so it's obvious which implementations are generated,
> - provides an implementation targeting the host (march/mtune=native) for the mem* functions,
> - makes sure all implementations are unittested (provided the host can run them).

Additional fixes:
- Fix uninitialized ALL_CPU_FEATURES
- Use non pseudo microarch as it is only supported from Clang 12 on

Differential Revision: https://reviews.llvm.org/D102233
The file was modifiedlibc/src/string/CMakeLists.txt
The file was removedlibc/src/string/x86_64/CMakeLists.txt
The file was modifiedlibc/test/src/string/CMakeLists.txt
The file was modifiedlibc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake
The file was removedlibc/src/string/aarch64/CMakeLists.txt
Commit 44642505ce6be476124575f1589552bd53a6fdeb by djtodoro
[NFC][llvm-dwarfdump] Avoid passing std::string by value in collectStatsForDie()
The file was modifiedllvm/tools/llvm-dwarfdump/Statistics.cpp
Commit d8e65585f7c7cddd63920d122a9e6368d91c9389 by aorlov
Fixed llvm-objcopy to add correct symbol table for ELF with program headers.

This fixes the following bugs:
https://bugs.llvm.org/show_bug.cgi?id=43935

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D102258
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/add-symbol-no-symtab.test
The file was modifiedllvm/tools/llvm-objcopy/ELF/Object.cpp
Commit edf9d88266376a693b07668f733034d2f6b22072 by tomas.matheson
[ARM] Precommit test for D101898

Differential Revision: https://reviews.llvm.org/D101912
The file was addedllvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
Commit 34c098b780a27a90b5614ea3b949b9269835f2a5 by tomas.matheson
[ARM] Prevent spilling between ldrex/strex pairs

Based on the same for AArch64: 4751cadcca45984d7671e594ce95aed8fe030bf1

At -O0, the fast register allocator may insert spills between the ldrex and
strex instructions inserted by AtomicExpandPass when expanding atomicrmw
instructions in LL/SC loops. To avoid this, expand to cmpxchg loops and
therefore expand the cmpxchg pseudos after register allocation.

Required a tweak to ARMExpandPseudo::ExpandCMP_SWAP to use the 4-byte encoding
of UXT, since the pseudo instruction can be allocated a high register (R8-R15)
which the 2-byte encoding doesn't support. However, the 4-byte encodings
are not present for ARM v8-M Baseline. To enable this, two new pseudos are
added for Thumb which are only valid for v8mbase, tCMP_SWAP_8 and
tCMP_SWAP_16.

The previously committed attempt in D101164 had to be reverted due to runtime
failures in the test suites. Rather than spending time fixing that
implementation (adding another implementation of atomic operations and more
divergence between backends) I have chosen to follow the approach taken in
D101163.

Differential Revision: https://reviews.llvm.org/D101898

Depends on D101912
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
The file was modifiedllvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb.td
Commit cbd93cee9bf014402a7405479ba21f6f3340a126 by qiucofan
Revert "[PowerPC] [Clang] Enable float128 feature on VSX targets"

This commit brought build break in some f128 related tests. But that's
not the root cause. There exists some differences between Clang and
GCC's definition for 128-bit float types on PPC, so macros/functions in
glibc may not work with clang -mfloat128 well. We need to handle this
carefully and reland it.
The file was modifiedclang/test/Driver/ppc-f128-support-check.c
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
Commit 68137ef5682f936a5db14202a69548eee6294256 by Piotr Sobczak
[AMDGPU] Skip invariant loads when avoiding WAR conflicts

No need to handle invariant loads when avoiding WAR conflicts, as
there cannot be a vector store to the same memory location.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D101177
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-realign.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
Commit 5af3a6645f38e5638b4ba03613ee18140f36962d by david.spickett
Remove Windows editline from LLDB

I don't mean to undo others' work but it looks like the hand-rolled EditLine for LLDB on Windows isn't used.  It'd be easier to make changes to bring the other platforms' Editline wrapper up to date (e.g. simplifying char vs wchar_t) without modifying/testing this one too.

Reviewed By: amccarth

Differential Revision: https://reviews.llvm.org/D102208
The file was modifiedlldb/include/lldb/Host/Editline.h
The file was modifiedlldb/source/Host/CMakeLists.txt
The file was removedlldb/include/lldb/Host/windows/editlinewin.h
The file was removedlldb/source/Host/windows/EditLineWin.cpp
Commit fdb055f4f139e225884109fbffa275bd3eb3d3b9 by stephen.tozer
Reapply "[DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST"

Previous crashes caused by this patch were the result of machine
subregisters being incorrectly handled in updateDbgUsersToReg; this has
been fixed by using RegUnits to determine overlapping registers, instead
of using the register values directly.

Differential Revision: https://reviews.llvm.org/D101523

This reverts commit 7ca26c5fa2df253878cab22e1e2f0d6f1b481218.
The file was addedllvm/test/DebugInfo/ARM/machine-cp-updates-dbg-reg.mir
The file was modifiedllvm/lib/CodeGen/MachineCopyPropagation.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineRegisterInfo.h
Commit b6c0edb9792c1a216961aefb63783ab4b986e823 by mgorny
[lldb] [Process/elf-core] Fix reading FPRs from FreeBSD/i386 cores

The FreeBSD coredumps from i386 systems contain only FSAVE-style
NT_FPREGSET.  Since we do not really support reading that kind of data
anymore, just use NT_X86_XSTATE to get FXSAVE-style data when available.

Differential Revision: https://reviews.llvm.org/D101086
The file was modifiedlldb/source/Plugins/Process/elf-core/RegisterUtilities.h
The file was modifiedlldb/test/Shell/Register/Core/x86-32-freebsd-addr.test
The file was addedlldb/test/Shell/Register/Core/x86-32-freebsd-fp.test
Commit 71e66da04cf15cf47045b5d1482803197a24a75d by mgorny
[Process/elf-core] Read PID from FreeBSD prpsinfo

Add a function to read NT_PRPSINFO note from FreeBSD core dumps.  This
is necessary to get the process ID (NT_PRSTATUS has only thread ID).
Move the lp64 check from NT_PRSTATUS parsing to the parseFreeBSDNotes()
to avoid repeating it.

Differential Revision: https://reviews.llvm.org/D101893
The file was modifiedlldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
Commit 6e6f9a636b1917f366821fb0a5c37cde19634c7a by peter.waller
[AArch64][SVE] Improve sve.convert.to.svbool lowering

The sve.convert.to.svbool lowering has the effect of widening a logical
<M x i1> vector representing lanes into a physical <16 x i1> vector
representing bits in a predicate register.

In general, if converting to svbool, the contents of lanes in the
physical register might not be known. For sve.convert.to.svbool the new
lanes are specified to be zeroed, requiring 'and' instructions to mask
off the new lanes. For lanes coming from a ptrue or a comparison,
however, they are known to be zero.

CodeGen Before:
  ptrue p0.s, vl16
  ptrue p1.s
  ptrue p2.b
  and   p0.b, p2/z, p0.b, p1.b
  ret

After:
  ptrue p0.s, vl16
  ret

Differential Revision: https://reviews.llvm.org/D101544
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit b7a11274f90f07537e2151fa4424db257ff9a950 by david.sherwood
[LoopVectorize] Fix scalarisation crash in widenPHIInstruction for scalable vectors

In InnerLoopVectorizer::widenPHIInstruction there are cases where we have
to scalarise a pointer induction variable after vectorisation. For scalable
vectors we already deal with the case where the pointer induction variable
is uniform, but we currently crash if not uniform. For fixed width vectors
we calculate every lane of the scalarised pointer induction variable for a
given VF, however this cannot work for scalable vectors. In this case I
have added support for caching the whole vector value for each unrolled
part so that we can always extract an arbitrary element. Additionally, we
still continue to cache the known minimum number of lanes too in order
to improve code quality by avoiding an extractelement operation.

I have adapted an existing test `pointer_iv_mixed` from the file:

  Transforms/LoopVectorize/consecutive-ptr-uniforms.ll

and added it here for scalable vectors instead:

  Transforms/LoopVectorize/AArch64/sve-widen-phi.ll

Differential Revision: https://reviews.llvm.org/D101294
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 725bc3eb0d5cdce1952e2848c1f170c808d0acde by gbreynoo
[llvm-symbolizer] Place Mach-O options into the Mach-O option group.

In the help output of other tools and in the symbolizer command guide,
Mach-O specific options are in their own section. This change fixes the
symbolizer help output to be consistent.

Differential Revision: https://reviews.llvm.org/D102178
The file was modifiedllvm/tools/llvm-symbolizer/Opts.td
Commit 81900dc4982dc03da859a75c927e1bba95837c30 by gbreynoo
[llvm-readelf] Unhide short options to match the command guide

The readelf command guide shows the short options used as aliases but
these are not found in the help text unless --show-hidden is used, other
tools show aliases with --help. This change fixes the help output to be
consistent with the command guide.

Differential Revision: https://reviews.llvm.org/D102173
The file was modifiedllvm/tools/llvm-readobj/llvm-readobj.cpp
Commit 72e242a286be1c821c521fdc8a778517b193a59e by llvm-dev
[X86][AVX] canonicalizeShuffleMaskWithHorizOp - improve support for 256/512-bit vectors

Extend the HOP(HOP(X,Y),HOP(Z,W)) and SHUFFLE(HOP(X,Y),HOP(Z,W)) folds to handle repeating 256/512-bit vector cases.

This allows us to drop the UNPACK(HOP(),HOP()) custom fold in combineTargetShuffle.

This required isRepeatedTargetShuffleMask to be tweaked to support target shuffle masks taking more than 2 inputs.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle.ll
Commit 96100f15082679b2c75c7744b8eb4fc87fcf71f5 by kbessonova
[libcxx] NFC. Correct wordings of _LIBCPP_ASSERT debug messages

Differential Revision: https://reviews.llvm.org/D102195
The file was modifiedlibcxx/include/__hash_table
The file was modifiedlibcxx/include/vector
The file was modifiedlibcxx/include/list
The file was modifiedlibcxx/include/deque
The file was modifiedlibcxx/include/optional
The file was modifiedlibcxx/include/iterator
Commit 0fb364a97e74abd3d3700b8f18bbfed787fbfdbb by gysit
[mlir][linalg] Remove IndexedGenericOp support from LinalgToStandard...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102236
The file was modifiedmlir/include/mlir/Conversion/LinalgToStandard/LinalgToStandard.h
The file was modifiedmlir/lib/Conversion/LinalgToStandard/LinalgToStandard.cpp
The file was modifiedmlir/test/Dialect/Linalg/standard.mlir
Commit 163325086c35b3984c5e6f7a2adb6022003fcd84 by n.james93
[clang-tidy] Enable the use of IgnoreArray flag in pro-type-member-init rule

The `IgnoreArray` flag was not used before while running the rule. Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=47288 | b/47288 ]]

Reviewed By: njames93

Differential Revision: https://reviews.llvm.org/D101239
The file was modifiedclang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeMemberInitCheck.cpp
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-pro-type-member-init.ignorearrays.cpp
Commit 7d0a81ca38e427de9b7fb0961ec643b757028131 by david.spickett
Revert "[scudo] Enable arm32 arch"

This reverts commit b1a77e465e37fc400c16f9fda2a637f11c698bb9.

Which has a failing test on our armv7 bots:
https://lab.llvm.org/buildbot/#/builders/59/builds/1812
The file was modifiedcompiler-rt/cmake/config-ix.cmake
Commit c6b96ae06f70bd0ecd28995ffc45d87edd89a84d by gysit
[mlir][linalg] Remove IndexedGenericOp support from LinalgBufferize...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102308
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp
The file was modifiedmlir/test/Dialect/Linalg/bufferize.mlir
Commit 4c59ab34f7bda74296e42ef7ea8d83828cb45558 by n.james93
[clang-tidy][NFC] Simplify a lot of bugprone-sizeof-expression matchers

There should be a follow up to this for changing the traversal mode, but some of the tests don't like that.

Reviewed By: steveire

Differential Revision: https://reviews.llvm.org/D101614
The file was modifiedclang-tools-extra/clang-tidy/bugprone/SizeofExpressionCheck.cpp
Commit 24d06fff55510780eba1a267d844ee26a17d6888 by spatel
[x86] add test for pcmpeq with 0; NFC
The file was modifiedllvm/test/CodeGen/X86/setcc-lowering.ll
Commit f58e0513dd95944b81ce7a6e7b49ba656de7d75f by spatel
[x86] try harder to lower to PCMPGT instead of not-of-PCMPEQ

This is motivated by the example in https://llvm.org/PR50055 ,
but it doesn't do anything for that bug currently because we
don't actually have a zero-extended setcc there.

Proof for the generic transform (inverse of what we would
try to do in combining):
https://alive2.llvm.org/ce/z/aBL-Mg

Differential Revision: https://reviews.llvm.org/D102275
The file was modifiedllvm/test/CodeGen/X86/vsel-cmp-load.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/setcc-lowering.ll
The file was modifiedllvm/test/CodeGen/X86/vec_umulo.ll
Commit a4db7025a9762c568c7bc9fdd3c64f4a60e31cfc by Piotr Sobczak
[AMDGPU] Remove assert

Remove assert introduced in D101177, following post-commit feedback.
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Commit 06bb9cf30d11247540d5b3f2a714f3aa640353e6 by gysit
[mlir][linalg] Remove IndexedGenericOp support from LinalgInterchangePattern...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102245
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
The file was modifiedmlir/test/lib/Transforms/TestLinalgTransforms.cpp
The file was modifiedmlir/test/Dialect/Linalg/transform-patterns.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Interchange.cpp
Commit a383d325f6c6c8d9bb52d1da221d9a144dfc475c by jay.foad
[TargetRegisterInfo] Speed up getAllocatableSet. NFCI.

MachineRegisterInfo caches the reserved register set that is computed by
by TargetRegisterInfo::getReservedRegs, so call into MRI to get the
reserved regs to avoid recomputing them.

In particular this speeds up AMDGPU's SIFormMemoryClauses pass because
AMDGPU has a particularly complicated reserved set that is expensive to
compute.

Differential Revision: https://reviews.llvm.org/D102318
The file was modifiedllvm/lib/CodeGen/TargetRegisterInfo.cpp
Commit 554b1bced325a8d860ad00bd59020d66d01c95f8 by lebedev.ri
[InstCombine] ~(C + X) --> ~C - X (PR50308)

We can not rely on (C+X)-->(X+C) already happening,
because we might not have visited that `add` yet.
The added testcase would get stuck in an endless combine loop.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/not-add.ll
Commit 46adccc5cc1095f57b65fb2a17a4a023ccc77eb9 by jay.foad
[AMDGPU] Improve Codegen for build_vector

Improve the code generation of build_vector.
Use the v_pack_b32_f16 instruction instead of
v_and_b32 + v_lshl_or_b32

Differential Revision: https://reviews.llvm.org/D98081

Patch by Julien Pagès!
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.round.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/frem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fpow.ll
The file was addedllvm/test/CodeGen/AMDGPU/v_pack.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/fexp.ll
Commit 5a439015393e616b2faed9a9fbb1d7036b28e786 by gkm
[llvm-objdump] Exclude __mh_*_header symbols during MachO disassembly

`__mh_(execute|dylib|dylinker|bundle|preload|object)_header` are special symbols whose values hold the VMA of the Mach header to support introspection. They are attached to the first section in `__TEXT`, even though their addresses are outside `__TEXT`, and they do not refer to code.

It is normally harmless, but when the first section of `__TEXT` has no other symbols, `__mh_*_header` is considered by the disassembler when determing function boundaries. Since `__mh_*_header` refers to an address outside `__TEXT`, the boundary determination fails and disassembly quits.

Since `__TEXT,__text` normally has symbols, this bug is obscured. Experiments placing `__stubs` and `__stub_helper` first exposed the bug, since neither has symbols.

Differential Revision: https://reviews.llvm.org/D101786
The file was addedllvm/test/tools/llvm-objdump/MachO/no-text-symbols-disassembly.test
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
Commit 4b98199ce8fb94d0de46e04b4d7b3a699691d2e1 by martin
[Passes] Reenable the relative lookup table converter pass for ELF and COFF on aarch64

The bug (PR50227, affecting COFF) that caused the revert in
6f5670a4c3d8c079d4b676140ee69e5cc235d5a8 has been fixed in
382c505d9cfca8adaec47aea2da7bbcbc00fc05c now, so it should be safe
to reenable the pass for that target (and ELF).

In PR50227 it's also mentioned that the same pass seems to cause
problems on aarch64 on darwin, so leaving it disabled there for now.
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
Commit 61630814b1d0415953fd4d1a58427836487f356c by david.sherwood
[NFC] Use variable GEP index in vec_demanded_elts tests

I've changed a test in each of these files:

  Transforms/InstCombine/vec_demanded_elts.ll
  Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll

to use a variable GEP index instead of a constant value so that
we're testing the more general case.
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
Commit 892c56eabe250acaeb761eaddf783f47d95f7f4d by powerman1st
[clang][AVR] Redefine some types to be compatible with avr-gcc

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D100701
The file was modifiedclang/test/CodeGen/builtins.cpp
The file was modifiedclang/lib/Basic/Targets/AVR.cpp
The file was modifiedclang/test/Preprocessor/init.c
Commit 3fa6510f6ea0101c70592487074957bb1cde576c by peter.waller
[CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr

When a ptest is used to set flags from the output of rdffr, the ptest
can be eliminated, using a flags-setting rdffrs instead.

Additionally, check that nothing consumes flags between rdffr and ptest;
this case appears to have been missed previously.

* There is no unpredicated RDFFRS instruction.
* If substituting RDFFR_PP, require that the mask argument of the
  PTEST matches that of the RDFFR_PP.
* Move some precondition code up inside optimizePTestInstr, so that it
  covers the new code paths for RDFFR which return earlier.
  * Only consider RDFFR, PTEST in same basic block.
  * Check for other flag setting instructions between the two, abort if
    found.
  * Drop an old TODO comment about removing dead PTEST instructions.

RDFFR_P to follow in later patch.

Differential Revision: https://reviews.llvm.org/D101357
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was addedllvm/test/CodeGen/AArch64/sve-ptest-removal-rdffr.mir
Commit 4b00ffa767fc8a71c2eaf544cb6397f6db34eb6a by hgreving
[DAGCombiner] Add test exposing bug in DAG combine.

Adds a test in X86, exposing a bug in DAG combine eliminating stores that
are the same value but no the same address space.

Differential Revision: https://reviews.llvm.org/D102243
The file was addedllvm/test/CodeGen/X86/dagcombine-dead-store.ll
Commit 762ac725bf9775536dda5b3dda13574f14a8c2b9 by hgreving
[DAGCombiner] Fix DAG combine store elimination, different address space.

Fixes a bug in the DAG combiner that eliminates the stores because it missed
to inspect the address space of the pointers.

%v = load %ptr_as1
// no chain side effect
store %v, %ptr_as2

As well as

store %v, %ptr_as1
store %v, %ptr_as2

Fixes a test for above in X86.

Differential Revision: https://reviews.llvm.org/D102096
The file was modifiedllvm/test/CodeGen/X86/dagcombine-dead-store.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 8d37411e48202b490c62ee3548df4b90f5974e12 by stefanp
Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics"

This reverts commit 6c80361b8474535852afb2f7201370fb5f410091.
Breaks PowerPC Big Endian buildbots.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
The file was modifiedllvm/test/CodeGen/Mips/atomic.ll
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-signext.ll
Commit 44e0e91db01abb9de1868f5acf3ff4f2648b8fc0 by craig.topper
[ValueTypes] Rename MVT::getVectorNumElements() to MVT::getVectorMinNumElements(). Fix some misuses of getVectorNumElements()

getVectorNumElements() returns a value for scalable vectors
without any warning so it is effectively getVectorMinNumElements().
By renaming it and making getVectorNumElements() forward to
it, we can insert a check for scalable vectors into getVectorNumElements()
similar to EVT. I didn't do that in this patch because there are still more
fixes needed, but I was able to temporarily do it and passed the RISCV
lit tests with these changes.

The changes to isPow2VectorType and getPow2VectorType are copied from EVT.

The change to TypeInfer::EnforceSameNumElts reduces the size of AArch64's isel table.
We're now considering SameNumElts to require the scalable property to match which
removes some unneeded type checks.

This was motivated by the bug I fixed yesterday in 80b9510806cf11c57f2dd87191d3989fc45defa8

Reviewed By: frasercrmck, sdesmalen

Differential Revision: https://reviews.llvm.org/D102262
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
Commit 98575708da9544ccab8939fece9c3d638a32f09f by Yaxun.Liu
[CUDA][HIP] Fix device template variables

Currently clang does not emit device template variables
instantiated only in host functions, however, nvcc is
able to do that:

https://godbolt.org/z/fneEfferY

This patch fixes this issue by refactoring and extending
the existing mechanism for emitting static device
var ODR-used by host only. Basically clang records
device variables ODR-used by host code and force
them to be emitted in device compilation. The existing
mechanism makes sure these device variables ODR-used
by host code are added to llvm.compiler-used, therefore
they are guaranteed not to be deleted.

It also fixes non-ODR-use of static device variable by host code
causing static device variable to be emitted and registered,
which should not.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D102237
The file was modifiedclang/test/CodeGenCUDA/device-stub.cu
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/CodeGenCUDA/static-device-var-no-rdc.cu
The file was modifiedclang/lib/CodeGen/CGCUDANV.cpp
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was modifiedclang/test/CodeGenCUDA/static-device-var-rdc.cu
The file was modifiedclang/test/CodeGenCUDA/host-used-device-var.cu
Commit 1336c5ae2fea48bcb54a5050a01b59333fd502aa by rupprecht
[llvm-cov][test] Add test coverage for "gcov" implying "llvm-cov gcov" compatibility.

Much like other LLVM binary utilities, `llvm-cov` has a symlink compatibility feature where it runs in `gcov` compatibility mode if the binary name ends in `gcov`. This is identical to invoking `llvm-cov gcov ...`.

Differential Revision: https://reviews.llvm.org/D102299
The file was addedllvm/test/tools/llvm-cov/tool-name.test
Commit 58d18dde5cca3417e3d52670775c95d2f6fe9d05 by anastasia.stulova
[OpenCL] Remove pragma requirement from Arm dot extension.

This removed the pointless need for extension pragma since
it doesn't disable anything properly and it doesn't need to
enable anything that is not possible to disable.

The change doesn't break existing kernels since it allows to
compile more cases i.e. without pragma statements but the
pragma continues to be accepted.

Differential Revision: https://reviews.llvm.org/D100985
The file was modifiedclang/test/CodeGenOpenCL/arm-integer-dot-product.cl
The file was modifiedclang/lib/Headers/opencl-c.h
The file was modifiedclang/test/SemaOpenCL/arm-integer-dot-product.cl
Commit 6110b667b0537104ee139a5c6efc726f902db4de by clementval
[mlir][openacc] Conversion of data operand to LLVM IR dialect

Add a conversion pass to convert higher-level type before translation.
This conversion extract meangingful information and pack it into a struct that
the translation (D101504) will be able to understand.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D102170
The file was addedmlir/lib/Conversion/OpenACCToLLVM/OpenACCToLLVM.cpp
The file was addedmlir/test/Conversion/OpenACCToLLVM/convert-standalone-data-to-llvmir.mlir
The file was modifiedmlir/include/mlir/Conversion/Passes.h
The file was modifiedmlir/include/mlir/Conversion/Passes.td
The file was addedmlir/lib/Conversion/OpenACCToLLVM/CMakeLists.txt
The file was modifiedmlir/lib/Conversion/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
The file was modifiedmlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
The file was addedmlir/include/mlir/Conversion/OpenACCToLLVM/ConvertOpenACCToLLVM.h
Commit c5ec00e62b0e7b91eb07e25441c7ed38227f5bf3 by fraser
[TargetLowering] Improve legalization of scalable vector types

This patch extends the vector type-conversion and legalization capabilities of
scalable vector types.

Firstly, `vscale x 1` types now behave more like the corresponding `vscale x
2+` types. This enables the integer promotion legalization of extended scalable
types, such as the promotion of `<vscale x 1 x i5>` to `<vscale x 1 x i8>`.

These `vscale x 1` types are also now better handled by
`getVectorTypeBreakdown`, where what looks like older handling for 1-element
fixed-length vector types was spuriously updated to include scalable types.

Widening of scalable types is now better supported, by using `INSERT_SUBVECTOR`
to insert the smaller scalable vector "value" type into the wider scalable
vector "part" type. This allows AArch64 to pass and return `vscale x 1` types
by value by widening.

There are still cases where we are unable to legalize `vscale x 1` types, such
as where expansion would require splitting the vector in two.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D102073
The file was addedllvm/test/CodeGen/AArch64/sve-widen-scalable-vectortype.ll
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
Commit 778562ada39f5353b735c4ac204eddedb072a94b by llvm-dev
[X86][AVX] Add v4i64 shift-by-32 tests

AVX1 could perform this as a v8f32 shuffle instead of splitting - based off PR46621
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-ashr-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-shl-256.ll
Commit 7bff9bdd34d53a660f80eb1cdc9da885fd2702e1 by llvm-dev
[X86][AVX] combineConcatVectorOps - add ConcatSubOperand helper. NFCI.

Pull out repeated code to create a concat_vectors of the same operand from all subvecs.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 47a11a97d0c28e6b1235907780c998f141497e0a by paul.robinson
Fix grammar in README.md
The file was modifiedREADME.md
Commit 5885f1a4cb0bec91ea106e4f300c860c8d061d56 by baptiste.saleil
[AMDGPU] Disable the SIFormMemoryClauses pass at -O1

This patch disables the SIFormMemoryClauses pass at -O1. This pass has a
significant impact on compilation time, so we only want it to be enabled
starting from -O2.

Differential Revision: https://reviews.llvm.org/D101939
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Commit cf4610d27bbb5c3a744374440e2fdf77caa12040 by wei.huang
[PowerPC] Fix definitions of CMPRB8, CMPEQB, CMPRB, SETB in PPCInstr64Bit.td and PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
Commit 33f908c42881fa02963f0c64f8be5088717664cc by fabian
[MLIR] Factor pass timing out into a dedicated timing manager

This factors out the pass timing code into a separate `TimingManager`
that can be plugged into the `PassManager` from the outside. Users are
able to provide their own implementation of this manager, and use it to
time additional code paths outside of the pass manager. Also allows for
multiple `PassManager`s to run and contribute to a single timing report.

More specifically, moves most of the existing infrastructure in
`Pass/PassTiming.cpp` into a new `Support/Timing.cpp` file and adds a
public interface in `Support/Timing.h`. The `PassTiming` instrumentation
becomes a wrapper around the new timing infrastructure which adapts the
instrumentation callbacks to the new timers.

Reviewed By: rriddle, lattner

Differential Revision: https://reviews.llvm.org/D100647
The file was modifiedmlir/docs/PassManagement.md
The file was modifiedmlir/include/mlir/Pass/Pass.h
The file was modifiedmlir/include/mlir/Pass/PassManager.h
The file was modifiedmlir/lib/Support/MlirOptMain.cpp
The file was modifiedmlir/lib/Pass/Pass.cpp
The file was modifiedmlir/lib/Support/CMakeLists.txt
The file was modifiedmlir/lib/Pass/PassTiming.cpp
The file was modifiedmlir/test/Pass/pipeline-parsing.mlir
The file was addedmlir/include/mlir/Support/Timing.h
The file was modifiedmlir/test/Pass/pass-timing.mlir
The file was modifiedmlir/lib/Pass/PassManagerOptions.cpp
The file was addedmlir/lib/Support/Timing.cpp
Commit 5389a05836e74e3acab6dbda7e80ea43e3bc6304 by malcolm.parsons
[docs] Fix documentation for bugprone-dangling-handle

string_view isn't experimental anymore.
This check has always handled both forms.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D102313
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/bugprone-dangling-handle.rst
Commit cbed6e5b2ff026e4d64de8f6ee19bc902b6e0e23 by Abhina.Sreeskantharajan
[SystemZ][z/OS] Fix warning caused by umask returning a signed integer type

On z/OS, umask() returns an int because mode_t is type int, however it is being compared to an unsigned int. This patch fixes the following warning we see when compiling Path.cpp.

```
comparison of integers of different signs: 'const int' and 'const unsigned int'
```

Reviewed By: muiez

Differential Revision: https://reviews.llvm.org/D102326
The file was modifiedllvm/unittests/Support/Path.cpp
Commit 9934571eab9c6b3be22c4c8857bd3f4280b77843 by jonathanchesterfield
[libomptarget][amdgpu][nfc] Expand errorcheck macros

[libomptarget][amdgpu][nfc] Expand errorcheck macros

These macros expand to continue, which is confusing, or exit,
which is incompatible with continuing execution on offloading fail.

Expanding the macros in place makes the code look untidy but the
control flow obvious and amenable to improving. In particular, exit
becomes easier to eliminate.

Reviewed By: pdhaliwal

Differential Revision: https://reviews.llvm.org/D102230
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/system.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/data.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/internal.h
Commit 93c8559baf551a7a30ab17654569ac5ac92986f4 by gkm
[lld-macho] Implement branch-range-extension thunks

Extend the range of calls beyond an architecture's limited branch range by first calling a thunk, which loads the far address into a scratch register (x16 on ARM64) and branches through it.

Other ports (COFF, ELF) use multiple passes with successively-refined guesses regarding the expansion of text-space imposed by thunk-space overhead. This MachO algorithm places thunks during MergedOutputSection::finalize() in a single pass using exact thunk-space overheads. Thunks are kept in a separate vector to avoid the overhead of inserting into the `inputs` vector of `MergedOutputSection`.

FIXME:
* arm64-stubs.s test is broken
* add thunk tests
* Handle thunks to DylibSymbol in MergedOutputSection::finalize()

Differential Revision: https://reviews.llvm.org/D100818
The file was modifiedlld/MachO/SyntheticSections.cpp
The file was modifiedlld/MachO/Target.h
The file was modifiedlld/MachO/Symbols.h
The file was addedlld/test/MachO/arm64-thunks.s
The file was modifiedlld/MachO/Arch/ARM64.cpp
The file was modifiedlld/MachO/Options.td
The file was modifiedlld/MachO/SyntheticSections.h
The file was modifiedlld/MachO/InputSection.h
The file was modifiedlld/MachO/Writer.cpp
The file was modifiedlld/MachO/Symbols.cpp
The file was addedlld/test/MachO/tools/generate-thunkable-program.py
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/MachO/InputSection.cpp
The file was modifiedlld/MachO/MergedOutputSection.cpp
The file was modifiedlld/MachO/MergedOutputSection.h
Commit dc8d16c03f4fcdc0dbfc2925621f6d0064bca31c by Amara Emerson
[AArch64][GlobalISel] Add MMOs to constant pool loads to allow LICM hoisting.

This caused performance regressions vs SDAG on SingleSource/Benchmarks/Adobe-C++
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-const-pool.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Commit ca5d0a7310bfb21730ac6dd735e06502e7e45099 by ajcbik
[mlir][sparse] keep runtime support library signature consistent

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D102285
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/conversion.mlir
Commit fb1d61b7257ccd5ba0c96bcea78d6516384ce5b6 by llvm-dev
[X86][AVX] Fold concat(ps*lq(x,32),ps*lq(y,32)) -> shuffle(concat(x,y),zero) (PR46621)

On AVX1 targets we can handle v4i64 logical shifts by 32 bits as a pair of v8f32 shuffles with zero.

I was hoping to put this in LowerScalarImmediateShift, but performing that early causes regressions where other instructions were respliting the subvectors.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vec_int_to_fp.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-shl-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-256.ll
Commit 5480ea6c84633b7a5548cfe48fc09c6b57cecfb9 by hanchung
Update static bound checker for Linalg to cover decreasing cases

The current static checker for linalg does not work on the decreasing
index cases well. So, this is to Update the current static bound checker
for linalg to cover decreasing index cases.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D102302
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
Commit 3bf1acab5b454ad7fb2074b34663108b53620695 by i
[CMake][ELF] Add -fno-semantic-interposition and -Bsymbolic-functions

llvm-dev message: https://lists.llvm.org/pipermail/llvm-dev/2021-May/150465.html

In an ELF shared object, a default visibility defined symbol is preemptible by default.
This creates some missed optimization opportunities. -fno-semantic-interposition can optimize -fPIC:

* in Clang: avoid GOT/PLT cost for variable access/function calls to external linkage definition in the same TU
* in GCC: enable interprocedural optimizations (including inlining) and avoid PLT

See https://gist.github.com/MaskRay/2d4dfcfc897341163f734afb59f689c6 for more information.

-Bsymbolic-functions is more aggressive than -fvisibility-inlines-hidden (present since 2012) as it applies
to all function definitions.  It can

* avoid PLT for cross-TU function calls && reduce dynamic symbol lookup
* reduce dynamic symbol lookup for taking function addresses and optimize out GOT/TOC on x86-64/ppc64

With both options, the libLLVM.so and libclang-cpp.so performance should
be closer to PIE binary linking against `libLLVM*.a` and `libclang*.a`

(In a -DLLVM_TARGETS_TO_BUILD=X86 build, the number of JUMP_SLOT decreases from 12716 to 1628, and the number of GLOB_DAT decreases from 1918 to 1313
The built clang with `-DLLVM_LINK_LLVM_DYLIB=on -DCLANG_LINK_CLANG_DYLIB=on` is significantly faster.
See the Linux kernel build result https://bugs.archlinux.org/task/70697
)

Some implication:

Interposing a subset of functions is no longer supported.
(This is fragile anyway and cannot really be supported. For Mach-O we don't use
`ld -interpose`, so interposition is not supported on Mach-O at all.)

Compiling a program which takes the address of any LLVM function with
`{gcc,clang} -fno-pic` and expects the address to equal to the address taken
from libLLVM.so or libclang-cpp.so is unsupported. I am fairly confident that
llvm-project shouldn't have different behaviors depending on such pointer
equality (as we've been using -fvisibility-inlines-hidden which applies to
inline functions for a long time), but if we accidentally do, users should be
aware that they should not make assumption on pointer equality in `-fno-pic`
mode.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D102090
The file was modifiedclang/tools/clang-shlib/CMakeLists.txt
The file was modifiedllvm/tools/llvm-shlib/CMakeLists.txt
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
Commit 0fe6649bc5b1824e87e418b2b18f61c1ed1025ce by i
[X86] Fix -Wunused-lambda-capture
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2d84195d60b0cb5ea43b18ab8f6770a84bf32da4 by lebedev.ri
[NFCI][clang][Codegen] CodeGenVTables::addVTableComponent(): use getGlobalDecl

It does the same thing.
Split off from https://reviews.llvm.org/D100388
The file was modifiedclang/lib/CodeGen/CGVTables.cpp
Commit 81f56a2eb3797eb5be61d65a8f7d7e19456e67d1 by lebedev.ri
[NFC][clang][Codegen] Split ThunkInfo into it's own header

Otherwise we'll have issues with forward definition of GlobalDecl.

Split off from https://reviews.llvm.org/D100388
The file was modifiedclang/include/clang/Basic/ABI.h
The file was modifiedclang/include/clang/AST/VTableBuilder.h
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was addedclang/include/clang/Basic/Thunk.h
Commit 113b807017847f7d9e79db724f09968b51459cf0 by clementval
[mlir][openacc] Add OpenACC translation to LLVM IR (enter_data op create/copyin)

This patch begins to translate acc.enter_data operation to call to tgt runtime call.
It currently only translate create/copyin operands of memref type. This acts as a basis to add support
for FIR types in the Flang/OpenACC support. It follows more or less a similar path than clang
with `omp target enter data map` directives.
This patch is taking a different approach than D100678 and perform a translation to LLVM IR
and make use of the OpenMPIRBuilder instead of doing a conversion to the LLVMIR dialect.

OpenACC support in Flang will rely on the current OpenMP runtime where 1:1 lowering can be
applied. Some extension will be added where features are not available yet.

Big part of this code will be shared for other standalone data operations in the OpenACC
dialect such as acc.exit_data and acc.update.

It is likely that parts of the lowering can also be shared later with the ops for
standalone data directives in the OpenMP dialect when they are introduced.

This is an initial translation and it probably needs more work.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D101504
The file was addedmlir/test/Target/LLVMIR/openacc-llvm.mlir
The file was modifiedmlir/lib/Target/LLVMIR/CMakeLists.txt
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
The file was addedmlir/lib/Target/LLVMIR/Dialect/OpenACC/CMakeLists.txt
The file was addedmlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp
The file was modifiedmlir/include/mlir/Target/LLVMIR/Dialect/All.h
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h
Commit 1470b8587f6fdc357163c2258747b77ae9ad6d7a by benny.kra
Remove AST inclusion from Basic include

That's a cyclic dependency. NFC.
The file was modifiedclang/include/clang/Basic/Thunk.h
Commit 7b57517507929a5d23fde4776aeb792ee0e9c293 by rob.suderman
[mlir][linalg] Fixed issue generating reassociation map with Rank-0 types

Rank-0 case causes a graph during linalg reshape operation.

Differential Revision: https://reviews.llvm.org/D102282
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
Commit 56f7e5a822b43578e086c40d063af2a2c0d214ee by smeenai
[cmake] Add support for multiple distributions

LLVM's build system contains support for configuring a distribution, but
it can often be useful to be able to configure multiple distributions
(e.g. if you want separate distributions for the tools and the
libraries). Add this support to the build system, along with
documentation and usage examples.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D89177
The file was modifiedclang/cmake/modules/CMakeLists.txt
The file was modifiedlld/cmake/modules/CMakeLists.txt
The file was modifiedlld/cmake/modules/AddLLD.cmake
The file was modifiedllvm/cmake/modules/LLVMConfig.cmake.in
The file was modifiedflang/cmake/modules/AddFlang.cmake
The file was modifiedflang/cmake/modules/CMakeLists.txt
The file was modifiedllvm/docs/BuildingADistribution.rst
The file was modifiedflang/cmake/modules/FlangConfig.cmake.in
The file was modifiedllvm/cmake/modules/LLVMDistributionSupport.cmake
The file was modifiedmlir/cmake/modules/MLIRConfig.cmake.in
The file was modifiedclang/cmake/modules/ClangConfig.cmake.in
The file was modifiedmlir/cmake/modules/CMakeLists.txt
The file was modifiedllvm/cmake/modules/AddLLVM.cmake
The file was modifiedclang/cmake/modules/AddClang.cmake
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedmlir/cmake/modules/AddMLIR.cmake
The file was modifiedlld/cmake/modules/LLDConfig.cmake.in
The file was modifiedllvm/cmake/modules/CMakeLists.txt
The file was addedclang/cmake/caches/MultiDistributionExample.cmake
Commit 1124ad2f5d47aa468a0d00b6d82853a6d4eda8d1 by stelios.ioannou
[LoopFlatten] Simplify loops so that the pass can operate on unsimplified loops.

The loop flattening pass requires loops to be in simplified form. If the
loops are not in simplified form, the pass cannot operate. This patch
simplifies all loops before flattening. As a result, all loops will be
simplified regardless of whether anything ends up being flattened.

This change was inspired by observing a certain loop that was not flatten
because the loops were not in simplified form. This loop is added as a
test to verify that it is now flattened.

Differential Revision: https://reviews.llvm.org/D102249

Change-Id: I45bcabe70fb99b0d89f0effafc82eb9e0585ec30
The file was modifiedllvm/lib/Transforms/Scalar/LoopFlatten.cpp
The file was addedllvm/test/Transforms/LoopFlatten/loop-flatten-simplify-cfg.ll
Commit 96c1fa2a041d352d2b6eb202f3c419323239514f by flo
[SCEV] Add loop-guard pessimizing test with step = 2.
The file was modifiedllvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
Commit ed9e1a7dcc2eceb4596a5f2ede7daabcb1fdf4ab by flo
[PhaseOrdering] Add test for missing vectorization with NewPM.
The file was addedllvm/test/Transforms/PhaseOrdering/AArch64/globals-aa-required-for-vectorization.ll
Commit 211761332e4381c37edd91be7c59fc048014ff4e by hokein.wu
[clang-tidy] Allow opt-in or out of some commonly occuring patterns in NarrowingConversionsCheck.

Within clang-tidy's NarrowingConversionsCheck.
* Allow opt-out of some common occurring patterns, such as:
  - Implicit casts between types of equivalent bit widths.
  - Implicit casts occurring from the return of a ::size() method.
  - Implicit casts on size_type and difference_type.
* Allow opt-in of errors within template instantiations.

This will help projects adopt these guidelines iteratively.
Developed in conjunction with Yitzhak Mandelbaum (ymandel).

Patch by Stephen Concannon!

Differential Revision: https://reviews.llvm.org/D99543
The file was modifiedclang-tools-extra/clang-tidy/cppcoreguidelines/NarrowingConversionsCheck.cpp
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-narrowing-conversions.rst
The file was modifiedclang-tools-extra/clang-tidy/cppcoreguidelines/NarrowingConversionsCheck.h
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-narrowing-conversions-intemplates-option.cpp
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-narrowing-conversions-ignoreconversionfromtypes-option.cpp
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-narrowing-conversions-equivalentbitwidth-option.cpp
Commit d8c227ba05d065046bdb8671f1df73dabaffa222 by thakis
Revert "Produce warning for performing pointer arithmetic on a null pointer."

This reverts commit dfc1e31d49fe1380c9bab43373995df5fed15e6d.
See discussion on https://reviews.llvm.org/D98798
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/Sema/pointer-addition.c
The file was removedclang/test/Sema/pointer-addition.cpp
Commit 99d63ccff04b672694f8a2b3eed024b873dc163d by v.g.vassilev
Add type information to integral template argument if required.

Non-comprehensive list of cases:
* Dumping template arguments;
* Corresponding parameter contains a deduced type;
* Template arguments are for a DeclRefExpr that hadMultipleCandidates()

Type information is added in the form of prefixes (u8, u, U, L),
suffixes (U, L, UL, LL, ULL) or explicit casts to printed integral template
argument, if MSVC codeview mode is disabled.

Differential revision: https://reviews.llvm.org/D77598
The file was modifiedclang/test/SemaTemplate/temp_arg_enum_printing.cpp
The file was modifiedclang/unittests/Tooling/RecursiveASTVisitorTests/TemplateArgumentLocTraverser.cpp
The file was modifiedclang/test/CXX/lex/lex.literal/lex.ext/p12.cpp
The file was modifiedclang/test/SemaCXX/matrix-type-operators.cpp
The file was modifiedclang/test/SemaTemplate/address_space-dependent.cpp
The file was modifiedclang/include/clang/AST/StmtDataCollectors.td
The file was modifiedclang-tools-extra/clangd/Hover.cpp
The file was addedclang/test/CXX/lex/lex.literal/lex.ext/p13.cpp
The file was modifiedclang/lib/AST/DeclPrinter.cpp
The file was modifiedclang/lib/AST/TypePrinter.cpp
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
The file was modifiedclang/test/SemaCXX/cxx11-ast-print.cpp
The file was modifiedclang/lib/AST/ASTTypeTraits.cpp
The file was modifiedclang/lib/AST/TemplateBase.cpp
The file was modifiedclang/test/SemaTemplate/temp_arg_nontype.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/test/Analysis/eval-predefined-exprs.cpp
The file was modifiedclang/include/clang/AST/DeclTemplate.h
The file was modifiedclang/include/clang/AST/TemplateBase.h
The file was modifiedclang/test/SemaCXX/matrix-type-builtins.cpp
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp
The file was modifiedclang/lib/AST/Expr.cpp
The file was modifiedclang/test/SemaTemplate/matrix-type.cpp
The file was modifiedclang/include/clang/AST/Expr.h
The file was modifiedclang/lib/AST/DeclTemplate.cpp
The file was modifiedclang/lib/AST/StmtPrinter.cpp
The file was addedclang/test/CodeGenCXX/debug-info-codeview-template-literal.cpp
The file was modifiedclang/test/SemaCXX/builtin-align-cxx.cpp
The file was addedclang/test/SemaTemplate/default-arguments-ast-print.cpp
The file was modifiedclang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp
The file was modifiedclang/lib/Analysis/PathDiagnostic.cpp
The file was addedclang/test/CodeGenCXX/debug-info-codeview-template-type.cpp
The file was addedclang/test/SemaCXX/cxx1z-ast-print.cpp
The file was modifiedclang/lib/AST/NestedNameSpecifier.cpp
The file was modifiedclang/test/SemaTemplate/delegating-constructors.cpp
The file was modifiedclang/tools/libclang/CIndex.cpp
The file was addedclang/test/CXX/lex/lex.literal/lex.ext/p14.cpp
Commit a8f7dee1dffbf8c18acbcc7b1f6d659bf808798e by nikita.ppv
[InstCombine] Support one-hot merge for logical and/or

If a logical and/or is used, we need to be careful not to propagate
a potential poison value from the RHS by inserting a freeze
instruction. Otherwise it works the same way as bitwise and/or.

This is intended to address the regression reported at
https://reviews.llvm.org/D101191#2751002.

Differential Revision: https://reviews.llvm.org/D102279
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
The file was modifiedllvm/test/Transforms/InstCombine/onehot_merge.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit c273f5ef7d3f5ac05f67ec899e25830cd9543e56 by koraq
[libc++][nfc] remove duplicated __to_unsigned.

Both `<type_traits>` and `<charconv>` implemented this function with
different names and a slightly different behavior. This removes the
version in `<charconv>` and improves the version in `<typetraits>`.

- The code can be used again in C++11.
-  The original claimed C++14 support, but `[[nodiscard]]` is not
   available in  C++14.
- Adds `_LIBCPP_INLINE_VISIBILITY`.

Reviewed By: zoecarver, #libc, Quuxplusone

Differential Revision: https://reviews.llvm.org/D102332
The file was modifiedlibcxx/include/__ranges/size.h
The file was modifiedlibcxx/include/type_traits
The file was modifiedlibcxx/include/charconv
Commit 77997f28d5954fa2417806586f2c5c9d1a0ffeef by smeenai
[cmake] Fix typo in function name

Not sure how my local testing didn't trigger this path. Should fix
https://lab.llvm.org/buildbot/#/builders/132/builds/5494
The file was modifiedllvm/cmake/modules/AddLLVM.cmake
Commit 6bd3d8a17cef9108a338ada9b3dbed201bf9c158 by martin
[libcxx] [test] Fix fs.op.last_write_time for Windows

Don't use stat and lstat on Windows; lstat is missing, stat only provides
the modification times with second granularity (and does the wrong thing
regarding symlinks). Instead do a minimal reimplementation using the
native windows APIs.

Differential Revision: https://reviews.llvm.org/D101731
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.last_write_time/last_write_time.pass.cpp
The file was modifiedlibcxx/test/support/filesystem_test_helper.h
Commit 7e0768329ca347e37c7bdb0da16b51cb3e7b7d8b by martin
[LLD] [COFF] Fix including the personality function for DWARF EH when linking with --gc-sections

Since c579a5b1d92a9bc2046d00ee2d427832e0f5ddec we don't traverse
.eh_frame when doing GC. But the exception handling personality
function needs to be included, and is only referenced from within
.eh_frame.

Differential Revision: https://reviews.llvm.org/D102138
The file was modifiedlld/COFF/Driver.cpp
The file was addedlld/test/COFF/gc-dwarf-eh.s
Commit a8053399cde847dfce88d7d1fa2a2099f3a58c40 by i
[ELF][AVR] Add explicit relocation types to getRelExpr
The file was modifiedlld/ELF/Arch/AVR.cpp
Commit 4b014352308f7244b86438fff7c61c632934a1ff by rob.suderman
[mlir][tosa] Remove tosa.identityn operator

Removes the identityn operator from TOSA MLIR definition.
Removes TosaToLinAlg mappings

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D102329
The file was modifiedmlir/test/Dialect/Tosa/ops.mlir
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
The file was modifiedmlir/docs/Dialects/TOSA.md
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
Commit 08ba9ce1ef7214623d4104e72d817c73644a0884 by erich.keane
Suppress Deferred Diagnostics in discarded statements.

It doesn't really make sense to emit language specific diagnostics
in a discarded statement, and suppressing these diagnostics results in a
programming pattern that many users will feel is quite useful.

Basically, this makes sure we only emit errors from the 'true' side of a
'constexpr if'.

It does this by making the ExprEvaluatorBase type have an opt-in option
as to whether it should visit discarded cases.

Differential Revision: https://reviews.llvm.org/D102251
The file was modifiedclang/include/clang/AST/Stmt.h
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/test/SemaCUDA/deferred-diags.cu
The file was modifiedclang/include/clang/AST/EvaluatedExprVisitor.h
The file was modifiedclang/lib/AST/Stmt.cpp
Commit 30b7dfafdb620420ad3498aae01130bc7e2fb9cd by smeenai
[flang] Fix standalone builds

Flang's CMake modules directory was being added to the CMake module path
twice, and AddFlang was being included after the first addition. Remove
the unnecessary first addition and move the AddFlang include down to the
second one. This way, it occurs after LLVM's CMake modules have been
included for a standalone build, so it can make use of those modules.
The file was modifiedflang/CMakeLists.txt
Commit b3911cdfc89f3b560fc00048d6f99280268fa63c by riddleriver
[mlir-lsp-server] Add support for sending diagnostics to the client

This allows for diagnostics emitted during parsing/verification to be surfaced to the user by the language client, as opposed to just being emitted to the logs like they are now.

Differential Revision: https://reviews.llvm.org/D102293
The file was modifiedmlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp
The file was modifiedmlir/lib/Tools/mlir-lsp-server/LSPServer.cpp
The file was modifiedmlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
The file was modifiedmlir/lib/Tools/mlir-lsp-server/MLIRServer.h
The file was modifiedmlir/lib/Tools/mlir-lsp-server/lsp/Transport.h
The file was modifiedmlir/lib/Parser/AsmParserState.cpp
The file was modifiedmlir/lib/Tools/mlir-lsp-server/lsp/Protocol.cpp
The file was modifiedmlir/lib/Tools/mlir-lsp-server/lsp/Transport.cpp
The file was addedmlir/test/mlir-lsp-server/diagnostics.test
The file was modifiedmlir/include/mlir/Parser/AsmParserState.h
Commit 29ac15ab380b6d9853d4cdc9c220107e90375cb9 by riddleriver
[mlir-lsp-server][NFC] Add newline between Protocol JSON serialization methods and class definitions.
The file was modifiedmlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
Commit 5bb7e81c64bd29edd1c9ebadd4e4717919def0bf by richard
Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope.

This implements the direction proposed in
https://github.com/itanium-cxx-abi/cxx-abi/pull/126.

Differential Revision: https://reviews.llvm.org/D101968
The file was modifiedclang/test/CodeGenCXX/clang-abi-compat.cpp
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.h
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was modifiedclang/test/CodeGenCXX/mangle-lambda-explicit-template-params.cpp
Commit 9c345407b4999e62e51667927f531b891363569b by craig.topper
[RISCV] Remove RISCVII:VSEW enum. Make encodeVYPE operate directly on SEW.

The VSEW encoding isn't a useful value to pass around. It's better
to use SEW or log2(SEW) directly. The only real ugliness is that
the vsetvli IR intrinsics use the VSEW encoding, but it's easy
enough to decode that when the intrinsic is processed.
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
Commit ba38b72ec2833bf8c54829a0fd7a8c968e6260d4 by aheejin
[WebAssembly] Allow Wasm EH with Emscripten SjLj

We explicitly made it error out in D101403, out of a good intention that
the error message will make people less confusing. Turns out, we weren't
failing all cases of wasm EH + SjLj; only a few cases were failing and
our client was able to get around by fixing source code, but now we made
it fail for all cases, even the cases that previously succeeded fail,
which we didn't intend. This reverts that change.

Reviewed By: tlively

Differential Revision: https://reviews.llvm.org/D102364
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-ehsjlj-options.ll
Commit 3041b16f7322a0392810e4a14b13cacac1929ad8 by sbc
[WebAssembly] Add TLS data segment flag: WASM_SEG_FLAG_TLS

Previously the linker was relying solely on the name of the segment
to imply TLS.

Differential Revision: https://reviews.llvm.org/D102202
The file was modifiedllvm/lib/MC/MCParser/WasmAsmParser.cpp
The file was modifiedllvm/lib/MC/MCSectionWasm.cpp
The file was modifiedllvm/lib/ObjectYAML/WasmYAML.cpp
The file was modifiedlld/wasm/Writer.cpp
The file was modifiedllvm/test/MC/WebAssembly/tls.s
The file was modifiedlld/wasm/InputChunks.h
The file was modifiedllvm/test/CodeGen/WebAssembly/target-features-tls.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/tls-local-exec.ll
The file was modifiedlld/test/wasm/tls.s
The file was modifiedllvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/include/llvm/BinaryFormat/Wasm.h
Commit cd01430ff13b5441bc71e6dc3c4e688052f7be82 by sbc
[lld][WebAssembly] Allow data symbols to extend past end of segment

This fixes a bug with string merging with string symbols that contain
NULLs, as is the case in the `merge-string.s` test.

The bug only showed when we run with `--relocatable` and then try read
the resulting object back in.  In this case we would end up with string
symbols that extend past the end of the segment in which they live.

The problem comes from the fact that sections which are flagged as
string mergable assume that all strings are NULL terminated.  The
merging algorithm will drop trailing chars that follow a NULL since they
are essentially unreachable.  However, the "size" attribute (in the
symbol table) of such a truncated symbol is not updated resulting a
symbol size that can overlap the end of the segment.

I verified that this can happen in ELF too given the right conditions
and the its harmless enough.  In practice Strings that contain embedded
null should not be part of a mergable section.

Differential Revision: https://reviews.llvm.org/D102281
The file was addedllvm/test/Object/wasm-bad-data-symbol.yaml
The file was modifiedllvm/lib/Object/WasmObjectFile.cpp
The file was modifiedlld/test/wasm/merge-string.s
Commit fb3a00c327df78eaa534e53ac6f07112e0585121 by riddleriver
[mlir] Fix ssa values naming bug

Address comments in https://reviews.llvm.org/D102226 to fix the bug + style violations

Differential Revision: https://reviews.llvm.org/D102368
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
Commit e5bdacba2e185034979fddd8bff2695bfcdd3056 by gclayton
Optimize GSymCreator::finalize.

The algorithm removing duplicates from the Funcs list used to have
amortized quadratic time complexity because it was potentially
removing each entry using std::vector::erase individually. This
patch is now using a erase-remove idiom with an adapted
removeIfBinary algorithm.

Probably this was made under the assumption that these removals are
rare, but there are cases where the case of duplicate entries is
occurring frequently. In these cases, the actual runtime was very
poor, taking hours to process a single binary of around 1 GiB size
including debug info. Another factor contributing to that is the
frequent output of the warning, which is now removed.

It seems this is particularly an issue with GCC-compiled binaries,
rather than clang-built binaries.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D102219
The file was modifiedllvm/lib/DebugInfo/GSYM/GsymCreator.cpp
Commit e7d26aceca071d67168062b2f7784c56234b0cb3 by Justin Bogner
Change the context instruction for computeKnownBits in LoadStoreVectorizer pass

This change enables cases for which the index value for the first
load/store instruction in a pair could be a function argument. This
allows using llvm.assume to provide known bits information in such
cases.

Patch by Viacheslav Nikolaev. Thanks!

Differential Revision: https://reviews.llvm.org/D101680
The file was modifiedllvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
Commit b7911e80d6926f9280ceb23d4e86e25c29370904 by ravishankarm
[mlir][Linalg] Add interface methods to get lhs and rhs of contraction

Differential Revision: https://reviews.llvm.org/D102301
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
Commit bd00106d1e77e4de769ce0d143c97a076f25c92b by Stanislav.Mekhanoshin
[AMDGPU] Refactor shouldExpandAtomicRMWInIR(). NFC.

This is logic simplification for better readability.

Differential Revision: https://reviews.llvm.org/D102371
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 58d12332a4730226d0a640136f06f3bd0861f1a5 by ajcbik
[mlir][sparse][capi][python] add sparse tensor passes

First set of "boilerplate" to get sparse tensor
passes available through CAPI and Python.

Reviewed By: stellaraccident

Differential Revision: https://reviews.llvm.org/D102362
The file was modifiedmlir/lib/CAPI/Dialect/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/Transforms/CMakeLists.txt
The file was modifiedmlir/include/mlir-c/Dialect/SparseTensor.h
The file was addedmlir/lib/CAPI/Dialect/SparseTensorPasses.cpp
The file was modifiedmlir/python/mlir/dialects/sparse_tensor.py
The file was modifiedmlir/lib/Bindings/Python/CMakeLists.txt
The file was addedmlir/lib/Bindings/Python/SparseTensorPasses.cpp
The file was addedmlir/test/python/dialects/sparse_tensor/passes.py
Commit 46c17429bc86dc5ccddb5512b77bd1ede39c9ccd by cjdb
[libcxx] modifies `_CmpUnspecifiedParam` ignore types outside its domain

D85051's honeypot solution was a bit too aggressive swallowed up the
comparison types, which made comparing objects of different ordering
types ambiguous.

Depends on D101707.

Differential Revision: https://reviews.llvm.org/D101708
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.weakord/weakord.pass.cpp
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.categories.pre/zero_type.verify.cpp
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.strongord/strongord.pass.cpp
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.partialord/partialord.pass.cpp
The file was modifiedlibcxx/include/compare
Commit 6732a5328cf03872d53827d3e0e283fcf16b551a by peter
scudo: Require fault address to be in bounds for UAF.

The bounds check that we previously had here was suitable for secondary
allocations but not for UAF on primary allocations, where it is likely
to result in false positives. Fix it by using a different bounds check
for UAF that requires the fault address to be in bounds.

Differential Revision: https://reviews.llvm.org/D102376
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
Commit 10c779d2065f7e216660f1687244269afcee13b1 by Pushpinder.Singh
[AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S

Previously clang would print a binary blob into the bundled file
for amdgcn. With this patch, it will instead print textual IR as
expected.

Reviewed By: JonChesterfield, ronlieb

Differential Revision: https://reviews.llvm.org/D102065

Change-Id: I10c0127ab7357787769fdf9a2edd4b3071e790a1
The file was modifiedclang/test/Driver/amdgpu-openmp-toolchain.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit 4c88cfb1dc79227be78f8dade966934384914e5e by richard
Add test for substitutability of variable templates in closure type
mangling.
The file was modifiedclang/test/CodeGenCXX/mangle-lambdas.cpp
Commit e0acfed7ed5173b437868f75fc394084487e390a by richard
Clean up handling of constrained parameters in lambdas.

No functionality change intended.
The file was modifiedclang/lib/AST/TypePrinter.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/lib/Sema/TreeTransform.h
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp
Commit 2f9d8b08ea658b612065cbf7d4b0fbd7f28bb36a by richard
PR50306: When instantiating a generic lambda with a constrained 'auto',
properly track that it has constraints.

Previously an instantiation of a constrained generic lambda would behave
as if unconstrained because we incorrectly cached a "has no constraints"
value that we computed before the constraints from 'auto' parameters
were attached.
The file was modifiedclang/test/SemaTemplate/concepts.cpp
The file was modifiedclang/lib/AST/DeclTemplate.cpp
Commit e1aa528d3aaf5fcf9c50d1e34b39dbde1e63801d by richard
Handle unexpanded packs appearing in type-constraints.

For a type-constraint in a lambda signature, this makes the lambda
contain an unexpanded pack; for requirements in a requires-expressions
it makes the requires-expression contain an unexpanded pack; otherwise
it's invalid.
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
The file was modifiedclang/test/SemaTemplate/concepts.cpp
The file was modifiedclang/lib/AST/DeclTemplate.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/include/clang/AST/RecursiveASTVisitor.h
The file was modifiedclang/lib/AST/Type.cpp
The file was modifiedclang/include/clang/AST/DeclTemplate.h
The file was modifiedclang/include/clang/Sema/Sema.h
Commit 017d7a9e14245e549999c5e3b8bd7398fcf79410 by Adrian Prantl
Rename human-readable name for DW_LANG_Mips_Assembler

The Mips in DW_LANG_Mips_Assembler is a vendor name not an
architecture name and in lack of a proper generic DW_LANG_assembler,
some assemblers emit DWARF using this tag. Due to a warning I recently
introduced users will now be greeted with

  This version of LLDB has no plugin for the mipsassem language. Inspection of frame variables will be limited.

By renaming this to just "Assembler" this error message will make more sense.

Differential Revision: https://reviews.llvm.org/D101406

rdar://77214764
The file was modifiedlldb/source/Target/Language.cpp
The file was modifiedlldb/source/Target/Process.cpp
The file was modifiedlldb/test/Shell/Process/UnsupportedLanguage.test
Commit ce6cc87ce9e96eaa5e5ef0c1f5dc07b41381996d by Yaxun.Liu
[clang] Minor fix for MarkVarDeclODRUsed

Merge two if as follow up of https://reviews.llvm.org/D102270
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit c9087788f7e41285445729127dd07ff7f82e3fc0 by springerm
[mlir] Fix masked vector transfer ops with broadcasts

Broadcast dimensions of a vector transfer op have no corresponding dimension in the mask vector. E.g., a 2-D TransferReadOp, where one dimension is a broadcast, can have a 1-D `mask` attribute.

This commit also adds a few additional transfer op integration tests for various combinations of broadcasts, masking, dim transposes, etc.

Differential Revision: https://reviews.llvm.org/D101745
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.td
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-2d.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir
The file was modifiedmlir/lib/Interfaces/VectorInterfaces.cpp
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.h
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
Commit 6555e53ab0f2bca3dc30f5ab3a2d6872d50b6ff8 by springerm
Revert "[mlir] Fix masked vector transfer ops with broadcasts"

This reverts commit c9087788f7e41285445729127dd07ff7f82e3fc0.

Accidentally pushed old version of the commit.
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-2d.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.td
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.h
The file was modifiedmlir/lib/Interfaces/VectorInterfaces.cpp
Commit a0ca4c46ca35957a38a6023fa84afda2fc9ba0ec by czhengsz
[Debug-Info] add -gstrict-dwarf support in backend

Reviewed By: dblaikie, probinson

Differential Revision: https://reviews.llvm.org/D100826
The file was modifiedllvm/lib/CodeGen/CommandFlags.cpp
The file was addedllvm/test/DebugInfo/PowerPC/strict-dwarf.ll
The file was modifiedllvm/include/llvm/Target/TargetOptions.h
The file was modifiedllvm/include/llvm/CodeGen/CommandFlags.h
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
Commit c52cbe63e42fff8c1a95921effd35d7bb59301d3 by springerm
[mlir] Fix masked vector transfer ops with broadcasts

Broadcast dimensions of a vector transfer op have no corresponding dimension in the mask vector. E.g., a 2-D TransferReadOp, where one dimension is a broadcast, can have a 1-D `mask` attribute.

This commit also adds a few additional transfer op integration tests for various combinations of broadcasts, masking, dim transposes, etc.

Differential Revision: https://reviews.llvm.org/D101745
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.td
The file was modifiedmlir/test/Dialect/Vector/ops.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.h
The file was modifiedmlir/lib/Interfaces/VectorInterfaces.cpp
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-2d.mlir
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir
Commit 864adf399e58a6bfd823136fc2cbcfe9dff5b4a8 by springerm
[mlir] Allow empty position in vector.insert and vector.extract

Such ops are no-ops and are folded to their respective `source`/`vector` operand.

Differential Revision: https://reviews.llvm.org/D101879
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/test/Dialect/Vector/ops.mlir
Commit 9b77be5583d2da03f2ccd7319d33a2daedf8b1b3 by springerm
[mlir] Unrolled progressive-vector-to-scf.

Instead of an SCF for loop, these pattern generate fully unrolled loops with no temporary buffer allocations.

Differential Revision: https://reviews.llvm.org/D101981
The file was modifiedmlir/lib/Interfaces/VectorInterfaces.cpp
The file was modifiedmlir/test/lib/Transforms/TestVectorTransforms.cpp
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir
The file was addedmlir/test/Conversion/VectorToSCF/unrolled-vector-to-loops.mlir
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
The file was modifiedmlir/include/mlir/Conversion/VectorToSCF/ProgressiveVectorToSCF.h
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-2d.mlir
Commit 2a51e9ff2e06d5d7096f826014916b4cc02269fc by springerm
[mlir] Support memref layout maps in vector transfer ops

Differential Revision: https://reviews.llvm.org/D102042
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
Commit 44a4000181e1a25027e87f2ae4e71cb876a7a275 by v.g.vassilev
[clang-repl] Land initial infrastructure for incremental parsing

In http://lists.llvm.org/pipermail/llvm-dev/2020-July/143257.html we have
mentioned our plans to make some of the incremental compilation facilities
available in llvm mainline.

This patch proposes a minimal version of a repl, clang-repl, which enables
interpreter-like interaction for C++. For instance:

./bin/clang-repl
clang-repl> int i = 42;
clang-repl> extern "C" int printf(const char*,...);
clang-repl> auto r1 = printf("i=%d\n", i);
i=42
clang-repl> quit

The patch allows very limited functionality, for example, it crashes on invalid
C++. The design of the proposed patch follows closely the design of cling. The
idea is to gather feedback and gradually evolve both clang-repl and cling to
what the community agrees upon.

The IncrementalParser class is responsible for driving the clang parser and
codegen and allows the compiler infrastructure to process more than one input.
Every input adds to the “ever-growing” translation unit. That model is enabled
by an IncrementalAction which prevents teardown when HandleTranslationUnit.

The IncrementalExecutor class hides some of the underlying implementation
details of the concrete JIT infrastructure. It exposes the minimal set of
functionality required by our incremental compiler/interpreter.

The Transaction class keeps track of the AST and the LLVM IR for each
incremental input. That tracking information will be later used to implement
error recovery.

The Interpreter class orchestrates the IncrementalParser and the
IncrementalExecutor to model interpreter-like behavior. It provides the public
API which can be used (in future) when using the interpreter library.

Differential revision: https://reviews.llvm.org/D96033
The file was modifiedclang/lib/Frontend/FrontendAction.cpp
The file was addedclang/unittests/Interpreter/IncrementalProcessingTest.cpp
The file was addedclang/lib/Interpreter/IncrementalParser.cpp
The file was addedclang/lib/Interpreter/IncrementalExecutor.cpp
The file was removedclang/unittests/CodeGen/IncrementalProcessingTest.cpp
The file was modifiedclang/lib/CodeGen/CodeGenAction.cpp
The file was addedclang/lib/Interpreter/IncrementalExecutor.h
The file was addedclang/lib/Interpreter/CMakeLists.txt
The file was addedclang/include/clang/Interpreter/Transaction.h
The file was modifiedclang/test/CMakeLists.txt
The file was addedclang/include/clang/Interpreter/Interpreter.h
The file was modifiedclang/include/clang/Frontend/FrontendAction.h
The file was addedclang/lib/Interpreter/IncrementalParser.h
The file was modifiedclang/test/lit.cfg.py
The file was addedclang/lib/Interpreter/Interpreter.cpp
The file was modifiedclang/tools/CMakeLists.txt
The file was addedclang/unittests/Interpreter/InterpreterTest.cpp
The file was addedclang/tools/clang-repl/ClangRepl.cpp
The file was addedclang/test/Interpreter/sanity.c
The file was addedclang/test/Interpreter/execute.cpp
The file was addedclang/tools/clang-repl/CMakeLists.txt
The file was modifiedclang/include/clang/CodeGen/CodeGenAction.h
The file was modifiedclang/lib/CMakeLists.txt
The file was addedclang/unittests/Interpreter/CMakeLists.txt
The file was modifiedclang/unittests/CodeGen/CMakeLists.txt
The file was modifiedclang/unittests/CMakeLists.txt
Commit 00a0595b253f22f5138eb0ceaf892dbe8e670453 by anton.a.afanasyev
[SLP][Test] Fix and precommit tests for D98714
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/bswap.ll
Commit cd9090031c83ee857f82c3344b6efd97185c928e by anton.a.afanasyev
[SLP][Test] Fix and precommit tests for D98714
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
Commit ab2c499d3a2ed3d3e13d96e456c57fb35a114b31 by anton.a.afanasyev
[SLP] Add insertelement instructions to vectorizable tree

Add new type of tree node for `InsertElementInst` chain forming vector.
These instructions could be either removed, or replaced by shuffles during
vectorization and we can add this node to cost model, so naturally estimating
their cost, getting rid of `CompensateCost` tricks and reducing further work
for InstCombine. This fixes PR40522 and PR35732 in a natural way. Also this
patch is the first step towards revectorization of partially vectorization
(to fix PR42022 completely). After adding inserts to tree the next step is
to add vector instructions there (for instance, to merge `store <2 x float>`
and `store <2 x float>` to `store <4 x float>`).

Fixes PR40522 and PR35732.

Differential Revision: https://reviews.llvm.org/D98714
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sign-extend-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/zext-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
The file was modifiedllvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/hadd-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/load-merge.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/bswap.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/insertelement-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/ARM/extract-insert.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-fp-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/value-bug-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/arith-fp.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr31599.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR35865.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/ARM/extract-insert-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/value-bug.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sext-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/external_user_jumbled_load.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/gather-root.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/hsub.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/hsub-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/vectorize-free-extracts-inserts.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/arith-fp-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr31599-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr44067.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/transpose-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/vectorizable-functions.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR35865-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/hadd.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/insertelement.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/zext.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/long_chains.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr40522.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sign-extend.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sext.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/external_user_jumbled_load-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/transpose.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/crash_extract_subvector_cost.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/resched.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-fp.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/phi.ll
Commit 6e5b8f489a27901de4b9dfa152da02dbca13ec31 by yedeng.yd
[Coroutines] Enable printing coroutine frame when dbg info is available

Summary: This patch tries to build debug info for coroutine frame in the
middle end. Although the coroutine frame is constructed and maintained by
the compiler and the programmer shouldn't care about the coroutine frame
by the design of C++20 coroutine,
a lot of programmers told me that they want to see the layout of the
coroutine frame strongly. Although C++ is designed as an abstract layer
so that the programmers shouldn't care about the actual memory in bits,
many experienced C++ programmers  are familiar with assembler and
debugger to see the memory layout in fact, After I was been told they
want to see the coroutine frame about 3 times, I think it is an actual
and desired demand.

However, the debug information is constructed in the front end and
coroutine frame is constructed in the middle end. This is a natural and
clear gap. So I could only try to construct the debug information in the
middle end after coroutine frame constructed. It is unusual, but we are
in consensus that the approch is the best one.

One hard part is we need construct the name for variables since there
isn't a map from llvm variables to DIVar. Then here is the strategy this
patch uses:
- The name `__resume_fn `, `__destroy_fn` and `__coro_index ` are
  constructed by the patch.
- Then the name `__promise` comes from the dbg.variable of corresponding
  dbg.declare of PromiseAlloca, which shows highest priority to
construct the debug information for the member of coroutine frame.
- Then if the member is struct, we would try to get the name of the llvm
  struct directly. Then replace ':' and '.' with '_' to make it
printable for debugger.
- If the member is a basic type like integer or double, we would try to
  emit the corresponding name.
- Then if the member is a Pointer Type, we would add `Ptr` after
  corresponding pointee type.
- Otherwise, we would name it with 'UnknownType'.

Reviewered by: lxfind, aprantl, rjmcall, dblaikie

Differential Revision: https://reviews.llvm.org/D99179
The file was modifiedllvm/test/Transforms/Coroutines/coro-inline.ll
The file was addedllvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroInternal.h
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
Commit f6907152db3d70606817ffe28274c6a90b331bbc by v.g.vassilev
Revert "[clang-repl] Land initial infrastructure for incremental parsing"

This reverts commit 44a4000181e1a25027e87f2ae4e71cb876a7a275.

We are seeing build failures due to missing dependency to libSupport and
CMake Error at tools/clang/tools/clang-repl/cmake_install.cmake
file INSTALL cannot find
The file was removedclang/tools/clang-repl/ClangRepl.cpp
The file was modifiedclang/lib/CMakeLists.txt
The file was modifiedclang/tools/CMakeLists.txt
The file was removedclang/include/clang/Interpreter/Interpreter.h
The file was modifiedclang/test/CMakeLists.txt
The file was removedclang/unittests/Interpreter/IncrementalProcessingTest.cpp
The file was removedclang/tools/clang-repl/CMakeLists.txt
The file was modifiedclang/unittests/CMakeLists.txt
The file was removedclang/test/Interpreter/execute.cpp
The file was modifiedclang/include/clang/CodeGen/CodeGenAction.h
The file was modifiedclang/lib/CodeGen/CodeGenAction.cpp
The file was removedclang/include/clang/Interpreter/Transaction.h
The file was modifiedclang/test/lit.cfg.py
The file was removedclang/unittests/Interpreter/InterpreterTest.cpp
The file was modifiedclang/unittests/CodeGen/CMakeLists.txt
The file was modifiedclang/lib/Frontend/FrontendAction.cpp
The file was removedclang/lib/Interpreter/IncrementalExecutor.cpp
The file was removedclang/test/Interpreter/sanity.c
The file was removedclang/lib/Interpreter/Interpreter.cpp
The file was addedclang/unittests/CodeGen/IncrementalProcessingTest.cpp
The file was removedclang/lib/Interpreter/IncrementalParser.h
The file was removedclang/lib/Interpreter/CMakeLists.txt
The file was modifiedclang/include/clang/Frontend/FrontendAction.h
The file was removedclang/unittests/Interpreter/CMakeLists.txt
The file was removedclang/lib/Interpreter/IncrementalExecutor.h
The file was removedclang/lib/Interpreter/IncrementalParser.cpp
Commit 3f8aafd7902722cc2039c7ef3d6747f8d49f81a6 by rob.suderman
[mlir][tosa] Fix tosa.cast semantics to perform rounding/clipping

Rounding to integers requires rounding (for floating points) and clipping
to the min/max values of the destination range. Added this behavior and
updated tests appropriately.

Reviewed By: sjarus, silvas

Differential Revision: https://reviews.llvm.org/D102375
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp

Summary

  1. [Zorg][OpenMP] Add CUDA offloading worker. (details)
Commit e4aa8a2773fe76c427a91229f021ab067eafc8e7 by llvm-zorg
[Zorg][OpenMP] Add CUDA offloading worker.

This worker tests OpenMP offloading for the x86_64 and NVIDIA GPU. In
addition to check-openmp, it runs the SOLLVE Validation & Verification Suite
via the LLVM test-suite External builder. The builder is configured to
only warn if the SOLLVE suite fails, as it also tests features that
have not been implemented in Clang yet.

CUDA is intentionally not installed in a default location (/opt/cuda) to
resemble setups often found in computing clusters with multiple versions
of CUDA to choose from.

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D101268
The file was modifiedzorg/buildbot/builders/OpenMPBuilder.py
The file was modifiedbuildbot/osuosl/master/config/workers.py
The file was modifiedbuildbot/osuosl/master/config/builders.py