Commit
2cf0e52b8548716d8534470db1ce4bbb3571eea9
by david.green[ARM] Add patterns for vmulh
Now that vmulh can be selected, this adds the MVE patterns to make it legal and generate instructions.
Differential Revision: https://reviews.llvm.org/D88011
|
 | llvm/test/CodeGen/Thumb2/mve-vmulh.ll |
 | llvm/lib/Target/ARM/ARMInstrMVE.td |
 | llvm/lib/Target/ARM/ARMISelLowering.cpp |
 | llvm/unittests/Target/ARM/MachineInstrTest.cpp |
Commit
bf809cd165f4ea1b8ef6aabc8e41e29747b4d2c7
by esme.yi[NFC][object] Change the input parameter of the method isDebugSection.
Summary: This is a NFC patch to change the input parameter of the method SectionRef::isDebugSection(), by replacing the StringRef SectionName with DataRefImpl Sec. This allows us to determine if a section is debug type in more ways than just by section name.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D102601
|
 | llvm/include/llvm/Object/MachO.h |
 | llvm/lib/Object/MachOObjectFile.cpp |
 | llvm/include/llvm/Object/ObjectFile.h |
 | llvm/include/llvm/Object/COFF.h |
 | llvm/include/llvm/Object/ELFObjectFile.h |
 | llvm/tools/llvm-dwarfdump/SectionSizes.cpp |
 | llvm/lib/Object/ObjectFile.cpp |
 | llvm/lib/Object/COFFObjectFile.cpp |
Commit
b99f892b025b553680c7e5dbcf15ab7301e3fa57
by akuegel[mlir] Fold complex.re(complex.create) and complex.im(complex.create)
This extends the folding we already have. A test needs to be adjusted.
Differential Revision: https://reviews.llvm.org/D103141
|
 | mlir/test/Dialect/Complex/canonicalize.mlir |
 | mlir/test/Conversion/ComplexToLLVM/convert-to-llvm.mlir |
 | mlir/lib/Dialect/Complex/IR/ComplexOps.cpp |
Commit
9c766f4090d19e3e2f56e87164177f8c3eba4b96
by david.sherwood[InstCombine] Fold extractelement + vector GEP with one use
We sometimes see code like this:
Case 1: %gep = getelementptr i32, i32* %a, <2 x i64> %splat %ext = extractelement <2 x i32*> %gep, i32 0
or this:
Case 2: %gep = getelementptr i32, <4 x i32*> %a, i64 1 %ext = extractelement <4 x i32*> %gep, i32 0
where there is only one use of the GEP. In such cases it makes sense to fold the two together such that we create a scalar GEP:
Case 1: %ext = extractelement <2 x i64> %splat, i32 0 %gep = getelementptr i32, i32* %a, i64 %ext
Case 2: %ext = extractelement <2 x i32*> %a, i32 0 %gep = getelementptr i32, i32* %ext, i64 1
This may create further folding opportunities as a result, i.e. the extract of a splat vector can be completely eliminated. Also, even for the general case where the vector operand is not a splat it seems beneficial to create a scalar GEP and extract the scalar element from the operand. Therefore, in this patch I've assumed that a scalar GEP is always preferrable to a vector GEP and have added code to unconditionally fold the extract + GEP.
I haven't added folds for the case when we have both a vector of pointers and a vector of indices, since this would require generating an additional extractelement operation.
Tests have been added here:
Transforms/InstCombine/gep-vector-indices.ll
Differential Revision: https://reviews.llvm.org/D101900
|
 | llvm/test/Transforms/InstCombine/vec_demanded_elts.ll |
 | llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp |
 | llvm/test/Transforms/InstCombine/gep-vector-indices.ll |
 | llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll |
 | llvm/test/Transforms/InstCombine/vec_gep_scalar_arg-inseltpoison.ll |
 | llvm/test/Transforms/InstCombine/vec_gep_scalar_arg.ll |
Commit
cb65419b1ac05c3020dd05b64db183712235d2ff
by akuegel[mlir] Simplify folding code (NFC)
|
 | mlir/lib/Dialect/Complex/IR/ComplexOps.cpp |
Commit
91e0cb6598f458c79707bc3481f0e70b1dd731d4
by ivan.butygin[mlir] LocalAliasAnalysis: Assume allocation scope to function scope if cannot determine better
It helps when checking aliasing between AllocOp result and function arguments.
Differential Revision: https://reviews.llvm.org/D102557
|
 | mlir/lib/Analysis/AliasAnalysis/LocalAliasAnalysis.cpp |
 | mlir/test/Analysis/test-alias-analysis.mlir |
Commit
a3b3f7e631981bd861d5fe5e20f33b11a0dac978
by bjorn.a.pettersson[HIP] Adjust check in hip-include-path.hip test case
The changes in commit 722c39fef5ab6 caused the test case to fail when building with -DLLVM_LIBDIR_SUFFIX=64. This patch makes the checks a bit more relaxed to support libdir suffixes again.
Also adjusting the regular expressions to avoid mathes including double quotes.
|
 | clang/test/Driver/hip-include-path.hip |
Commit
70d8365e33366d44fd61c149f96e8228e05bebc0
by david.sherwoodFix warning introduced by 9c766f4090d19e3e2f56e87164177f8c3eba4b96
|
 | llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp |
Commit
8c86161a0be2266dd9232e9f1c13b625c2ff0db2
by lebedev.ri[NFC][X86] clang-format X86TTIImpl::getInterleavedMemoryOpCostAVX2()
I plan to make changes to it, and undoing formatting each time is not going to be fun.
|
 | llvm/lib/Target/X86/X86TargetTransformInfo.cpp |
Commit
794fb5482efc4af5434e23efb5b0a99b4a386eed
by mkazantsev[Test] Add test on unrolling to make sure it won't fail
Initially it failed an assertion with "Do actual DCE in LoopUnroll (try 2)" which was later reverted. Make sure that when this patch is returned, the test works fine.
|
 | llvm/test/Transforms/LoopUnroll/nonlatchcondbr.ll |
Commit
66978466baefbaac3234df07851ec6d94f99914c
by llvm-dev[X86][Atom] Fix vector variable shift resource/throughputs
Match whats documented in the Intel AOM - the non-immediate variants of the PSLL*/PSRA*/PSRL* shift instructions requires BOTH ports - this was being incorrectly modelled as EITHER port.
Now that we can use in-order models in llvm-mca, the atom model is a good "worst case scenario" analysis for x86.
|
 | llvm/test/tools/llvm-mca/X86/Atom/resources-sse2.s |
 | llvm/lib/Target/X86/X86ScheduleAtom.td |
 | llvm/test/tools/llvm-mca/X86/Atom/resources-mmx.s |
Commit
942e01de896a5e1fa76d367747e8fc0126038038
by llvm-dev[CostModel][X86] Remove old testshift* tests
The vector shift cost tests are better covered (more cpu/sse levels) by the vshift-*-*cost files, and we're trying to avoid codegen tests in here as it makes it harder to maintain the test files.
|
 | llvm/test/Analysis/CostModel/X86/testshiftshl.ll |
 | llvm/test/Analysis/CostModel/X86/testshiftashr.ll |
 | llvm/test/Analysis/CostModel/X86/testshiftlshr.ll |
Commit
8c5ac18d7165fa0963583e0249faa3b272239fee
by Tim NorthoverAArch64: support post-indexed stores to bfloat types.
|
 | llvm/test/CodeGen/AArch64/bf16.ll |
 | llvm/lib/Target/AArch64/AArch64InstrInfo.td |
Commit
7ee863b8ebfad9249450dd283087042354a02939
by mkazantsev[Test] Add simplified versions of tests for loop deletion that don't need context
|
 | llvm/test/Transforms/LoopDeletion/eval_first_iteration.ll |
Commit
7e27e4273d093064da8ecbf868795f8ae68bc775
by fraser[RISCV] Pre-commit fixed-length mask vselect tests
These are default-expanded but later unrolled due to RISC-V's vector boolean content policy. A patch to improve this codegen will follow shortly.
|
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll |
Commit
7386ad4e9e26df93876ae309920e4f7e72288bae
by Mirko.BrkusaninRevert "[AMDGPU][GlobalISel] Stop foldInsertEltToCmpSelect from changing reg banks"
This reverts commit 18c5444702893fd63b0a99ec7133dd714284f9d2.
|
 | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll |
Commit
9601849984a79eae176a9b114d7707c651097523
by Mirko.Brkusanin[AMDGPU][GlobalISel] Stop foldInsertEltToCmpSelect from changing reg banks
This function can change regbank for registers which already have a selected bank. Depending on the instruction where these registers were used it can cause instruction selection to fail.
Differential Revision: https://reviews.llvm.org/D98515
|
 | llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll |
 | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll |
 | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir |
Commit
6b0fe3c63b4619a67b45853b7bd47ecac75c4f31
by kerry.mclaughlin[NFC] Add CHECK lines for unordered FP reductions
An additional RUN line has been added to both strict-fadd.ll & scalable-strict-fadd.ll to ensure the correct behaviour of these tests where `-enable-strict-reductions` is false.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D103015
|
 | llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll |
 | llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll |
Commit
7648b6978e5539bcb43b3ca24a5a53e9c6a52c1e
by Pushpinder.Singh[AMDGPU][Libomptarget] Move Kernel/Symbol info tables to RTLDeviceInfoTy
Two globals KernelInfoTable & SymbolInfoTable are moved into RTLDeviceInfoTy class. This builds on the top of D102691. [2/2]
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D102692
|
 | openmp/libomptarget/plugins/amdgpu/src/rtl.cpp |
 | openmp/libomptarget/plugins/amdgpu/impl/atmi_interop_hsa.cpp |
 | openmp/libomptarget/plugins/amdgpu/impl/atmi_interop_hsa.h |
 | openmp/libomptarget/plugins/amdgpu/impl/system.cpp |
 | openmp/libomptarget/plugins/amdgpu/impl/internal.h |
Commit
2a41d702be478e3975f49bffec0672c991225786
by flo[SCEV] Add tests with signed predicates for applyLoopGuards.
|
 | llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll |
Commit
21aec4fdc5de213a1009bc684adff988c290c6b3
by llvm-dev[X86][SLM] Fix vector PSHUFB + variable shift resource/throughputs
Match whats documented in the Intel AOM (+Agner) - PSHUFB xmm is really slow, and mmx/xmm vector shifts are half rate.
Noticed while working to get the cost tables to more closely match llvm-mca analysis, in this case for shifts and truncations.
|
 | llvm/test/tools/llvm-mca/X86/SLM/resources-mmx.s |
 | llvm/test/tools/llvm-mca/X86/SLM/resources-sse2.s |
 | llvm/test/tools/llvm-mca/X86/SLM/resources-ssse3.s |
 | llvm/lib/Target/X86/X86ScheduleSLM.td |
Commit
76e47d4887f456878c0e2f20ebfae36267006cd7
by Raphael Isemann[lldb][NFC] Use C++ versions of the deprecated C standard library headers
The C headers are deprecated so as requested in D102845, this is replacing them all with their (not deprecated) C++ equivalent.
Reviewed By: shafik
Differential Revision: https://reviews.llvm.org/D103084
|
 | lldb/source/Core/Disassembler.cpp |
 | lldb/source/Core/PluginManager.cpp |
 | lldb/include/lldb/Core/Section.h |
 | lldb/include/lldb/Core/ValueObjectConstResultImpl.h |
 | lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp |
 | lldb/include/lldb/API/SBExecutionContext.h |
 | lldb/include/lldb/Core/StreamFile.h |
 | lldb/source/Host/posix/HostProcessPosix.cpp |
 | lldb/source/Utility/DataExtractor.cpp |
 | lldb/tools/debugserver/source/MacOSX/i386/MachRegisterStatesI386.h |
 | lldb/include/lldb/Core/ValueObjectVariable.h |
 | lldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.cpp |
 | lldb/source/Utility/StructuredData.cpp |
 | lldb/source/Breakpoint/BreakpointID.cpp |
 | lldb/source/Host/common/ProcessLaunchInfo.cpp |
 | lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOSXDYLD.cpp |
 | lldb/include/lldb/Core/ValueObjectList.h |
 | lldb/include/lldb/Utility/ConstString.h |
 | lldb/tools/debugserver/source/RNBSocket.cpp |
 | lldb/include/lldb/Utility/StringExtractorGDBRemote.h |
 | lldb/tools/lldb-vscode/lldb-vscode.cpp |
 | lldb/source/Core/AddressResolverFileLine.cpp |
 | lldb/include/lldb/Host/Time.h |
 | lldb/include/lldb/Core/ValueObjectConstResult.h |
 | lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h |
 | lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp |
 | lldb/tools/lldb-server/lldb-gdbserver.cpp |
 | lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM.cpp |
 | lldb/source/Utility/FileSpec.cpp |
 | lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp |
 | lldb/include/lldb/Core/FormatEntity.h |
 | lldb/source/Core/ValueObjectMemory.cpp |
 | lldb/tools/debugserver/source/MacOSX/MachThread.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.cpp |
 | lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionVariable.h |
 | lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp |
 | lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.h |
 | lldb/source/Plugins/Platform/NetBSD/PlatformNetBSD.cpp |
 | lldb/source/Core/Module.cpp |
 | lldb/include/lldb/Core/ValueObject.h |
 | lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerPlatform.cpp |
 | lldb/include/lldb/Host/StringConvert.h |
 | lldb/source/Host/posix/HostInfoPosix.cpp |
 | lldb/include/lldb/Core/MappedHash.h |
 | lldb/source/Core/Opcode.cpp |
 | lldb/include/lldb/API/SBProcess.h |
 | lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.cpp |
 | lldb/include/lldb/API/SBSourceManager.h |
 | lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_s390x.cpp |
 | lldb/include/lldb/Core/AddressResolver.h |
 | lldb/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp |
 | lldb/source/Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h |
 | lldb/include/lldb/Utility/DataEncoder.h |
 | lldb/source/Core/ValueObjectChild.cpp |
 | lldb/include/lldb/Utility/Status.h |
 | lldb/source/Plugins/SymbolFile/DWARF/DWARFDefines.h |
 | lldb/tools/debugserver/source/DNBBreakpoint.cpp |
 | lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp |
 | lldb/tools/debugserver/source/MacOSX/MachVMRegion.cpp |
 | lldb/source/Plugins/SymbolVendor/wasm/SymbolVendorWasm.cpp |
 | lldb/source/Utility/ReproducerInstrumentation.cpp |
 | lldb/include/lldb/Core/Communication.h |
 | lldb/source/Expression/UserExpression.cpp |
 | lldb/include/lldb/Host/FileSystem.h |
 | lldb/tools/debugserver/source/DNBTimer.h |
 | lldb/source/Host/macosx/objcxx/Host.mm |
 | lldb/source/Utility/Event.cpp |
 | lldb/source/API/SBLineEntry.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterContextDarwin_x86_64.cpp |
 | lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp |
 | lldb/include/lldb/Core/FileLineResolver.h |
 | lldb/include/lldb/Utility/Listener.h |
 | lldb/tools/debugserver/source/JSON.cpp |
 | lldb/source/Plugins/StructuredData/DarwinLog/StructuredDataDarwinLog.cpp |
 | lldb/include/lldb/Utility/StringList.h |
 | lldb/include/lldb/Core/UserSettingsController.h |
 | lldb/tools/debugserver/source/MacOSX/x86_64/MachRegisterStatesX86_64.h |
 | lldb/include/lldb/Host/File.h |
 | lldb/source/Host/linux/HostInfoLinux.cpp |
 | lldb/source/API/SBError.cpp |
 | lldb/source/Utility/StringExtractor.cpp |
 | lldb/include/lldb/Core/FileSpecList.h |
 | lldb/include/lldb/Core/ValueObjectConstResultChild.h |
 | lldb/source/Host/posix/ProcessLauncherPosixFork.cpp |
 | lldb/include/lldb/Core/ValueObjectSyntheticFilter.h |
 | lldb/source/Plugins/Process/Linux/NativeThreadLinux.cpp |
 | lldb/source/Core/Value.cpp |
 | lldb/source/Utility/DataBufferLLVM.cpp |
 | lldb/include/lldb/Host/ProcessRunLock.h |
 | lldb/source/Core/ValueObject.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterInfos_mips.h |
 | lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp |
 | lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp |
 | lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp |
 | lldb/include/lldb/Symbol/LocateSymbolFile.h |
 | lldb/source/Core/Address.cpp |
 | lldb/source/Interpreter/CommandObject.cpp |
 | lldb/include/lldb/Breakpoint/StoppointHitCounter.h |
 | lldb/source/Utility/SelectHelper.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterContextDarwin_i386.cpp |
 | lldb/source/Host/linux/Host.cpp |
 | lldb/tools/driver/Platform.cpp |
 | lldb/source/Core/DynamicLoader.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64le.h |
 | lldb/include/lldb/Core/Opcode.h |
 | lldb/source/Plugins/Process/Utility/RegisterInfos_mips64.h |
 | lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp |
 | lldb/include/lldb/Utility/StringExtractor.h |
 | lldb/source/Plugins/ExpressionParser/Clang/ASTStructExtractor.cpp |
 | lldb/source/Plugins/ExpressionParser/Clang/ASTResultSynthesizer.cpp |
 | lldb/source/Utility/StringLexer.cpp |
 | lldb/include/lldb/Core/Disassembler.h |
 | lldb/tools/driver/Platform.h |
 | lldb/source/Core/IOHandler.cpp |
 | lldb/tools/lldb-server/lldb-server.cpp |
 | lldb/source/Plugins/Process/Linux/SingleStepCheck.cpp |
 | lldb/source/Plugins/Platform/OpenBSD/PlatformOpenBSD.cpp |
 | lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h |
 | lldb/source/Core/FileSpecList.cpp |
 | lldb/source/Plugins/Platform/Android/AdbClient.cpp |
 | lldb/include/lldb/Utility/Stream.h |
 | lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp |
 | lldb/include/lldb/Utility/Connection.h |
 | lldb/include/lldb/Utility/FileSpec.h |
 | lldb/source/Interpreter/ScriptInterpreter.cpp |
 | lldb/source/Plugins/DynamicLoader/Darwin-Kernel/DynamicLoaderDarwinKernel.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.cpp |
 | lldb/source/Utility/DataEncoder.cpp |
 | lldb/source/Host/common/FileSystem.cpp |
 | lldb/tools/lldb-vscode/JSONUtils.h |
 | lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp |
 | lldb/source/Utility/RegisterValue.cpp |
 | lldb/tools/lldb-vscode/VSCode.cpp |
 | lldb/source/Plugins/Language/ObjC/CoreMedia.cpp |
 | lldb/source/Plugins/Process/POSIX/CrashReason.h |
 | lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp |
 | lldb/source/Utility/VMRange.cpp |
 | lldb/source/Core/ValueObjectRegister.cpp |
 | lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp |
 | lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfoEntry.cpp |
 | lldb/tools/debugserver/source/libdebugserver.cpp |
 | lldb/tools/debugserver/source/DNBRegisterInfo.cpp |
 | lldb/include/lldb/Utility/StreamTee.h |
 | lldb/include/lldb/Host/HostInfoBase.h |
 | lldb/include/lldb/Host/FileCache.h |
 | lldb/source/Core/Section.cpp |
 | lldb/include/lldb/Core/ValueObjectChild.h |
 | lldb/tools/debugserver/source/DNBDefs.h |
 | lldb/tools/debugserver/source/SysSignal.cpp |
 | lldb/include/lldb/API/SBThread.h |
 | lldb/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp |
 | lldb/source/Host/freebsd/Host.cpp |
 | lldb/source/Host/freebsd/HostInfoFreeBSD.cpp |
 | lldb/tools/debugserver/source/PseudoTerminal.cpp |
 | lldb/tools/debugserver/source/DNB.cpp |
 | lldb/source/Core/ValueObjectVariable.cpp |
 | lldb/source/Symbol/UnwindTable.cpp |
 | lldb/source/API/SBFileSpec.cpp |
 | lldb/tools/debugserver/source/JSON.h |
 | lldb/include/lldb/Core/Value.h |
 | lldb/include/lldb/Utility/IOObject.h |
 | lldb/source/Host/windows/Windows.cpp |
 | lldb/include/lldb/Core/StreamAsynchronousIO.h |
 | lldb/include/lldb/Core/AddressRange.h |
 | lldb/source/Utility/VASprintf.cpp |
 | lldb/include/lldb/Utility/StreamCallback.h |
 | lldb/source/Plugins/Process/Utility/RegisterInfos_s390x.h |
 | lldb/tools/debugserver/source/DNBError.h |
 | lldb/source/Core/StreamFile.cpp |
 | lldb/tools/debugserver/source/MacOSX/MachThreadList.cpp |
 | lldb/include/lldb/Utility/Event.h |
 | lldb/source/Expression/DWARFExpression.cpp |
 | lldb/include/lldb/API/SBDebugger.h |
 | lldb/source/Host/common/MainLoop.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64le.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterInfos_powerpc.h |
 | lldb/source/Host/posix/ConnectionFileDescriptorPosix.cpp |
 | lldb/include/lldb/Core/ValueObjectConstResultCast.h |
 | lldb/include/lldb/Core/EmulateInstruction.h |
 | lldb/source/Host/common/Terminal.cpp |
 | lldb/source/Host/windows/Host.cpp |
 | lldb/source/Host/posix/DomainSocket.cpp |
 | lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.cpp |
 | lldb/include/lldb/API/SBCommandReturnObject.h |
 | lldb/source/Core/AddressRange.cpp |
 | lldb/source/Core/Mangled.cpp |
 | lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp |
 | lldb/tools/debugserver/source/RNBRemote.cpp |
 | lldb/source/Host/openbsd/HostInfoOpenBSD.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp |
 | lldb/include/lldb/Utility/DataBuffer.h |
 | lldb/include/lldb/Host/windows/PosixApi.h |
 | lldb/include/lldb/DataFormatters/TypeSynthetic.h |
 | lldb/include/lldb/Core/ValueObjectMemory.h |
 | lldb/include/lldb/Utility/VMRange.h |
 | lldb/include/lldb/Core/StreamBuffer.h |
 | lldb/include/lldb/Utility/DataExtractor.h |
 | lldb/include/lldb/lldb-types.h |
 | lldb/include/lldb/Core/ValueObjectRegister.h |
 | lldb/source/Core/Debugger.cpp |
 | lldb/source/Host/common/File.cpp |
 | lldb/include/lldb/Utility/Endian.h |
 | lldb/source/Target/ThreadCollection.cpp |
 | lldb/source/Symbol/Type.cpp |
 | lldb/include/lldb/Target/Process.h |
 | lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp |
 | lldb/include/lldb/Core/Mangled.h |
 | lldb/include/lldb/Core/Address.h |
 | lldb/source/Target/ThreadList.cpp |
 | lldb/tools/debugserver/source/DNBArch.cpp |
 | lldb/include/lldb/Utility/StreamString.h |
 | lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp |
 | lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServer.cpp |
 | lldb/source/Plugins/Process/MacOSX-Kernel/CommunicationKDP.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_powerpc.cpp |
 | lldb/include/lldb/Core/PluginManager.h |
 | lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64.h |
 | lldb/source/API/SBProcess.cpp |
 | lldb/include/lldb/Utility/Timer.h |
 | lldb/tools/debugserver/source/PThreadEvent.h |
 | lldb/source/Interpreter/CommandInterpreter.cpp |
 | lldb/source/Utility/ConstString.cpp |
 | lldb/source/Utility/Log.cpp |
 | lldb/source/Host/common/PseudoTerminal.cpp |
 | lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp |
 | lldb/tools/debugserver/source/DNBRegisterInfo.h |
 | lldb/source/Core/DumpDataExtractor.cpp |
 | lldb/source/Core/ValueObjectDynamicValue.cpp |
 | lldb/source/Host/netbsd/HostNetBSD.cpp |
 | lldb/source/Core/SourceManager.cpp |
 | lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp |
 | lldb/include/lldb/API/SBThreadPlan.h |
 | lldb/tools/debugserver/source/PThreadMutex.h |
 | lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h |
 | lldb/tools/debugserver/source/DNBDataRef.h |
 | lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp |
 | lldb/include/lldb/Host/Host.h |
 | lldb/source/Host/macosx/cfcpp/CFCReleaser.h |
 | lldb/source/Utility/Stream.cpp |
 | lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp |
 | lldb/include/lldb/API/SBStream.h |
 | lldb/include/lldb/Utility/UUID.h |
 | lldb/tools/debugserver/source/DNBLog.h |
 | lldb/source/API/SBDeclaration.cpp |
 | lldb/source/Host/common/StringConvert.cpp |
 | lldb/include/lldb/Core/ModuleList.h |
 | lldb/include/lldb/Core/AddressResolverFileLine.h |
 | lldb/include/lldb/Core/ValueObjectDynamicValue.h |
 | lldb/source/Host/common/Host.cpp |
 | lldb/tools/debugserver/source/MacOSX/arm64/DNBArchImplARM64.cpp |
 | lldb/source/Utility/GDBRemote.cpp |
 | lldb/tools/lldb-server/lldb-platform.cpp |
 | lldb/tools/debugserver/source/PThreadEvent.cpp |
 | lldb/tools/debugserver/source/StdStringExtractor.cpp |
 | lldb/source/Host/common/GetOptInc.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h |
 | lldb/source/Utility/UserID.cpp |
 | lldb/tools/driver/Driver.cpp |
 | lldb/source/Plugins/SymbolVendor/ELF/SymbolVendorELF.cpp |
 | lldb/source/Utility/Logging.cpp |
 | lldb/source/Utility/TildeExpressionResolver.cpp |
 | lldb/include/lldb/Core/Module.h |
 | lldb/source/Host/common/Socket.cpp |
 | lldb/include/lldb/Core/DumpDataExtractor.h |
 | lldb/include/lldb/Core/ValueObjectCast.h |
 | lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.h |
 | lldb/source/Plugins/InstrumentationRuntime/UBSan/InstrumentationRuntimeUBSan.cpp |
 | lldb/source/Interpreter/CommandHistory.cpp |
 | lldb/source/Utility/UUID.cpp |
 | lldb/include/lldb/Utility/DataBufferLLVM.h |
 | lldb/tools/lldb-vscode/VSCode.h |
 | lldb/source/Utility/StringExtractorGDBRemote.cpp |
 | lldb/source/Host/android/LibcGlue.cpp |
 | lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm |
 | lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp |
 | lldb/tools/debugserver/source/MacOSX/MachException.cpp |
 | lldb/source/Breakpoint/BreakpointSite.cpp |
 | lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp |
 | lldb/source/Utility/StringList.cpp |
 | lldb/include/lldb/Utility/Predicate.h |
 | lldb/source/Core/Communication.cpp |
 | lldb/tools/debugserver/source/DNBLog.cpp |
 | lldb/source/API/SBQueue.cpp |
 | lldb/include/lldb/Core/IOHandler.h |
 | lldb/source/Host/posix/HostThreadPosix.cpp |
 | lldb/include/lldb/Core/SearchFilter.h |
 | lldb/source/API/SBFileSpecList.cpp |
 | lldb/source/Target/ModuleCache.cpp |
 | lldb/source/Host/common/SocketAddress.cpp |
 | lldb/source/Utility/Broadcaster.cpp |
 | lldb/source/Host/posix/PipePosix.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.cpp |
 | lldb/source/Utility/Timer.cpp |
 | lldb/include/lldb/Core/dwarf.h |
 | lldb/tools/debugserver/source/StdStringExtractor.h |
 | lldb/include/lldb/API/SBInstruction.h |
 | lldb/source/Plugins/ExpressionParser/Clang/ClangUserExpression.cpp |
 | lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.cpp |
 | lldb/tools/debugserver/source/DNBDataRef.cpp |
 | lldb/include/lldb/API/SBInstructionList.h |
 | lldb/tools/debugserver/source/TTYState.h |
 | lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp |
 | lldb/source/DataFormatters/StringPrinter.cpp |
 | lldb/tools/darwin-debug/darwin-debug.cpp |
 | lldb/source/Core/SearchFilter.cpp |
 | lldb/include/lldb/API/SBEvent.h |
 | lldb/source/Utility/UriParser.cpp |
 | lldb/source/Utility/Status.cpp |
 | lldb/tools/debugserver/source/MacOSX/arm/DNBArchImpl.cpp |
 | lldb/tools/debugserver/source/DNBArch.h |
 | lldb/include/lldb/Core/Debugger.h |
 | lldb/include/lldb/Host/SocketAddress.h |
 | lldb/source/Host/openbsd/Host.cpp |
 | lldb/tools/debugserver/source/debugserver.cpp |
 | lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp |
 | lldb/include/lldb/Core/SourceManager.h |
 | lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationReplayServer.cpp |
 | lldb/source/Plugins/SymbolFile/DWARF/DWARFFormValue.cpp |
 | lldb/include/lldb/Target/DynamicLoader.h |
 | lldb/source/Core/IOHandlerCursesGUI.cpp |
 | lldb/source/Expression/UtilityFunction.cpp |
 | lldb/include/lldb/Utility/GDBRemote.h |
 | lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp |
 | lldb/include/lldb/DataFormatters/TypeSummary.h |
 | lldb/source/Core/FormatEntity.cpp |
 | lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp |
 | lldb/source/Core/EmulateInstruction.cpp |
 | lldb/source/Host/common/Editline.cpp |
 | lldb/source/Host/netbsd/HostInfoNetBSD.cpp |
Commit
cc8661ac4a20fbbf654187c8072b226b2700d708
by Pushpinder.Singh[AMDGPU][Libomptarget] Delete g_atmi_initialized
This patch drops g_atmi_initialized and inlines the Initialize & Finalize methods from Runtime class.
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D102847
|
 | openmp/libomptarget/plugins/amdgpu/impl/system.cpp |
 | openmp/libomptarget/plugins/amdgpu/impl/atmi_interop_hsa.cpp |
Commit
a2d6ef58765301fa95776cd17033a0974a487bf4
by Pushpinder.Singh[AMDGPU][Libomptarget] Inline atmi_init/atmi_finalize
After D102847, these functions can be inlined.
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D103075
|
 | openmp/libomptarget/plugins/amdgpu/src/rtl.cpp |
 | openmp/libomptarget/plugins/amdgpu/impl/atmi_runtime.h |
 | openmp/libomptarget/plugins/amdgpu/impl/rt.h |
 | openmp/libomptarget/plugins/amdgpu/impl/system.cpp |
 | openmp/libomptarget/plugins/amdgpu/impl/atmi.cpp |
Commit
e79e8041c5ff6a611390b6c3c8484d2cc80ab21d
by tomas.matheson[MC][NFCI] Factor out ELF section unique ID calculation
Precursor to D100944. The logic for determining the unique ID had become quite difficult to reason about, so I have factored this out into a separate function.
Differential Revision: https://reviews.llvm.org/D102336
|
 | llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp |
Commit
165321b3d27de5349520b5fdb7e08cbd238c880f
by tomas.matheson[MC][ELF] Emit unique sections for different flags
Global values imply flags such as readable, writable, executable for the sections that they will be placed in. Currently MC places all such entries into the same section, using the first set of flags seen. This can lead to situations in LTO where a writable global is placed in the same named section as a readable global from another file, and the section may not be marked writable.
D72194 ensures that mergeable globals with explicit sections are placed in separate sections with compatible entry size, by emitting the `unique` assembly syntax where appropriate. This change extends that approach to include section flags, so that globals with different section flags are emitted in separate unique sections.
Differential revision: https://reviews.llvm.org/D100944
|
 | llvm/test/CodeGen/X86/explicit-section-mergeable.ll |
 | llvm/unittests/ExecutionEngine/Orc/RTDyldObjectLinkingLayerTest.cpp |
 | llvm/test/CodeGen/Mips/gpopt-explict-section.ll |
 | llvm/include/llvm/MC/MCContext.h |
 | llvm/lib/MC/MCContext.cpp |
 | llvm/test/CodeGen/Generic/elf-unique-sections-by-flags.ll |
Commit
cebdf5d8465c71e43386ecec14ec1eb4b208f626
by pyadav2299[Docs] Updated the content of getting started documentation under llvm/lib/MC
Wrote about llvm/lib/MC subproject on https://llvm.org/docs/GettingStarted.html page.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D101047
|
 | llvm/docs/GettingStarted.rst |
Commit
ab8c44112c481fb32917b8e9b22b7576a4d6656d
by tomas.matheson[MC] Move elf-unique-sections-by-flags.ll to X86/
|
 | llvm/test/CodeGen/X86/elf-unique-sections-by-flags.ll |
 | llvm/test/CodeGen/Generic/elf-unique-sections-by-flags.ll |
Commit
ba0fe85ec0e93db44f9babaace84cb9ab29ff5f4
by sven.vanhaastregt[OpenCL] Include header for atomic-ops test
Avoid duplicating the memory_order and memory_scope enum definitions.
|
 | clang/test/SemaOpenCL/atomic-ops.cl |
Commit
5fb58d45989d63c2deee1c901c3d02b6cf01a067
by mkazantsev[Test] Add Loop Deletion test with irreducible CFG
Authored by Mikael Holmén. It demonstrated miscompile on irreducible CFG with patch "[LoopDeletion] Break backedge if we can prove that the loop is exited on 1st iteration". The patch is reverted. Checking in the test to make sure this bug does not return.
|
 | llvm/test/Transforms/LoopDeletion/irreducible-cfg.ll |
Commit
8ac66d61eab3dd44defa5755b884eca71a19431c
by andrew.savonichev[AArch64] Generate LD1 for anyext i8 or i16 vector load
The existing LD1 patterns do not cover cases where result type does not match the memory type. This happens when illegal vector types are extended and scalarized, for example:
load <2 x i16>* %v2i16
is lowered into:
// first element (v4i32 (insert_subvector (v2i32 (scalar_to_vector (load anyext from i16))))) // other elements (v4i32 (insert_vector_elt (i32 (load anyext from i16)) idx))
Before this patch these patterns were compiled into LDR + INS. Now they are compiled into LD1.
The problem was reported in PR24820: LLVM Generates abysmal code in simple situation.
Differential Revision: https://reviews.llvm.org/D102938
|
 | llvm/lib/Target/AArch64/AArch64InstrInfo.td |
 | llvm/test/CodeGen/AArch64/aarch64-load-ext.ll |
 | llvm/test/CodeGen/AArch64/ssub_sat_vec.ll |
 | llvm/test/CodeGen/AArch64/sadd_sat_vec.ll |
Commit
dee46d08293f2ff693893d85c472029207ce750e
by akuegel[mlir] Fold complex.create(complex.re(op), complex.im(op))
Differential Revision: https://reviews.llvm.org/D103148
|
 | mlir/lib/Dialect/Complex/IR/ComplexOps.cpp |
 | mlir/include/mlir/Dialect/Complex/IR/ComplexOps.td |
 | mlir/test/Dialect/Complex/canonicalize.mlir |
Commit
43d2e51c2e86788b9e2a582fdd3d8ffa7829328a
by mkazantsevReturn "[LoopDeletion] Break backedge if we can prove that the loop is exited on 1st iteration"
The patch was reverted due to compile time impact of contextual SCEV queries. It also appeared that it introduced a miscompile on irreducible CFG.
Changes made: 1. isKnownPredicateAt is replaced with more lightweight isKnownPredicate; 2. Irreducible CFG in live code is now detected and excluded from processing.
Differential Revision: https://reviews.llvm.org/D102615
|
 | llvm/test/Transforms/LoopDeletion/zero-btc.ll |
 | llvm/lib/Transforms/Scalar/LoopDeletion.cpp |
 | llvm/test/Transforms/LoopDeletion/eval_first_iteration.ll |
Commit
0de553dce0098e2606345ec5b89cf7d14599c643
by mkazantsevRevert "Return "[LoopDeletion] Break backedge if we can prove that the loop is exited on 1st iteration""
This reverts commit 43d2e51c2e86788b9e2a582fdd3d8ffa7829328a.
Commited wrong version.
|
 | llvm/test/Transforms/LoopDeletion/zero-btc.ll |
 | llvm/test/Transforms/LoopDeletion/eval_first_iteration.ll |
 | llvm/lib/Transforms/Scalar/LoopDeletion.cpp |
Commit
b70fe92f08e8aac8fa2e0d46d5d0a1ae56fe9d2f
by spatel[InstCombine] avoid 'tmp' usage in test file; NFC
The update script ( utils/update_test_checks.py ) warns against this.
|
 | llvm/test/Transforms/InstCombine/select.ll |
Commit
9e43b1e9a1f3b261ef998003bf7edba96d8c64a5
by spatel[InstCombine] avoid 'tmp' usage in test files; NFC
The update script ( utils/update_test_checks.py ) warns against this.
|
 | llvm/test/Transforms/InstCombine/fmul-exp2.ll |
 | llvm/test/Transforms/InstCombine/fmul-exp.ll |
Commit
01120fe5b39837f87e6fa34a5227b8f8634d7b01
by spatel[InstCombine] add fmul tests with shared operand; NFC
Baseline tests for: D102698
|
 | llvm/test/Transforms/InstCombine/fmul-exp.ll |
 | llvm/test/Transforms/InstCombine/fmul-exp2.ll |
Commit
be1a23203b1de655b8c7dac7549818d975a0cbbf
by mkazantsevReturn "[LoopDeletion] Break backedge if we can prove that the loop is exited on 1st iteration" (try 2)
The patch was reverted due to compile time impact of contextual SCEV queries. It also appeared that it introduced a miscompile on irreducible CFG.
Changes made: 1. isKnownPredicateAt is replaced with more lightweight isKnownPredicate; 2. Irreducible CFG in live code is now detected and excluded from processing.
Differential Revision: https://reviews.llvm.org/D102615
|
 | llvm/test/Transforms/LoopDeletion/eval_first_iteration.ll |
 | llvm/lib/Transforms/Scalar/LoopDeletion.cpp |
 | llvm/test/Transforms/LoopDeletion/zero-btc.ll |
Commit
9f76a8526010015fc3e5046fb2c5925000ac45a4
by kerry.mclaughlin[LoopVectorize] Enable strict reductions when allowReordering() returns false
When loop hints are passed via metadata, the allowReordering function in LoopVectorizationLegality will allow the order of floating point operations to be changed:
bool allowReordering() const { // When enabling loop hints are provided we allow the vectorizer to change // the order of operations that is given by the scalar loop. This is not // enabled by default because can be unsafe or inefficient.
The -enable-strict-reductions flag introduced in D98435 will currently only vectorize reductions in-loop if hints are used, since canVectorizeFPMath() will return false if reordering is not allowed.
This patch changes canVectorizeFPMath() to query whether it is safe to vectorize the loop with ordered reductions if no hints are used. For testing purposes, an additional flag (-hints-allow-reordering) has been added to disable the reordering behaviour described above.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D101836
|
 | llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll |
 | llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h |
 | llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp |
 | llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll |
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
Commit
8be23ed3f02ae633193c400909d135876de6c8cb
by a.bataev[SLP][NFC]Add a test for multiple uses of insertelement instruction, NFC.
|
 | llvm/test/Transforms/SLPVectorizer/X86/insert-element-multiple-uses.ll |
Commit
63cc9fd579b20e225d1109ebd077a6a13c97c2ab
by andrea.dibiagio[MCA][InOrderIssueStage] Fix LastWriteBackCycle computation.
Conservatively use the instruction latency to compute the last write-back cycle. Before this patch, the last write cycle computation was incorrect for store instructions that didn't declare any register writes.
|
 | llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s |
 | llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s |
 | llvm/lib/MCA/Stages/InOrderIssueStage.cpp |
Commit
629e2b3442257937486bd7a5c8239c173492963e
by llvm-dev[X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads
|
 | llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll |
 | llvm/test/CodeGen/X86/combine-mul.ll |
 | llvm/test/CodeGen/X86/vec_shift6.ll |
 | llvm/test/CodeGen/X86/avx2-arith.ll |
 | llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll |
 | llvm/test/CodeGen/X86/sse-domains.ll |
 | llvm/test/CodeGen/X86/vector-gep.ll |
 | llvm/test/CodeGen/X86/oddsubvector.ll |
 | llvm/test/CodeGen/X86/x86-shifts.ll |
 | llvm/test/CodeGen/X86/combine-rotates.ll |
 | llvm/test/CodeGen/X86/sse2-vector-shifts.ll |
Commit
a409fcddaed9ad4468d781a447fc5a4b3aac90d4
by david.green[ARM] Extra test for reverted WLS memset. NFC
|
 | llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll |
Commit
b6f6501b2412ffaf5d7dce539de3c382b1cf9b64
by sjoerd.meijer[CostModel][AArch64] Add tests for bitreverse. NFC.
|
 | llvm/test/Analysis/CostModel/AArch64/bitreverse.ll |
Commit
4ed2b6cccdef912013c84244c3f5ee4c018de9b1
by yuanke.luo[X86][AMX] Fix a bug on tile config.
The previous code detect if a MBB is bottom block to determine if it is a backedge of a loop. We should check latch block instead of bottom block and we should check the header and the bottom block are in the same loop.
Differential Revision: https://reviews.llvm.org/D103145
|
 | llvm/test/CodeGen/X86/AMX/amx-gemm.ll |
 | llvm/lib/Target/X86/X86PreTileConfig.cpp |
Commit
a8f75d497daa2684a03909d7c31d5bce11b427e1
by hans[clang-cl] Add driver support for /std:c++20 and bump /std:c++latest (PR50465)
VS 2019 16.11 (just released in Preview) is adding support for the /std:c++20 option and bumping /std:c++latest to "post-c++20". This updates clang-cl to match.
Differential revision: https://reviews.llvm.org/D103155
|
 | clang/test/Driver/cl-options.c |
 | clang/include/clang/Driver/Options.td |
 | clang/lib/Driver/ToolChains/Clang.cpp |
Commit
b37a2fcd8d7c59c3db4b1c64bbdba6d1bbea9e99
by anirudh_prasad[SystemZ][z/OS] Validate symbol names for z/OS for printing without quotes
- Currently, before printing a label in MCSymbol.cpp (MCSymbol::print), the current code "validates" the label that is to be printed. - If it fails the validation step, then it prints the label within double quotes. - However, the validation is provided as a virtual function in MCAsmInfo.h (i.e. isAcceptableChar() function). So we can override this for the AD_HLASM dialect in SystemZMCAsmInfo.cpp.
Reviewed By: uweigand
Differential Revision: https://reviews.llvm.org/D103091
|
 | llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h |
 | llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp |
 | llvm/unittests/MC/SystemZ/SystemZAsmLexerTest.cpp |
Commit
fcd32d62c0675abccac7b7f919bb0df52b6c4262
by sebastian.neubauer[AMDGPU] Fix function pointer argument bug in AMDGPU Propagate Attributes pass.
This patch fixes a bug in the AMDGPU Propagate Attributes pass where a call instruction with a function pointer argument is identified as a user of the passed function, and illegally replaces the called function of the instruction with the function argument.
For example, given functions f and g with appropriate types, the following illegal transformation could occur without this fix: call void @f(void ()* @g) --> call void @g(void ()* @g.1)
The solution introduced in this patch is to prevent the cloning and substitution if the instruction's called function and the function which might be cloned do not match.
Reviewed By: arsenm, madhur13490
Differential Revision: https://reviews.llvm.org/D101847
|
 | llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp |
 | llvm/test/CodeGen/AMDGPU/propagate-attributes-function-pointer-argument.ll |
Commit
1bc0e857bfd4d5a10675b5b75494c2ea6cff7c78
by anirudh_prasad[SystemZ][z/OS] Enable the AllowAtInName attribute for the HLASM dialect
- Currently, LLVM supports symbols of the name "token1@token2". - "token2" is used to identify whether an appropriate symbol reference can be used for the symbol. - Now, if the symbol reference couldn't be found, the AsmParser usually emits an error, unless the backend is configured to accept the "@" in a symbol name - Thus, this patch aims to do that. It sets the `AllowAtInName` attribute in the SystemZ backend for the HLASM dialect. - Setting this attribute ensures that, if a particular symbol reference is found, it uses that. If it doesn't, and there exists an "@" in the symbol name, it will use that instead of explicitly erroring out.
Reviewed By: uweigand
Differential Revision: https://reviews.llvm.org/D103111
|
 | llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp |
Commit
5f500d73cd1aaff4c9ab2fd5c327c2d5ca9ae5c9
by andrea.dibiagio[MCA] Add a test for PR50483. NFC
|
 | llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s |
Commit
8f79203a22d8e04086f4cc9a58bb365148852a09
by kadircet[clangd] New ParsingCallback for semantics changes
Previously notification of the Server about semantic happened strictly before notification of the AST thread. Hence a racy Server could make a request (like semantic tokens) after the notification, with the assumption that it'll be served fresh content. But it wasn't true if AST thread wasn't notified about the change yet.
This change reverses the order of those notifications to prevent racy interactions.
Differential Revision: https://reviews.llvm.org/D102761
|
 | clang-tools-extra/clangd/ClangdServer.cpp |
 | clang-tools-extra/clangd/TUScheduler.cpp |
 | clang-tools-extra/clangd/TUScheduler.h |
Commit
d058262b1471c80577924fc988ee86e175e3fc16
by paulsson[SystemZ] Support i128 inline asm operands.
Support virtual, physical and tied i128 register operands in inline assembly.
i128 is on SystemZ not really supported and is not a legal type and generally such a value will be split into two i64 parts. There are however some instructions that require a pair of two GPR64 registers contained in the GR128 bit reg class, which is untyped.
For inline assmebly operands, it proved to be very cumbersome to first follow the general behavior of splitting an i128 operand into two parts and then later rebuild the INLINEASM MI to have one GR128 register. Instead, some minor common code changes were made to SelectionDAGBUilder to only create one GR128 register part to begin with. In particular:
- getNumRegisters() now has an optional parameter "RegisterVT" which is passed by AddInlineAsmOperands() and GetRegistersForValue().
- The bitcasting in GetRegistersForValue is not performed if RegVT is Untyped.
- The RC for a tied use in AddInlineAsmOperands() is now computed either from the tied def (virtual register), or by getMinimalPhysRegClass() (physical register).
- InstrEmitter.cpp:EmitCopyFromReg() has been fixed so that the register class (DstRC) can also be computed for an illegal type.
In the SystemZ backend getNumRegisters(), splitValueIntoRegisterParts() and joinRegisterPartsIntoValue() have been implemented to handle i128 operands.
Differential Revision: https://reviews.llvm.org/D100788
Review: Ulrich Weigand
|
 | llvm/lib/Target/SystemZ/SystemZISelLowering.h |
 | llvm/lib/Target/SystemZ/SystemZISelLowering.cpp |
 | llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp |
 | llvm/test/CodeGen/SystemZ/inline-asm-i128.ll |
 | llvm/include/llvm/CodeGen/TargetLowering.h |
 | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp |
Commit
31191e15b6e362bcbd83353344bbb102f822762d
by Louis Dionne[libc++] Fix concepts tests with GCC
|
 | libcxx/test/std/concepts/concepts.callable/concept.invocable/invocable.compile.pass.cpp |
 | libcxx/test/std/concepts/concepts.callable/concept.regularinvocable/regular_invocable.compile.pass.cpp |
 | libcxx/test/std/concepts/concepts.callable/concept.regularinvocable/regular_invocable.pass.cpp |
Commit
9cc2181ec3885b5b505849448955659b3c6299d5
by listmail[unroll] Use value domain for symbolic execution based cost model
The current full unroll cost model does a symbolic evaluation of the loop up to a fixed limit. That symbolic evaluation currently simplifies to constants, but we can generalize to arbitrary Values using the InstructionSimplify infrastructure at very low cost.
By itself, this enables some simplifications, but it's mainly useful when combined with the branch simplification over in D102928.
Differential Revision: https://reviews.llvm.org/D102934
|
 | llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp |
 | llvm/test/Transforms/LoopUnroll/unroll-cost-symbolic-execute.ll |
 | llvm/include/llvm/Analysis/LoopUnrollAnalyzer.h |
 | llvm/lib/Analysis/LoopUnrollAnalyzer.cpp |
 | llvm/unittests/Analysis/UnrollAnalyzerTest.cpp |
Commit
1005ef445dbf71e70966856e9a78aa9322125f37
by clementval[mlir][openacc] Translate UpdateOp to LLVM IR
Add translation to LLVM IR for the UpdateOp with host and device operands. Translation is done with call using the runtime. This is done in a similar way as D101504 and D102381.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D102382
|
 | mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp |
 | mlir/test/Target/LLVMIR/openacc-llvm.mlir |
Commit
16342e39947bca83b25c251a65c7ea86a244a092
by koraq[libc++][NFC] Move format_error to its own header.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D101723
|
 | libcxx/include/__format/format_error.h |
 | libcxx/include/CMakeLists.txt |
 | libcxx/include/format |
Commit
deb6a0f94a24301a015d88a943d1acb429024f72
by llvmgnsyncbot[gn build] Port 16342e39947b
|
 | llvm/utils/gn/secondary/libcxx/include/BUILD.gn |
Commit
de9df3f5b952f66d6b80f9e4d957eb82f3021d71
by koraq[libc++][NFC] Move basic_format_parse_context to its own header.
This is a preparation to split the format header in smaller parts for the upcoming patches.
Depends on D101723
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D102703
|
 | libcxx/include/format |
 | libcxx/include/__format/format_parse_context.h |
 | libcxx/include/CMakeLists.txt |
Commit
74a89cba8ced90520f129083bd3c97cfce717bbc
by pifon[mlir] Add `distributionTypes` to LinalgTilingOptions.
Differential Revision: https://reviews.llvm.org/D103161
|
 | mlir/lib/Dialect/Linalg/Utils/Utils.cpp |
 | mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h |
 | mlir/include/mlir/Dialect/Linalg/Utils/Utils.h |
 | mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp |
 | mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td |
 | mlir/include/mlir/Dialect/Linalg/Passes.h |
 | mlir/test/Dialect/Linalg/tile-tensors.mlir |
 | mlir/include/mlir/Dialect/Linalg/Passes.td |
Commit
963495f0d4b5a0707f82b6c6454f42f3aa52da9b
by koraq[libc++][format] Adds availability macros for std::format.
This prevents std::format to be available until there's an ABI stable version. (This only impacts the Apple platform.)
Depends on D102703
Reviewed By: ldionne, #libc
Differential Revision: https://reviews.llvm.org/D102705
|
 | libcxx/include/version |
 | libcxx/include/__availability |
 | libcxx/utils/generate_feature_test_macro_components.py |
 | libcxx/include/__format/format_parse_context.h |
Commit
e47311d88899088379ee25176c3246265d5322eb
by llvmgnsyncbot[gn build] Port de9df3f5b952
|
 | llvm/utils/gn/secondary/libcxx/include/BUILD.gn |
Commit
07f59baad634de8be91a266acf33465663b9d5f7
by jonathanchesterfield[libomptarget][nfc][amdgpu] Remove atmi_status_t type
ATMI_STATUS_UNKNOWN was unused, deleted references to it. Replaced ATMI_STATUS_{SUCCESS,ERROR} with HSA_STATUS_{SUCCESS,ERROR} Replaced atmi_status_t with hsa_status_t
Otherwise no change. In particular, conversions between atmi_status_t and hsa_status_t will now be conversions between hsa_status_t and itself.
Reviewed By: pdhaliwal
Differential Revision: https://reviews.llvm.org/D103115
|
 | openmp/libomptarget/plugins/amdgpu/impl/system.cpp |
 | openmp/libomptarget/plugins/amdgpu/impl/atmi.cpp |
 | openmp/libomptarget/plugins/amdgpu/impl/rt.h |
 | openmp/libomptarget/plugins/amdgpu/impl/atmi.h |
 | openmp/libomptarget/plugins/amdgpu/impl/atmi_interop_hsa.h |
 | openmp/libomptarget/plugins/amdgpu/impl/atmi_runtime.h |
 | openmp/libomptarget/plugins/amdgpu/impl/data.cpp |
 | openmp/libomptarget/plugins/amdgpu/src/rtl.cpp |
 | openmp/libomptarget/plugins/amdgpu/impl/utils.cpp |
 | openmp/libomptarget/plugins/amdgpu/impl/atmi_interop_hsa.cpp |
 | openmp/libomptarget/plugins/amdgpu/impl/internal.h |
Commit
ea91a8cbab93e6592c918b771942598ad0e9b571
by sebastian.neubauer[AMDGPU][NFC] Remove non-existing function header
|
 | llvm/lib/Target/AMDGPU/SIRegisterInfo.h |
Commit
1b47a3de48d2ac3ee4420209ab5d191f66849979
by craig.topper[RISCV] Enable cross basic block aware vsetvli insertion
This patch extends D102737 to allow VL/VTYPE changes to be taken into account before adding an explicit vsetvli.
We do this by using a data flow analysis to propagate VL/VTYPE information from predecessors until we've determined a value for every value in the function.
We use this information to determine if a vsetvli needs to be inserted before the first vector instruction the block.
Differential Revision: https://reviews.llvm.org/D102739
|
 | llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll |
Commit
d28bc54ff44aad7b080177ef85764d7c5444f031
by Raphael Isemann[lldb] Remove cache in get_demangled_name_without_arguments
This function has a single-value caching based on function local static variables.
This causes two problems:
* There is no synchronization, so this function randomly returns the demangled name of other functions that are demangled at the same time. * The 1-element cache is not very effective (the cache rate is around 0% when running the LLDB test suite that calls this function around 30k times).
I would propose just removing it.
To prevent anyone else the git archeology: the static result variables were originally added as this returned a ConstString reference, but that has since been changed so that this returns by value.
Reviewed By: #lldb, JDevlieghere, shafik
Differential Revision: https://reviews.llvm.org/D103107
|
 | lldb/source/Core/Mangled.cpp |
Commit
adf1561d6ce8af057127c65af863b3f0e1c77e60
by smeenai[libunwind] Inform ASan that resumption is noreturn
If you're building libunwind instrumented with ASan, `_Unwind_RaiseException` will poison the stack and then transfer control in a manner which isn't understood by ASan, so the stack will remain poisoned. This can cause false positives, e.g. if you call an uninstrumented function (so it doesn't re-poison the stack) after catching an exception. Add a call to `__asan_handle_no_return` inside `__unw_resume` to get ASan to unpoison the stack and avoid this.
`__unw_resume` seems like the appropriate place to make this call, since it's used for resumption by all unwind implementations except SJLJ. SJLJ uses `__builtin_longjmp` to handle resumption, which is already recognized as noreturn (and therefore ASan adds the `__asan_handle_no_return` call itself), so it doesn't need any special handling.
PR32434 is somewhat similar (in particular needing a component built without ASan to trigger the bug), and rG781ef03e1012, the fix for that bug, adds an interceptor for `_Unwind_RaiseException`. This interceptor won't always be triggered though, e.g. if you statically link the unwinder into libc++abi in a way that prevents interposing the unwinder functions (e.g. marking the symbols as hidden, using `--exclude-libs`, or using `-Bsymbolic`). rG53335d6d86d5 makes `__cxa_throw` call `__asan_handle_no_return` explicitly, to similarly avoid relying on interception.
Reviewed By: #libunwind, compnerd
Differential Revision: https://reviews.llvm.org/D103002
|
 | libunwind/src/libunwind.cpp |
Commit
969eefd98e0f8e485148be61190cc2ef62fb1eca
by smeenai[lldb] add LLDB_SKIP_DSYM option
Add an option to skip generating a dSYM when installing the LLDB framework on Darwin.
Reviewed By: smeenai
Differential Revision: https://reviews.llvm.org/D103124
|
 | lldb/cmake/modules/AddLLDB.cmake |
 | lldb/cmake/modules/LLDBConfig.cmake |
Commit
a0bd6105d80698c53ceaa64bbe6e3b7e7bbf99ee
by stephen.tozer[DebugInfo] Limit the number of values that may be referenced by a dbg.value
Following the addition of salvaging dbg.values using DIArgLists to reference multiple values, a case has been found where excessively large DIArgLists are produced as a result of this salvaging, resulting in large enough performance costs to effectively freeze the compiler.
This patch introduces an upper bound of 16 to the number of values that may be salvaged into a dbg.value, to limit the impact of these extreme cases to performance.
Differential Revision: https://reviews.llvm.org/D103162
|
 | llvm/lib/Transforms/Utils/Local.cpp |
 | llvm/test/DebugInfo/limit-arglist-size.ll |
Commit
27d3528acf8aacc62a955dc13b0f08d4167b5b48
by a.bataev[SLP]Fix vectorization of insertelements with multiple uses.
SLP vectorizer should not consider in sertelements with multiple uses as a part of high level build vector, it must be considered as a terminating insertelement in the vector build, otherwise it may produce incorrect code.
Differential Revision: https://reviews.llvm.org/D103164
|
 | llvm/test/Transforms/SLPVectorizer/X86/insert-element-multiple-uses.ll |
 | llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp |
Commit
a45877eea8c424cd91bc1f7749313c9cb3aab285
by kostyak[scudo] Get rid of initLinkerInitialized
Now that everything is forcibly linker initialized, it feels like a good time to get rid of the `init`/`initLinkerInitialized` split.
This allows to get rid of various `memset` construct in `init` that gcc complains about (this fixes a Fuchsia open issue).
I added various `DCHECK`s to ensure that we would get a zero-inited object when entering `init`, which required ensuring that `unmapTestOnly` leaves the object in a good state (tests are currently the only location where an allocator can be "de-initialized").
Running the tests with `--gtest_repeat=` showed no issue.
Differential Revision: https://reviews.llvm.org/D103119
|
 | compiler-rt/lib/scudo/standalone/tests/mutex_test.cpp |
 | compiler-rt/lib/scudo/standalone/tsd_shared.h |
 | compiler-rt/lib/scudo/standalone/secondary.h |
 | compiler-rt/lib/scudo/standalone/benchmarks/malloc_benchmark.cpp |
 | compiler-rt/lib/scudo/standalone/tests/tsd_test.cpp |
 | compiler-rt/lib/scudo/standalone/primary32.h |
 | compiler-rt/lib/scudo/standalone/primary64.h |
 | compiler-rt/lib/scudo/standalone/tsd_exclusive.h |
 | compiler-rt/lib/scudo/standalone/bytemap.h |
 | compiler-rt/lib/scudo/standalone/local_cache.h |
 | compiler-rt/lib/scudo/standalone/mutex.h |
 | compiler-rt/lib/scudo/standalone/combined.h |
 | compiler-rt/lib/scudo/standalone/quarantine.h |
 | compiler-rt/lib/scudo/standalone/stats.h |
 | compiler-rt/lib/scudo/standalone/tsd.h |
 | compiler-rt/lib/scudo/standalone/tests/combined_test.cpp |
Commit
b2c7ac874f516df38968d02636ecab7730ca9323
by craig.topper[RISCV] Don't propagate VL/VTYPE across inline assembly in the Insert VSETVLI pass.
It's conceivable someone could put a vsetvli in inline assembly so its safer to consider them as barriers. The alternative would be to trust that the user marks VL and VTYPE registers as clobbers of the inline assembly if they do that, but hat seems error prone.
I'm assuming inline assembly in vector code is going to be rare.
Reviewed By: frasercrmck, HsiangKai
Differential Revision: https://reviews.llvm.org/D103126
|
 | llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir |
 | llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp |
Commit
d63d662d3cc51219fb08908ebea8d5851e53adb8
by jrtc27[RISCV] Remove --riscv-no-aliases from RVV tests
This serves no useful purpose other than to clutter things up. Diff summary as the real diff is extremely unwieldy:
24844 -; CHECK-NEXT: jalr zero, 0(ra) 24844 +; CHECK-NEXT: ret 8 -; CHECK-NEXT: vl4re8.v v28, (a0) 8 +; CHECK-NEXT: vl4r.v v28, (a0) 64 -; CHECK-NEXT: vl8re8.v v24, (a0) 64 +; CHECK-NEXT: vl8r.v v24, (a0) 392 -; RUN: --riscv-no-aliases < %s | FileCheck %s 392 +; RUN: < %s | FileCheck %s 1 -; RUN: -verify-machineinstrs --riscv-no-aliases < %s \ 1 +; RUN: -verify-machineinstrs < %s \
As discussed in D103004.
|
 | llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll |
 | llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll |
Commit
6911114d8cbed06a8a809c34ae07f4e3e89ab252
by 31459023+hctim[Scudo] Make -fsanitize=scudo use standalone. Migrate tests.
This patch moves -fsanitize=scudo to link the standalone scudo library, rather than the original compiler-rt based library. This is one of the major remaining roadblocks to deleting the compiler-rt based scudo, which should not be used any more. The standalone Scudo is better in pretty much every way and is much more suitable for production usage.
As well as patching the litmus tests for checking that the scudo_standalone lib is linked instead of the scudo lib, this patch also ports all the scudo lit tests to run under scudo standalone.
This patch also adds a feature to scudo standalone that was under test in the original scudo - that arguments passed to an aligned operator new were checked that the alignment was a power of two.
Some lit tests could not be migrated, due to the following issues: 1. Features that aren't supported in scudo standalone, like the rss limit. 2. Different quarantine implementation where the test needs some more thought. 3. Small bugs in scudo standalone that should probably be fixed, like the Secondary allocator having a full page on the LHS of an allocation that only contains the chunk header, so underflows by <= a page aren't caught. 4. Slight differences in behaviour that's technically correct, like 'realloc(malloc(1), 0)' returns nullptr in standalone, but a real pointer in old scudo. 5. Some tests that might be migratable, but not easily.
Tests that are obviously not applicable to scudo standalone (like testing that no sanitizer symbols made it into the DSO) have been deleted.
After this patch, the remaining work is: 1. Update the Scudo documentation. The flags have changed, etc. 2. Delete the old version of scudo. 3. Patch up the tests in lit-unmigrated, or fix Scudo standalone.
Reviewed By: cryptoad, vitalybuka
Differential Revision: https://reviews.llvm.org/D102543
|
 | compiler-rt/test/scudo/malloc.cpp |
 | compiler-rt/test/scudo/lit.cfg.py |
 | compiler-rt/test/scudo/valloc.c |
 | compiler-rt/test/scudo/dealloc-race.c |
 | compiler-rt/test/scudo/sized-delete.cpp |
 | compiler-rt/test/scudo/realloc.cpp |
 | clang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/aarch64-unknown-fuchsia/libclang_rt.scudo_standalone.so |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/realloc.cpp |
 | compiler-rt/test/scudo/standalone/mismatch.cpp |
 | compiler-rt/test/scudo/random_shuffle.cpp |
 | compiler-rt/test/scudo/alignment.c |
 | compiler-rt/test/scudo/tsd_destruction.c |
 | compiler-rt/test/scudo/standalone/alignment.c |
 | compiler-rt/test/scudo/mismatch.cpp |
 | compiler-rt/test/scudo/double-free.cpp |
 | compiler-rt/test/scudo/standalone/tsd_destruction.c |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/secondary.c |
 | compiler-rt/test/scudo/preload.cpp |
 | compiler-rt/test/scudo/secondary.c |
 | compiler-rt/test/scudo/quarantine.c |
 | compiler-rt/test/scudo/options.cpp |
 | compiler-rt/test/scudo/rss.c |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/quarantine.c |
 | clang/test/Driver/fuchsia.c |
 | clang/lib/Driver/ToolChains/CommonArgs.cpp |
 | compiler-rt/test/scudo/standalone/aligned-new.cpp |
 | compiler-rt/test/scudo/threads.c |
 | compiler-rt/test/scudo/fsanitize.c |
 | compiler-rt/test/scudo/standalone/preinit.c |
 | compiler-rt/test/scudo/standalone/CMakeLists.txt |
 | compiler-rt/test/scudo/stats.c |
 | compiler-rt/test/scudo/lit.site.cfg.py.in |
 | clang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/aarch64-unknown-fuchsia/libclang_rt.scudo.so |
 | compiler-rt/test/scudo/standalone/random_shuffle.cpp |
 | compiler-rt/test/scudo/standalone/lit.cfg.py |
 | compiler-rt/test/scudo/standalone/double-free.cpp |
 | compiler-rt/test/scudo/overflow.c |
 | compiler-rt/test/scudo/standalone/preload.cpp |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/overflow.c |
 | compiler-rt/test/scudo/standalone/sized-delete.cpp |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/threads.c |
 | clang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/x86_64-unknown-fuchsia/libclang_rt.scudo.so |
 | compiler-rt/lib/scudo/standalone/wrappers_cpp.cpp |
 | compiler-rt/test/scudo/standalone/fsanitize.c |
 | compiler-rt/test/scudo/aligned-new.cpp |
 | compiler-rt/test/scudo/CMakeLists.txt |
 | compiler-rt/test/scudo/standalone/dealloc-race.c |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/valloc.c |
 | compiler-rt/test/scudo/sizes.cpp |
 | compiler-rt/test/scudo/symbols.test |
 | compiler-rt/test/scudo/memalign.c |
 | compiler-rt/test/scudo/standalone/stats.c |
 | compiler-rt/test/scudo/standalone/memalign.c |
 | compiler-rt/test/scudo/standalone/malloc.cpp |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/sizes.cpp |
 | compiler-rt/test/scudo/standalone/lit.site.cfg.py.in |
 | clang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/x86_64-unknown-fuchsia/libclang_rt.scudo_standalone.so |
 | clang/test/Driver/sanitizer-ld.c |
 | compiler-rt/test/scudo/standalone/options.cpp |
 | compiler-rt/test/scudo/interface.cpp |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/rss.c |
 | compiler-rt/test/scudo/preinit.c |
Commit
fb14577d0c4828f0e793072fc3e6bb3c57ec596e
by listmail[SCEV] Extract out a helper for computing trip multiples
|
 | llvm/lib/Analysis/ScalarEvolution.cpp |
 | llvm/include/llvm/Analysis/ScalarEvolution.h |
Commit
9065118b6463adf6cc5552f202cd8302c21cd7b0
by craig.topper[RISCV] Optimize SEW=64 shifts by splat on RV32.
SEW=64 shifts only uses the log2(64) bits of shift amount. If we're splatting a 64 bit value in 2 parts, we can avoid splatting the upper bits and just let the low bits be sign extended. They won't be read anyway.
For the purposes of SelectionDAG semantics of the generic ISD opcodes, if hi was non-zero or bit 31 of the low is 1, the shift was already undefined so it should be ok to replace high with sign extend of low.
In order do be able to find the split i64 value before it becomes a stack operation, I added a new ISD opcode that will be expanded to the stack spill in PreprocessISelDAG. This new node is conceptually similar to BuildPairF64, but I expanded earlier so that we could go through regular isel to get the right VLSE opcode for the LMUL. BuildPairF64 is expanded in a CustomInserter.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D102521
|
 | llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll |
 | llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll |
 | llvm/lib/Target/RISCV/RISCVISelLowering.h |
 | llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll |
 | llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll |
 | llvm/lib/Target/RISCV/RISCVISelLowering.cpp |
Commit
921d3f7af09c6a08d2d2897e6fcce6127a9f4fd4
by listmail[SCEV] Add a utility for converting from "exit count" to "trip count"
(Mostly as a logical place to put a comment since this is a reoccuring confusion.)
|
 | llvm/include/llvm/Analysis/ScalarEvolution.h |
 | llvm/lib/Analysis/ScalarEvolution.cpp |
 | llvm/lib/Analysis/LoopCacheAnalysis.cpp |
Commit
73a117953599af58645d944e68076ec8fb052540
by i[llvm-mc] Add -M to replace -riscv-no-aliases and -riscv-arch-reg-names
In objdump, many targets support `-M no-aliases`. Instead of having a `-*-no-aliases` for each target when LLVM adds the support, it makes more sense to introduce objdump style `-M`.
-riscv-arch-reg-names is removed. -riscv-no-aliases has too many uses and thus is retained for now.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D103004
|
 | llvm/tools/llvm-mc/llvm-mc.cpp |
 | llvm/test/MC/RISCV/numeric-reg-names-d.s |
 | llvm/test/MC/RISCV/rvi-aliases-valid.s |
 | llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp |
 | llvm/test/tools/llvm-mc/disassembler-options.test |
 | llvm/include/llvm/MC/MCInstPrinter.h |
 | llvm/test/MC/RISCV/numeric-reg-names-f.s |
 | llvm/test/MC/RISCV/numeric-reg-names.s |
Commit
f7c5c0d87b8ae5e55006fd3a31994cd68d64f102
by 31459023+hctimRevert "[Scudo] Make -fsanitize=scudo use standalone. Migrate tests."
This reverts commit 6911114d8cbed06a8a809c34ae07f4e3e89ab252.
Broke the QEMU sanitizer bots due to a missing header dependency. This actually needs to be fixed on the bot-side, but for now reverting this patch until I can fix up the bot.
|
 | compiler-rt/test/scudo/alignment.c |
 | compiler-rt/test/scudo/fsanitize.c |
 | clang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/x86_64-unknown-fuchsia/libclang_rt.scudo.so |
 | clang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/x86_64-unknown-fuchsia/libclang_rt.scudo_standalone.so |
 | compiler-rt/test/scudo/quarantine.c |
 | clang/test/Driver/sanitizer-ld.c |
 | compiler-rt/test/scudo/aligned-new.cpp |
 | compiler-rt/test/scudo/secondary.c |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/overflow.c |
 | compiler-rt/test/scudo/standalone/stats.c |
 | compiler-rt/test/scudo/double-free.cpp |
 | compiler-rt/test/scudo/symbols.test |
 | compiler-rt/test/scudo/threads.c |
 | compiler-rt/test/scudo/lit.cfg.py |
 | clang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/aarch64-unknown-fuchsia/libclang_rt.scudo_standalone.so |
 | compiler-rt/test/scudo/overflow.c |
 | clang/lib/Driver/ToolChains/CommonArgs.cpp |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/sizes.cpp |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/realloc.cpp |
 | compiler-rt/test/scudo/standalone/fsanitize.c |
 | compiler-rt/lib/scudo/standalone/wrappers_cpp.cpp |
 | compiler-rt/test/scudo/options.cpp |
 | compiler-rt/test/scudo/rss.c |
 | compiler-rt/test/scudo/sizes.cpp |
 | compiler-rt/test/scudo/stats.c |
 | compiler-rt/test/scudo/standalone/malloc.cpp |
 | compiler-rt/test/scudo/standalone/lit.cfg.py |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/threads.c |
 | compiler-rt/test/scudo/standalone/preinit.c |
 | compiler-rt/test/scudo/standalone/CMakeLists.txt |
 | compiler-rt/test/scudo/interface.cpp |
 | compiler-rt/test/scudo/standalone/options.cpp |
 | compiler-rt/test/scudo/standalone/sized-delete.cpp |
 | compiler-rt/test/scudo/lit.site.cfg.py.in |
 | compiler-rt/test/scudo/valloc.c |
 | compiler-rt/test/scudo/preload.cpp |
 | compiler-rt/test/scudo/standalone/mismatch.cpp |
 | compiler-rt/test/scudo/standalone/aligned-new.cpp |
 | compiler-rt/test/scudo/memalign.c |
 | compiler-rt/test/scudo/standalone/random_shuffle.cpp |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/quarantine.c |
 | compiler-rt/test/scudo/CMakeLists.txt |
 | compiler-rt/test/scudo/standalone/preload.cpp |
 | compiler-rt/test/scudo/tsd_destruction.c |
 | compiler-rt/test/scudo/random_shuffle.cpp |
 | compiler-rt/test/scudo/standalone/tsd_destruction.c |
 | clang/test/Driver/fuchsia.c |
 | compiler-rt/test/scudo/preinit.c |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/secondary.c |
 | compiler-rt/test/scudo/standalone/memalign.c |
 | compiler-rt/test/scudo/standalone/double-free.cpp |
 | clang/test/Driver/Inputs/resource_dir_with_per_target_subdir/lib/aarch64-unknown-fuchsia/libclang_rt.scudo.so |
 | compiler-rt/test/scudo/malloc.cpp |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/rss.c |
 | compiler-rt/test/scudo/sized-delete.cpp |
 | compiler-rt/test/scudo/standalone/dealloc-race.c |
 | compiler-rt/test/scudo/standalone/alignment.c |
 | compiler-rt/test/scudo/realloc.cpp |
 | compiler-rt/test/scudo/standalone/lit-unmigrated/valloc.c |
 | compiler-rt/test/scudo/standalone/lit.site.cfg.py.in |
 | compiler-rt/test/scudo/dealloc-race.c |
 | compiler-rt/test/scudo/mismatch.cpp |
Commit
e5eff533f7611967ae1ead99846d06597dcb8ee2
by thomasraoux[mlir] Make StripDebugInfo strip out block arguments locs
Differential Revision: https://reviews.llvm.org/D103187
|
 | mlir/lib/Transforms/StripDebugInfo.cpp |
 | mlir/test/Transforms/strip-debuginfo.mlir |
Commit
9306bb638ff2b13fb8472b5b035e658c1dcbd74c
by listmail[SCEV] Generalize getSmallConstantTripCount(L) for multiple exit loops
This came up in review for another patch, see https://reviews.llvm.org/D102982#2782407 for full context.
I've reviewed the callers to make sure they can handle multiple exit loops w/non-zero returns. There's two cases in target cost models where results might change (Hexagon and PowerPC), but the results looked legal and reasonable. If a target maintainer wishes to back out the effect of the costing change, they should explicitly check for multiple exit loops and handle them as desired.
Differential Revision: https://reviews.llvm.org/D103182
|
 | llvm/lib/Analysis/ScalarEvolution.cpp |
 | llvm/include/llvm/Analysis/ScalarEvolution.h |
Commit
c5c1ec7945ff2c26f4f9ce5db5ff647ee3f931ab
by jonathanchesterfield[libomptarget][nfc][amdgpu] Refactor uses of KernelInfoTable
Suggested in D103059. Use a single lookup instead of two, more const, less mutation.
Reviewed By: dhruvachak
Differential Revision: https://reviews.llvm.org/D103093
|
 | openmp/libomptarget/plugins/amdgpu/src/rtl.cpp |
Commit
13c6568c6e20ee70aaa8157431e8a3d01be07e81
by dmitry.preobrazhensky[AMDGPU][MC][GFX90A] Corrected DS_GWS opcodes
Corrected DS_GWS opcodes to use even aligned registers.
Differential Revision: https://reviews.llvm.org/D103185
|
 | llvm/test/MC/AMDGPU/gfx90a_err_pos.s |
 | llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt |
 | llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s |
 | llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp |
 | llvm/test/MC/AMDGPU/gfx90a_err.s |
Commit
5e2facb922840bfd03eb116eaeead039df021275
by Stanislav.Mekhanoshin[AMDGPU] Fix kernel LDS lowering for constants
There is a trivial but severe bug in the recent code collecting LDS globals used by kernel. It aborts scan on the first constant without scanning further uses. That leads to LDS overallocation with multiple kernels in certain cases.
Differential Revision: https://reviews.llvm.org/D103190
|
 | llvm/lib/Target/AMDGPU/Utils/AMDGPULDSUtils.cpp |
 | llvm/test/CodeGen/AMDGPU/ds_read2.ll |
 | llvm/test/CodeGen/AMDGPU/ds_write2.ll |
 | llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll |
Commit
5bfe06ad3590d5aeb14c2fc3fae729abc6412cb3
by aheejin[SimplifyCFG] Use make_early_inc_range() while deleting instructions
We are deleting `phi` nodes within the for loop, so this makes sure we increment the iterator before we delete the instruction pointed by the iterator.
This started to break in https://github.com/llvm/llvm-project/commit/a0be08164622bf938855ff5d19dd8e9d0c96b9b3.
Reviewed By: dschuff, lebedev.ri
Differential Revision: https://reviews.llvm.org/D103181
|
 | llvm/test/Transforms/SimplifyCFG/cleanup-phis.ll |
 | llvm/lib/Transforms/Utils/SimplifyCFG.cpp |
Commit
5dd86aadf0b014913bd35bb7435808eb081bc049
by aheejin[WebAssembly] Add TargetInstrInfo::getCalleeOperand
DwarfDebug unconditionally assumes for all call instructions the 0th operand is the callee operand, which seems to be true for other targets, but not for WebAssembly. This adds `TargetInstrInfo::getCallOperand` method whose default implementation returns `getOperand(0)` and makes WebAssembly overrides it to use its own utility method to get the callee operand.
This also fixes an existing bug in `WebAssembly::getCalleeOp`, which was uncovered by this CL.
Reviewed By: dschuff, djtodoro
Differential Revision: https://reviews.llvm.org/D102978
|
 | llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp |
 | llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp |
 | llvm/include/llvm/CodeGen/TargetInstrInfo.h |
 | llvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.cpp |
 | llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h |
 | llvm/test/DebugInfo/WebAssembly/call-site.ll |
Commit
ff08c3468fa4ba25384104206255f3648fd21fe9
by listmail[SCEV] Compute trip multiple for multiple exit loops
This patch implements getSmallConstantTripMultiple(L) correctly for multiple exit loops. The previous implementation was both imprecise, and violated the specified behavior of the method. This was fine in practice, because it turns out the function was both dead in real code, and not tested for the multiple exit case.
Differential Revision: https://reviews.llvm.org/D103189
|
 | llvm/lib/Analysis/ScalarEvolution.cpp |
 | llvm/test/Analysis/ScalarEvolution/tripmultiple_calculation.ll |
 | llvm/include/llvm/Analysis/ScalarEvolution.h |
Commit
78c9796f963f0577b86de7bf062f65b4595cb757
by lebedev.ri[NFC][X86][Costmodel] Add some more interleaved load/store test with i16 element type
Not sure if even larger interleaving factors are needed, but these are what i have seen being queried in the wild.
|
 | llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll |
 | llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll |
 | llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll |
 | llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll |
 | llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll |
 | llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll |
 | llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll |
 | llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll |
 | llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll |
 | llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-5.ll |
Commit
ab7f26dc13f282101691370f98f3c0e4371ea12d
by lebedev.ri[NFC][Codegen][X86] Add a few more interleaved load/store patterns w/ i16 element type
Matching the costmodel coverage. We want them both because they simplify coming up with the patterns to check their cost, and to track their codegen.
Tests for loads can be fully autogenerated: https://godbolt.org/z/o1fncqo9n For stores, however, i have done that semi-manually: https://godbolt.org/z/KPzTnvsh1
|
 | llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll |
 | llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll |
 | llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll |
 | llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll |
 | llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll |
 | llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll |
 | llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll |
 | llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll |
 | llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll |
 | llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll |
Commit
2fdf8bbd19c33c0eb5fdf88ff3cbd12aae607768
by jonathanchesterfield[libomptarget][nfc][amdgpu] Factor out setting upper bounds
Refactor suggested in D103037 to help avoid similar copy-paste errors. Change is mechanical. Some parts of this would be more robust with unsigned.
Reviewed By: dhruvachak
Differential Revision: https://reviews.llvm.org/D103090
|
 | openmp/libomptarget/plugins/amdgpu/src/rtl.cpp |
Commit
3b9a1bb1af90db9472340ef2122d3855eb9ba3fc
by Louis Dionne[pstl] Fix -Wundef errors in the test suite
|
 | pstl/include/pstl/internal/pstl_config.h |
 | pstl/include/pstl/internal/unseq_backend_simd.h |
 | pstl/test/std/algorithms/alg.modifying.operations/alg.partitions/is_partitioned.pass.cpp |
 | pstl/test/support/utils.h |
 | pstl/test/std/algorithms/alg.nonmodifying/count.pass.cpp |
 | pstl/test/std/algorithms/alg.modifying.operations/unique_copy_equal.pass.cpp |
 | pstl/test/std/algorithms/alg.sorting/alg.heap.operations/is_heap.pass.cpp |
 | pstl/test/std/algorithms/alg.modifying.operations/alg.copy/copy_if.pass.cpp |
 | pstl/test/std/algorithms/alg.nonmodifying/any_of.pass.cpp |
 | pstl/test/std/numerics/numeric.ops/reduce.pass.cpp |
 | pstl/test/std/algorithms/alg.nonmodifying/nth_element.pass.cpp |
 | pstl/test/std/algorithms/alg.modifying.operations/unique.pass.cpp |
 | pstl/include/pstl/internal/algorithm_impl.h |
 | pstl/test/std/algorithms/alg.modifying.operations/remove.pass.cpp |
 | pstl/test/std/utilities/memory/specialized.algorithms/uninitialized_copy_move.pass.cpp |
 | pstl/test/std/algorithms/alg.modifying.operations/alg.partitions/partition_copy.pass.cpp |
 | pstl/test/std/numerics/numeric.ops/scan.pass.cpp |
 | pstl/test/std/algorithms/alg.nonmodifying/find_first_of.pass.cpp |
 | pstl/test/std/algorithms/alg.nonmodifying/all_of.pass.cpp |
 | pstl/include/pstl/internal/execution_defs.h |
 | pstl/test/std/algorithms/alg.nonmodifying/find_end.pass.cpp |
 | pstl/test/std/algorithms/alg.nonmodifying/none_of.pass.cpp |
 | pstl/include/pstl/internal/glue_execution_defs.h |
 | pstl/include/pstl/internal/numeric_impl.h |
 | pstl/test/std/algorithms/alg.nonmodifying/search_n.pass.cpp |
 | pstl/test/std/algorithms/alg.nonmodifying/find_if.pass.cpp |
 | pstl/test/std/algorithms/alg.modifying.operations/alg.reverse/reverse.pass.cpp |
 | pstl/test/std/algorithms/alg.nonmodifying/equal.pass.cpp |
 | pstl/test/std/algorithms/alg.sorting/alg.lex.comparison/lexicographical_compare.pass.cpp |
 | pstl/test/std/algorithms/alg.modifying.operations/alg.partitions/partition.pass.cpp |
 | pstl/test/std/numerics/numeric.ops/transform_scan.pass.cpp |
 | pstl/test/std/algorithms/alg.modifying.operations/alg.reverse/reverse_copy.pass.cpp |
 | pstl/test/std/algorithms/alg.nonmodifying/find.pass.cpp |
 | pstl/test/std/algorithms/alg.merge/inplace_merge.pass.cpp |
 | pstl/test/std/utilities/memory/specialized.algorithms/uninitialized_construct.pass.cpp |
 | pstl/include/pstl/internal/execution_impl.h |
 | pstl/test/std/algorithms/alg.modifying.operations/rotate.pass.cpp |
 | pstl/test/std/algorithms/alg.modifying.operations/copy_move.pass.cpp |
 | pstl/test/std/algorithms/alg.sorting/partial_sort_copy.pass.cpp |
 | pstl/test/std/algorithms/alg.merge/merge.pass.cpp |
 | pstl/test/std/algorithms/alg.modifying.operations/replace_copy.pass.cpp |
 | pstl/test/std/numerics/numeric.ops/adjacent_difference.pass.cpp |
 | pstl/test/std/algorithms/alg.modifying.operations/rotate_copy.pass.cpp |
Commit
8496fc2ec8046727e298629aa74943be0137267b
by jeremy.morse[DebugInstrRef][1/3] Track PHI values through register allocation
This patch introduces "DBG_PHI" instructions, a marker of where a PHI instruction used to be, before PHI elimination. Under the instruction referencing model, we want to know where every value in the function is defined -- and a PHI, even if implicit, is such a place.
Just like instruction numbers, we can use this to identify a value to be used as a variable value, but we don't need to know what instruction defines that value, for example:
bb1: DBG_PHI $rax, 1 [... more insts ... ] bb2: DBG_INSTR_REF 1, 0, !1234, !DIExpression()
This specifies that on entry to bb1, whatever value is in $rax is known as value number one -- and the later DBG_INSTR_REF marks the position where variable !1234 should take on value number one.
PHI locations are stored in MachineFunction for the duration of the regalloc phase in the DebugPHIPositions map. The map is populated by PHIElimination, and then flushed back into the instruction stream by virtregrewriter. A small amount of maintenence is needed in LiveDebugVariables to account for registers being split, but only for individual positions, not for entire ranges of blocks.
Differential Revision: https://reviews.llvm.org/D86812
|
 | llvm/lib/CodeGen/LiveDebugVariables.cpp |
 | llvm/lib/CodeGen/PHIElimination.cpp |
 | llvm/include/llvm/Support/TargetOpcodes.def |
 | llvm/include/llvm/Target/Target.td |
 | llvm/lib/CodeGen/PrologEpilogInserter.cpp |
 | llvm/include/llvm/CodeGen/MachineInstr.h |
 | llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir |
 | llvm/include/llvm/CodeGen/MachineFunction.h |
 | llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp |
 | llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir |
Commit
6c92215e07f41cb566d54599e891180fe2ddbea5
by sjoerd.meijer[CostModel][AArch64] Add floating point arithmetic tests. NFC.
|
 | llvm/test/Analysis/CostModel/AArch64/mul.ll |
 | llvm/test/Analysis/CostModel/AArch64/arith-fp.ll |
Commit
c4823cc5db69f16bb5c96cf7d1b0d070da83605e
by Louis Dionne[pstl] Workaround more errors in the test suite
|
 | pstl/include/pstl/internal/pstl_config.h |
 | pstl/test/std/algorithms/alg.modifying.operations/replace.pass.cpp |
 | pstl/test/std/numerics/numeric.ops/transform_reduce.pass.cpp |
Commit
cc622aee302381b81acd6070206c84bab5bace71
by Louis Dionne[libc++] Add a job testing on GCC 11
I'm adding the job as a soft-fail for now, but once all the tests have been fixed to work on it, we'll switch over from GCC 10 to GCC 11 and remove the soft-fail.
Differential Revision: https://reviews.llvm.org/D103116
|
 | libcxx/utils/ci/buildkite-pipeline.yml |
 | libcxx/utils/ci/run-buildbot |
Commit
1494fa6943380fd0ee327c3349b648a32e679f7f
by mtrofinUpdate documentation for InlineModel features.
Reviewed By: mtrofin
Differential Revision: https://reviews.llvm.org/D103193
|
 | llvm/include/llvm/Analysis/InlineModelFeatureMaps.h |
Commit
e4fc8c3de8f38eab1feae5ec34e9bc573153d370
by jrtc27[RISCV][NFC] Fix some whitespace nits in MC test RUN lines
|
 | llvm/test/MC/RISCV/user-csr-names-invalid.s |
 | llvm/test/MC/RISCV/compress-rv32b.s |
 | llvm/test/MC/RISCV/hilo-constaddr.s |
 | llvm/test/MC/RISCV/machine-csr-names-invalid.s |
 | llvm/test/MC/RISCV/compress-rv32i.s |
 | llvm/test/MC/RISCV/compress-rv32d.s |
 | llvm/test/MC/RISCV/compress-rv32f.s |
 | llvm/test/MC/RISCV/rvv/snippet.s |
 | llvm/test/MC/RISCV/compress-rv64i.s |
 | llvm/test/MC/RISCV/option-rvc.s |
 | llvm/test/MC/RISCV/compress-rv64b.s |
 | llvm/test/MC/RISCV/option-invalid.s |
 | llvm/test/MC/RISCV/compress-cjal.s |
Commit
fdf10e6197d0bef20759a1457866c5e7daafd727
by craig.topper[RISCV] Use X0 as destination of inserted vsetvli when possible.
We aren't going to connect the result to anything so we might as well avoid allocating a register.
Reviewed By: frasercrmck, HsiangKai
Differential Revision: https://reviews.llvm.org/D102031
|
 | llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll |
 | llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll |
 | llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir |
 | llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir |
 | llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll |
 | llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll |
 | llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll |
 | llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/memory-args.ll |
 | llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll |
 | llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll |
 | llvm/test/CodeGen/RISCV/rvv/vand-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir |
 | llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll |
 | llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll |
 | llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp |
 | llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir |
 | llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll |
 | llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll |
 | llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll |
 | llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll |
 | llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vor-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll |
 | llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll |
 | llvm/test/CodeGen/RISCV/rvv/select-sra.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll |
 | llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll |
 | llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll |
 | llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll |
 | llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll |
Commit
6505c630407c5feec818f0bb1c284f9eeebf2071
by rahmanl[llvm-readobj] Optimize printing stack sizes to linear time.
Currently, each function name lookup is a linear iteration over all symbols defined in the object file which makes the total running time quadratic.
This patch optimizes the function name lookup by populating an **address to index** map upon the first function name lookup which is used to lookup each function name in O(1).
**impact**: For the clang binary built with `-fstack-size-section`, this improves the running time of `llvm-readobj --stack-size` from 7 minutes to 0.25 seconds.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D103072
|
 | llvm/tools/llvm-readobj/ELFDumper.cpp |
Commit
c4a41cd77c15c2905ac74beeec09f8343a65a549
by mvanottiRefactor mutation strategies into a standalone library
This change introduces libMutagen/libclang_rt.mutagen.a as a subset of libFuzzer/libclang_rt.fuzzer.a. This library contains only the fuzzing strategies used by libFuzzer to produce new test inputs from provided inputs, dictionaries, and SanitizerCoverage feedback.
Most of this change is simply moving sections of code to one side or the other of the library boundary. The only meaningful new code is:
* The Mutagen.h interface and its implementation in Mutagen.cpp. * The following methods in MutagenDispatcher.cpp: * UseCmp * UseMemmem * SetCustomMutator * SetCustomCrossOver * LateInitialize (similar to the MutationDispatcher's original constructor) * Mutate_AddWordFromTORC (uses callbacks instead of accessing TPC directly) * StartMutationSequence * MutationSequence * DictionaryEntrySequence * RecommendDictionary * RecommendDictionaryEntry * FuzzerMutate.cpp (which now justs sets callbacks and handles printing) * MutagenUnittest.cpp (which adds tests of Mutagen.h)
A note on performance: This change was tested with a 100 passes of test/fuzzer/LargeTest.cpp with 1000 runs per pass, both with and without the change. The running time distribution was qualitatively similar both with and without the change, and the average difference was within 30 microseconds (2.240 ms/run vs 2.212 ms/run, respectively). Both times were much higher than observed with the fully optimized system clang (~0.38 ms/run), most likely due to the combination of CMake "dev mode" settings (e.g. CMAKE_BUILD_TYPE="Debug", LLVM_ENABLE_LTO=OFF, etc.). The difference between the two versions built similarly seems to be "in the noise" and suggests no meaningful performance degradation.
Reviewed By: morehouse
Differential Revision: https://reviews.llvm.org/D102447
|
 | compiler-rt/lib/fuzzer/mutagen/MutagenSequence.h |
 | compiler-rt/lib/fuzzer/mutagen/build.sh |
 | compiler-rt/lib/fuzzer/tests/FuzzerUnittest.cpp |
 | compiler-rt/lib/fuzzer/CMakeLists.txt |
 | compiler-rt/lib/fuzzer/mutagen/MutagenUtil.h |
 | compiler-rt/lib/fuzzer/FuzzerTracePC.cpp |
 | compiler-rt/lib/fuzzer/build.sh |
 | compiler-rt/lib/fuzzer/mutagen/CMakeLists.txt |
 | compiler-rt/lib/fuzzer/FuzzerLoop.cpp |
 | compiler-rt/lib/fuzzer/mutagen/MutagenDispatcher.h |
 | compiler-rt/lib/fuzzer/FuzzerDictionary.h |
 | compiler-rt/lib/fuzzer/mutagen/MutagenUtilWindows.cpp |
 | compiler-rt/test/fuzzer/CMakeLists.txt |
 | compiler-rt/lib/fuzzer/mutagen/MutagenDispatcher.cpp |
 | compiler-rt/lib/fuzzer/FuzzerMutate.h |
 | compiler-rt/lib/fuzzer/mutagen/MutagenCrossOver.cpp |
 | compiler-rt/lib/fuzzer/mutagen/Mutagen.h |
 | compiler-rt/lib/fuzzer/FuzzerUtilFuchsia.cpp |
 | compiler-rt/lib/fuzzer/FuzzerMutate.cpp |
 | compiler-rt/lib/fuzzer/mutagen/MutagenDictionary.h |
 | compiler-rt/lib/fuzzer/FuzzerRandom.h |
 | compiler-rt/lib/fuzzer/FuzzerDefs.h |
 | compiler-rt/lib/fuzzer/FuzzerUtilPosix.cpp |
 | compiler-rt/lib/fuzzer/mutagen/Mutagen.cpp |
 | compiler-rt/lib/fuzzer/FuzzerDriver.cpp |
 | compiler-rt/lib/fuzzer/FuzzerInternal.h |
 | compiler-rt/lib/fuzzer/tests/CMakeLists.txt |
 | compiler-rt/lib/fuzzer/FuzzerCrossOver.cpp |
 | compiler-rt/lib/fuzzer/FuzzerUtil.h |
 | compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp |
 | compiler-rt/lib/fuzzer/FuzzerTracePC.h |
 | compiler-rt/lib/fuzzer/mutagen/MutagenUtilPosix.cpp |
 | compiler-rt/lib/fuzzer/tests/MutagenUnittest.cpp |
Commit
367cb9fbd651836488580862d8b020fe294d37d6
by zoecarver[libcxx][docs] Take mutex for common_iterator, common_view, and empty_view.
|
 | libcxx/docs/OneRangesProposalStatus.csv |
Commit
5852582532b3eb3ea8da51a1e272d8d017bd36c9
by i[AArch64] Support llvm-mc/llvm-objdump -M no-aliases
This enables the no-aliases forms of many instructions.
Depends on D103004
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D103005
|
 | llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h |
 | llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp |
 | llvm/test/MC/AArch64/alias-addsubimm.s |
Commit
5f8810d7b463e085ab24d5443cde7143cae08ddc
by naromero[flang][docs] Initial documentation for the Fortran LLVM Test Suite.
Describes how to run the Fortran LLVM Test Suite, specifically the external SPEC CPU 2017 Fortran tests.
Reviewed By: rovka
Differential Revision: https://reviews.llvm.org/D102877
|
 | flang/docs/FortranLLVMTestSuite.md |
 | flang/docs/index.md |
 | llvm/docs/TestSuiteGuide.md |
Commit
52123c96c016143ebfff6de76fe83cebd6c1d726
by zoecarver[libcxx][nfc] Fix the ASAN bots: update expected.pass.cpp.
Ensures that `get_return_object`'s return type is the same as the return type for the function calling `co_return`. Otherwise, we try to construct an object, then free it, then return it.
Differential Revision: https://reviews.llvm.org/D103196
|
 | libcxx/test/std/experimental/language.support/support.coroutines/end.to.end/expected.pass.cpp |
Commit
1032886a41c6ef386e5280344958dbdba337779f
by mascasa[libFuzzer] Add missing FuzzerBuiltinsMsvc.h include.
Should fix the Windows build.
|
 | compiler-rt/lib/fuzzer/mutagen/MutagenDispatcher.cpp |
Commit
0283abee5c87e86552b456a34d01311b66c37207
by a20012251[lldb] Fix gnu_libstdcpp's update methods
The variable.rst documentation says:
``` If it returns a value, and that value is True, LLDB will be allowed to cache the children and the children count it previously obtained, and will not return to the provider class to ask. If nothing, None, or anything other than True is returned, LLDB will discard the cached information and ask. Regardless, whenever necessary LLDB will call update. ```
However, several update methods in gnu_libstdcpp.py were returning True, which made lldb unaware of any changes in the corresponding objects. This problem was visible by lldb-vscode in the following way:
- If a breakpoint is hit and there's a vector with the contents {1, 2}, it'll be displayed correctly. - Then the user steps and the next stop contains the vector modified. The program changed it to {1, 2, 3} - frame var then displays {1, 2} incorrectly, due to the caching caused by the update method
It's worth mentioning that none of libcxx.py'd update methods return True. Same for LibCxxVector.cpp, which returns false.
Added a very simple test that fails without this fix.
Differential Revision: https://reviews.llvm.org/D103209
|
 | lldb/test/API/tools/lldb-vscode/evaluate/TestVSCode_evaluate.py |
 | lldb/examples/synthetic/gnu_libstdcpp.py |
 | lldb/test/API/tools/lldb-vscode/evaluate/main.cpp |
Commit
97f15eda4f26eb18c914884ce808b4e366e29c34
by ajcbik[mlir][python] Provide "all passes" registration module in Python
Currently, passes are registered on a per-dialect basis, which provides the smallest footprint obviously. But for prototyping and experimentation, a convenience "all passes" module is provided, which registers all known MLIR passes in one run.
Usage in Python:
import mlir.all_passes_registration
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D103130
|
 | mlir/lib/Bindings/Python/AllPassesRegistration.cpp |
 | mlir/python/mlir/all_passes_registration/__init__.py |
 | mlir/include/mlir-c/Registration.h |
 | mlir/lib/CAPI/Registration/Registration.cpp |
 | mlir/lib/Bindings/Python/CMakeLists.txt |
Commit
fd0a2f75ff4f25a4759afeb72b42ba1b6ccea93f
by mascasaRevert "Refactor mutation strategies into a standalone library"
This reverts commit c4a41cd77c15c2905ac74beeec09f8343a65a549 due to buildbot failure.
|
 | compiler-rt/lib/fuzzer/FuzzerUtilPosix.cpp |
 | compiler-rt/lib/fuzzer/tests/CMakeLists.txt |
 | compiler-rt/lib/fuzzer/mutagen/MutagenCrossOver.cpp |
 | compiler-rt/lib/fuzzer/mutagen/MutagenDispatcher.h |
 | compiler-rt/lib/fuzzer/FuzzerCrossOver.cpp |
 | compiler-rt/lib/fuzzer/FuzzerUtil.h |
 | compiler-rt/lib/fuzzer/mutagen/build.sh |
 | compiler-rt/test/fuzzer/CMakeLists.txt |
 | compiler-rt/lib/fuzzer/FuzzerUtilWindows.cpp |
 | compiler-rt/lib/fuzzer/build.sh |
 | compiler-rt/lib/fuzzer/FuzzerUtilFuchsia.cpp |
 | compiler-rt/lib/fuzzer/tests/FuzzerUnittest.cpp |
 | compiler-rt/lib/fuzzer/mutagen/MutagenSequence.h |
 | compiler-rt/lib/fuzzer/mutagen/MutagenUtilPosix.cpp |
 | compiler-rt/lib/fuzzer/mutagen/Mutagen.h |
 | compiler-rt/lib/fuzzer/mutagen/MutagenUtilWindows.cpp |
 | compiler-rt/lib/fuzzer/FuzzerDefs.h |
 | compiler-rt/lib/fuzzer/mutagen/CMakeLists.txt |
 | compiler-rt/lib/fuzzer/FuzzerDriver.cpp |
 | compiler-rt/lib/fuzzer/FuzzerMutate.cpp |
 | compiler-rt/lib/fuzzer/FuzzerLoop.cpp |
 | compiler-rt/lib/fuzzer/CMakeLists.txt |
 | compiler-rt/lib/fuzzer/mutagen/Mutagen.cpp |
 | compiler-rt/lib/fuzzer/tests/MutagenUnittest.cpp |
 | compiler-rt/lib/fuzzer/FuzzerTracePC.cpp |
 | compiler-rt/lib/fuzzer/mutagen/MutagenDispatcher.cpp |
 | compiler-rt/lib/fuzzer/FuzzerDictionary.h |
 | compiler-rt/lib/fuzzer/mutagen/MutagenUtil.h |
 | compiler-rt/lib/fuzzer/mutagen/MutagenDictionary.h |
 | compiler-rt/lib/fuzzer/FuzzerMutate.h |
 | compiler-rt/lib/fuzzer/FuzzerRandom.h |
 | compiler-rt/lib/fuzzer/FuzzerTracePC.h |
 | compiler-rt/lib/fuzzer/FuzzerInternal.h |
Commit
94d67b51dd025d152e1ef7dd6a14dc90f5ddcf36
by thomasraoux[mlir] Add n-D vector lowering to LLVM for cast ops
The casting ops (sitofp, uitofp, fptosi, fptoui) lowering currently does not handle n-D vectors. This patch fixes that.
Differential Revision: https://reviews.llvm.org/D103207
|
 | mlir/test/Conversion/StandardToLLVM/convert-nd-vector-to-llvmir.mlir |
 | mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp |
Commit
2fe987e6bacea8884a397041c13a38e8ba97c2d6
by 31459023+hctim[scudo] Build scudo_standalone on Android and Fuchsia.
This should be fine now, and is necessary for D102543.
Reviewed By: cryptoad
Differential Revision: https://reviews.llvm.org/D103200
|
 | compiler-rt/cmake/config-ix.cmake |
Commit
79c09d5ee1e97fc132b1f2087878d5c5d7a77888
by listmail[tests] Add some basic coverage of multiple exit unrolling
|
 | llvm/test/Transforms/LoopUnroll/multiple-exits.ll |
Commit
002f5e158d08929ca266be0fb8275052cc7aaed2
by kparzysz[Hexagon] Restore handling of expanding shuffles
Fixed bugs, added testcases. The byte-unpack is actually recognized by the DAG combiner, but the halfword-unpack it not.
|
 | llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-128b.ll |
 | llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp |
 | llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-64b.ll |
Commit
b5c3f17e70e70692e805c00d906a3a3d6678f093
by frank.laub[MLIR] Add support for empty IVs to affine.parallel
Allow support for specifying empty IVs in an `affine.parallel`.
For example:
``` affine.parallel () = () to () { affine.yield } ```
Reviewed By: bondhugula, jbruestle
Differential Revision: https://reviews.llvm.org/D102895
|
 | mlir/include/mlir/Dialect/Affine/IR/AffineOps.td |
 | mlir/test/Dialect/Affine/ops.mlir |
 | mlir/lib/Dialect/Affine/IR/AffineOps.cpp |
Commit
2dba40561a28c56b8e96149642ca3cad3b3c4178
by 31459023+hctimRevert "[scudo] Build scudo_standalone on Android and Fuchsia."
This reverts commit 2fe987e6bacea8884a397041c13a38e8ba97c2d6.
Broke the Android buildbots. Turns out a couple more tweaks are necessary to turn them back on.
|
 | compiler-rt/cmake/config-ix.cmake |
Commit
74edfb28053dac26d82d1372123be03db630ef62
by Amara Emerson[AArch64][GlobalISel] Legalize non-power-of-2 vector elements for G_STORE.
The rules were already there, it just needed re-ordering so the odd case didn't bail out too early.
|
 | llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll |
 | llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir |
 | llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp |
Commit
caae570978c490a137921b9516162a382831209e
by tmsriramEmit correct location lists with basic block sections.
This patch addresses multiple things:
1) It ensures that const_value is emitted when possible with basic block sections. 2) It emits location lists such that the labels are always within the section boundary. 3) It fixes a bug when the parameter is first used in a non-entry block which is in a different section from the entry block.
Differential Revision: https://reviews.llvm.org/D85085
|
 | llvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-4.ll |
 | llvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-1.ll |
 | llvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-2.ll |
 | llvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-5.ll |
 | llvm/test/DebugInfo/X86/basic-block-sections-debug-loc-const-value-2.ll |
 | llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp |
 | llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp |
 | llvm/test/DebugInfo/X86/basic-block-sections-debug-loc.ll |
 | llvm/test/DebugInfo/X86/basic-block-sections-debug-loc-const-value-1.ll |
 | llvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-3.ll |
 | llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp |
 | llvm/test/DebugInfo/X86/basic-block-sections-debug-loc-split-range.ll |
 | llvm/test/DebugInfo/X86/basic-block-sections_1.ll |
Commit
324af79dbc606678c4067411aca2a4ff2af831d7
by Jessica Paquette[GlobalISel] Don't emit lost debug location remarks when legalizing tail calls
There were a bunch of lost debug location remarks that show up when legalizing tail calls on AArch64.
This would happen because we drop the return in the block where we emit the tail call. So, we end up dropping the debug location, which makes the LostDebugLocObserver report a missing debug location.
Although it's *true* that we lose these debug locations, this isn't a particularly useful remark. We expect to drop these debug locations when emitting tail calls. Suppressing remarks in this case is preferable, since the amount of noise could hide actual debug location related bugs.
To do this, I just plumbed the LostDebugLocObserver through the relevant LegalizerHelper functions. This is the only case I can think of where we need the LostDebugLocObserver in the LegalizerHelper. So, rather than storing it in the LegalizerHelper proper and mucking around with the constructors, I figured it'd be cleanest to take the simplest path for now.
This clears up ~20 noisy lost debug location remarks on CTMark in AArch64 at -Os.
Differential Revision: https://reviews.llvm.org/D103128
|
 | llvm/test/CodeGen/AArch64/GlobalISel/debug-loc-legalize-tail-call.mir |
 | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp |
 | llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h |
 | llvm/lib/CodeGen/GlobalISel/Legalizer.cpp |
Commit
95ce0def7c983ae8c4c609e1688c55387e104419
by Lang Hames[ORC-RT] Add endianness support to the ORC runtime.
endian.h is a cut-down version of llvm/Support/SwapByteOrder.h. It will be used in upcoming serialization utilities for the ORC runtime.
|
 | compiler-rt/lib/orc/endian.h |
 | compiler-rt/lib/orc/unittests/CMakeLists.txt |
 | compiler-rt/lib/orc/unittests/endian_test.cpp |
 | compiler-rt/lib/orc/CMakeLists.txt |
Commit
08d31ff4f45f795afb6648bc00257d60ff2f8204
by Jessica PaquetteFix unit test after 324af79dbc6066
Needed to add in an extra parameter to calls to `libcall`.
|
 | llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp |
Commit
a4b61c82cf1a45c172af2e0242f5019281de14f8
by zahira.ammarguellatThe compiler is crashing when compiling a coroutine intrinsic without the use of the option fcoroutines-ts. This is a patch to fix this.
Fix for https://bugs.llvm.org/show_bug.cgi?id=50406
|
 | clang/include/clang/Basic/Builtins.h |
 | clang/include/clang/Basic/Builtins.def |
 | clang/test/SemaCXX/coroutine-builtins.cpp |
 | clang/lib/Basic/Builtins.cpp |
Commit
4d26f41f76c4f92023c02ec96ffbd02a6eb2c46d
by yrouban[RS4GC] Introduce intrinsics to get base ptr and offset
There can be a need for some optimizations to get (base, offset) for any GC pointer. The base can be calculated by generating needed instructions as it is done by the RewriteStatepointsForGC::findBasePointer() function. The offset can be calculated in the same way. Though to not expose the base calculation and to make the offset calculation as simple as ptrtoint(derived_ptr) - ptrtoint(base_ptr), which is illegal outside RS4GC, this patch introduces 2 intrinsics:
@llvm.experimental.gc.get.pointer.base(%derived_ptr) @llvm.experimental.gc.get.pointer.offset(%derived_ptr)
These intrinsics are inlined by RS4GC along with generation of statepoint sequences.
With these new intrinsics the GC parseable lowering for atomic memcpy intrinsics (6ec2c5e402a724ba99bce82a9cac7a3006d660f4) could be implemented as a separate pass.
Reviewed By: reames Differential Revision: https://reviews.llvm.org/D100445
|
 | llvm/docs/Statepoints.rst |
 | llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp |
 | llvm/lib/IR/IRBuilder.cpp |
 | llvm/docs/LangRef.rst |
 | llvm/test/Transforms/RewriteStatepointsForGC/intrinsics.ll |
 | llvm/include/llvm/IR/IRBuilder.h |
 | llvm/lib/IR/Verifier.cpp |
 | llvm/include/llvm/IR/Intrinsics.td |
Commit
0ce58c52d50bd2edd09df7c7ef3dd4dc85b05992
by haowei[Fuchsia][CMake] Add missing include path.
This patch adds include path for missing header files from "sync". This patch also fixes the build failures caused by scudo.
Differential Revision: https://reviews.llvm.org/D103218
|
 | clang/cmake/caches/Fuchsia-stage2.cmake |
Commit
8d25762720660aba3344752e577ae7017e6125c2
by joker.ephFix non-global-value-max-name-size not considered by LLParser
`non-global-value-max-name-size` is used by `Value` to cap the length of local value name. However, this flag is not considered by `LLParser`, which leads to unexpected `use of undefined value error`. The fix is to move the responsibility of capping the length to `ValueSymbolTable`.
The test is the one provided by [[ https://bugs.llvm.org/show_bug.cgi?id=45899 | Mikael in the bug report ]].
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D102707
|
 | llvm/include/llvm/IR/ValueSymbolTable.h |
 | llvm/test/Assembler/non-global-value-max-name-size.ll |
 | llvm/lib/IR/Module.cpp |
 | llvm/lib/IR/ValueSymbolTable.cpp |
 | llvm/lib/IR/Function.cpp |
 | llvm/lib/IR/Value.cpp |
Commit
857fa7b7b1872a4a9b4072b6e83c85524c7229af
by cjdb[libcxx][iterator] adds `std::ranges::next`
Implements part of P0896 'The One Ranges Proposal'. Implements [range.iter.op.next].
Depends on D101922.
Differential Revision: https://reviews.llvm.org/D102563
|
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_count_sentinel.pass.cpp |
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_count.pass.cpp |
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/special_function.compile.pass.cpp |
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/constraints.verify.cpp |
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator.pass.cpp |
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/check_round_trip.h |
 | libcxx/include/__iterator/next.h |
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/iterator_sentinel.pass.cpp |
 | libcxx/include/CMakeLists.txt |
 | libcxx/include/iterator |
Commit
0dc7fd1bc1670e9f7e58b08b51b478a6334c8b01
by cjdb[libcxx][iterator] adds `std::ranges::prev`
Implements part of P0896 'The One Ranges Proposal'. Implements [range.iter.op.prev].
Depends on D102563.
Differential Revision: https://reviews.llvm.org/D102564
|
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator_count_sentinel.pass.cpp |
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/special_function.compile.pass.cpp |
 | libcxx/include/iterator |
 | libcxx/include/__iterator/prev.h |
 | libcxx/include/CMakeLists.txt |
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/check_round_trip.h |
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/constraints.verify.cpp |
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator.pass.cpp |
 | libcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.prev/iterator_count.pass.cpp |
Commit
77274258e2d4c2b253778c316bb39a6f3c12eb6b
by llvmgnsyncbot[gn build] Port 0dc7fd1bc167
|
 | llvm/utils/gn/secondary/libcxx/include/BUILD.gn |
Commit
cc3db8dbdf517cf96264f8f63a828657775062e5
by llvmgnsyncbot[gn build] Port 857fa7b7b187
|
 | llvm/utils/gn/secondary/libcxx/include/BUILD.gn |
Commit
d82f2a123f9c443911fc40009d2017915b850758
by esme.yi[llvm-objdump] Print the DEBUG type under `--section-headers`.
Summary: Under the option --section-headers, we can only print the section types of TEXT, DATA, and BSS for now. This patch adds the DEBUG type.
Reviewed By: jhenderson, Higuoxing
Differential Revision: https://reviews.llvm.org/D102603
|
 | llvm/tools/llvm-objdump/llvm-objdump.cpp |
 | llvm/test/tools/llvm-objdump/section-headers.test |