Changes

Summary

  1. Removed abandoned lldb-sphinx-docs builder. (details)
  2. [sanitizer] Switch to patched QEMU (details)
Commit f395d4d0c7d3e9f063d6becd5933d77eb32c1089 by gkistanova
Removed abandoned lldb-sphinx-docs builder.
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)
Commit 6e3e7926bcf8e4d83d83d9072990ddc33e02bb11 by Vitaly Buka
[sanitizer] Switch to patched QEMU
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh (diff)

Summary

  1. [NFCI][LoopDeletion] Only query SCEV about loop successor if another successor is also in loop (details)
  2. [NFC] Formatting fix (details)
  3. [NFCI] Lazily evaluate SCEVs of PHIs (details)
  4. [mlir] Add a pass to distribute linalg::TiledLoopOp. (details)
  5. [docs] llvm-objdump: Mention -M no-aliases is supported on AArch64 (details)
  6. [mlir] Add TestLinalgDistribution.cpp to cmake build. (details)
  7. [GlobalISel] Implement splitting of G_SHUFFLE_VECTOR. (details)
  8. [NFC] Reuse existing variables instead of re-requesting successors (details)
  9. [NFCI][LoopDeletion] Do not call complex analysis for known non-zero BTC (details)
  10. [mlir] Support dialect-wide canonicalization pattern registration (details)
  11. [AMDGPU][GlobalISel] Allow amdgpu_gfx calling conv (details)
  12. [SelectionDAG][RISCV] Don't unroll 0/1-type bool VSELECTs (details)
  13. [Matrix] Include matrix pipeline for new PM in new-pm-defaults.ll. (details)
  14. [lit][test] Improve testing of use_llvm_tool (details)
  15. Add triples to a bunch of x86-specific tests that currently fail on PPC (details)
  16. [clang-format] [NFC] realign documentation in Format.h... (details)
  17. [ARM] Extra test for reverted WLS memset. NFC (details)
  18. [OpenMP]Add support for workshare loop modifier in lowering (details)
  19. [AMDGPU][Libomptarget][NFC] Remove atmi_mem_place_t (details)
  20. Revert "[OpenMP]Add support for workshare loop modifier in lowering" (details)
  21. Add --quiet option to llvm-gsymutil to suppress output of warnings. (details)
  22. [mlir][Linalg] Add comprehensive bufferization support for subtensor (5/n) (details)
  23. Add support for #elifdef and #elifndef (details)
  24. [VPlan] Do not sink uniform recipes in sinkScalarOperands. (details)
  25. [RISCV] Allow passing fixed-length vectors via the stack (details)
  26. [DAGCombine][RISCV] Don't try to trunc-store combined vector stores (details)
  27. Fix -Wswitch warning; NFC (details)
  28. AMDGPU/GlobalISel: Remove redundant parameter from function (details)
  29. AMDGPU/GlobalISel: Lower constant-32-bit zextload/sextload consistently (details)
  30. Speculatively fix a -Woverloaded-virtual diagnostic; NFC (details)
  31. Speculatively fix this harder and with improved spelling capabilities. (details)
  32. Reimplement __builtin_unique_stable_name- (details)
  33. Reuse temporary files for print-changed=diff (details)
  34. Correct the 'KEYALL' mask. (details)
  35. Hopefully fix the Clang sphinx doc build. (details)
  36. [OpenMP]Add support for workshare loop modifier in lowering (details)
  37. [VP][SelectionDAG] Add a target-configurable EVL operand type (details)
  38. Disable misc-no-recursion checking in Clang (details)
  39. VirtRegMap: Preserve LiveDebugVariables (details)
  40. [Flang][Openmp] Fortran specific semantic checks for Allocate directive (details)
  41. [OpenCL][NFC] Fix typos in test (details)
  42. [X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads (details)
  43. [CostModel][X86] AVX512 truncation ops are slower than cost models indicate. (details)
  44. AMDGPU/GlobalISel: Fix broken test run line (details)
  45. AMDGPU/GlobalISel: Use IncomingValueAssigner for implicit return (details)
  46. [libc++] Deprecate std::iterator and remove it as a base class (details)
  47. [libc++] NFC: Parenthesize expression to satisfy GCC 11 (details)
  48. Revert "Emit correct location lists with basic block sections." (details)
  49. Thread safety analysis: Factor out function for merging locks (NFC) (details)
  50. Thread safety analysis: Allow exlusive/shared joins for managed and asserted capabilities (details)
  51. [AIX] Add -lc++abi and -lunwind for linking (details)
  52. GlobalISel: Do not change register types in lowerLoad (details)
  53. [RISCV] Add a test case showing incorrect call-conv lowering (details)
  54. [HIP] Check compatibility of -fgpu-sanitize with offload arch (details)
  55. [mlir][gpu] Relax restriction on MMA store op to allow chain of mma ops. (details)
  56. [SPE] Disable strict-fp for SPE by default (details)
  57. [LoopUnrollAndJam] Change LoopUnrollAndJamPass to LoopNest pass (details)
  58. [mlir] Async reference counting for block successors with divergent reference counted liveness (details)
  59. [Clang] Enable __has_feature(coverage_sanitizer) (details)
  60. [mlir] Add error state and error propagation to async runtime values (details)
  61. [X86] Pre-commit tests for D103192. NFC (details)
  62. [X86] Fold (shift undef, X)->0 for vector shifts by immediate. (details)
  63. [mlir] Async: Add error propagation support to async groups (details)
  64. [mlir][NFC] Don't outline kernel in MMA integration tests (details)
  65. [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. (details)
  66. [CostModel][X86] Improve accuracy of sext/zext to 256-bit vector costs on AVX1 targets (details)
  67. [NFC][X86][Codegen] Re-autogenerate check lines in a few tests to remove noise from future changes (details)
  68. Revert "[libc++] NFC: Parenthesize expression to satisfy GCC 11" (details)
  69. [NFC][scudo] Rename internal function (details)
  70. MC: mark `dump` with `LLVM_DUMP_METHOD` (details)
  71. [mlir] AsyncRefCounting: check that LivenessBlockInfo is not nullptr (details)
  72. [mlir] Update cmake variable post D102976 (details)
  73. [NFC][scudo] Check zeros on smaller allocations (details)
  74. [libc++] NFC: Refactor raw_storage_iterator test to use UNSUPPORTED markup (details)
  75. [RISCV] Add a test showing missed opportunity to avoid a vsetvli in a loop. (details)
  76. [lldb][intel-pt] Remove old plugin (details)
  77. [mlir:Async] Convert assertions to async errors only inside async functions (details)
  78. [analyzer] RetainCountChecker: Disable reference counting for OSMetaClass. (details)
  79. Support stripping indirectly referenced DILocations from !llvm.loop metadata (details)
  80. [NFC][X86][Codegen] vector-interleaved-store-i16-stride-5.ll: precisely match the actual IR (details)
  81. [x86] add tests for extend of vector compare; NFC (details)
  82. Replace 'magic static' with a member variable for SCYL kernel names (details)
  83. [libc++] NFC: Make it easier for vendors to extend the run-buildbot script (details)
  84. [clang] [MinGW] Don't mark emutls variables as DSO local (details)
  85. [libcxx] [test] Convert an XFAIL LIBCXX-WINDOWS-FIXME into UNSUPPORTED with explanation (details)
  86. [mlir] Add support for querying the ModRef behavior from the AliasAnalysis class (details)
  87. [RISCV] Fix typo, use addImm instead of addReg. (details)
  88. [PDB] Enable parallel ghash type merging by default (details)
  89. [PowerPC] Added multiple PowerPC builtins (details)
  90. [MCA] Refactor the InOrderIssueStage stage. NFCI (details)
  91. [mlir-lsp-server] Add support for processing split files (details)
  92. [sanitizer] Android ELF TLS is supported from Q (API 29) (details)
  93. [mlir][capi] fix build issue with "all passes" registration (details)
  94. [NFC][X86][Codegen] Re-autogenerate a few tests to reduce noise in future changes (details)
  95. [SanCov] Properly set ABI parameter attributes (details)
  96. [RISCV] Teach VSETVLI insertion to look through PHIs to prove we don't need to insert a vsetvli. (details)
  97. [ConstFold] Simplify a load's GEP operand through local aliases (details)
  98. [MCA] Minor changes to the InOrderIssueStage. NFC (details)
  99. [NFC][libObject] clang-format Archive{.h,.cpp} (details)
  100. Fix comment to reflect what the method is doing (NFC) (details)
  101. [dfsan] Add a flag about whether to propagate offset labels at gep (details)
  102. [AIX] Enable stackprotect feature (details)
  103. [PDB] Fix ubsan complaint about memcpy from null pointer (details)
  104. [clang-cl] Bump default -fms-compatibility-version to 19.14 (details)
  105. Pass -gcodeview-ghash when using clang-cl and lld-link (details)
  106. Revert "[NFCI] Lazily evaluate SCEVs of PHIs" (details)
  107. [AArch64][GlobalISel] Legalize oversize G_EXTRACT_VECTOR_ELT sources. (details)
Commit b0b2bf3b5da950679db1431aae431a6dedea2245 by mkazantsev
[NFCI][LoopDeletion] Only query SCEV about loop successor if another successor is also in loop
The file was modifiedllvm/lib/Transforms/Scalar/LoopDeletion.cpp
Commit 59d938e649e62db0cef4903d495e838fbc6a6eb8 by mkazantsev
[NFC] Formatting fix
The file was modifiedllvm/lib/Transforms/Scalar/LoopDeletion.cpp
Commit 51d334a845a082338735b0fdfc620a4b15fa26fe by mkazantsev
[NFCI] Lazily evaluate SCEVs of PHIs

Eager evaluation has cost of compile time. Only query them if they are
required for proving predicates.
The file was modifiedllvm/lib/Transforms/Scalar/LoopDeletion.cpp
Commit 281ee4291110af5d1337d1da819a284eecf368ec by pifon
[mlir] Add a pass to distribute linalg::TiledLoopOp.

Differential Revision: https://reviews.llvm.org/D103194
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
The file was addedmlir/lib/Dialect/Linalg/Transforms/Distribution.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was addedmlir/test/Dialect/Linalg/distribute-tiled-loop.mlir
The file was modifiedmlir/tools/mlir-opt/mlir-opt.cpp
The file was addedmlir/test/lib/Dialect/Linalg/TestLinalgDistribution.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
Commit 3f85e124f6b790134c8074edef4e716c604c2b14 by i
[docs] llvm-objdump: Mention -M no-aliases is supported on AArch64
The file was modifiedllvm/docs/CommandGuide/llvm-objdump.rst
Commit 62686a47a448d4795720adf8cadc9c745192f8b6 by pifon
[mlir] Add TestLinalgDistribution.cpp to cmake build.
The file was modifiedmlir/test/lib/Dialect/Linalg/CMakeLists.txt
Commit 9f39ba13b59632eaa718068a981df0a00c9b9474 by Amara Emerson
[GlobalISel] Implement splitting of G_SHUFFLE_VECTOR.

Thhis is a port from the DAG legalization. We're still missing some of the
canonicalizations of shuffles but it's a start.

Differential Revision: https://reviews.llvm.org/D102828
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit c467585682dcdda75e645ef3ab47c8b48440db12 by mkazantsev
[NFC] Reuse existing variables instead of re-requesting successors
The file was modifiedllvm/lib/Transforms/Scalar/LoopDeletion.cpp
Commit 7d418dadf6b1e6fd9bcccf7c5b5e1db74992ee70 by mkazantsev
[NFCI][LoopDeletion] Do not call complex analysis for known non-zero BTC
The file was modifiedllvm/lib/Transforms/Scalar/LoopDeletion.cpp
Commit 108ca7a7e73ca6d5f4c17a8291d0e94cd9f740d3 by springerm
[mlir] Support dialect-wide canonicalization pattern registration

* Add `hasCanonicalizer` option to Dialect.
* Initialize canonicalizer with dialect-wide canonicalization patterns.
* Add test case to TestDialect.

Dialect-wide canonicalization patterns are useful if a canonicalization pattern does not conceptually associate with any single operation, i.e., it should not be registered as part of an operation's `getCanonicalizationPatterns` function. E.g., this is the case for canonicalization patterns that match an op interface.

Differential Revision: https://reviews.llvm.org/D103226
The file was modifiedmlir/test/Transforms/test-canonicalize.mlir
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td
The file was modifiedmlir/lib/Transforms/Canonicalizer.cpp
The file was modifiedmlir/include/mlir/TableGen/Dialect.h
The file was modifiedmlir/include/mlir/IR/Dialect.h
The file was modifiedmlir/lib/TableGen/Dialect.cpp
The file was modifiedmlir/tools/mlir-tblgen/DialectGen.cpp
The file was modifiedmlir/test/lib/Dialect/Test/TestDialect.cpp
The file was modifiedmlir/include/mlir/IR/OpBase.td
Commit 0bb60dbe34e4a934e47a0493832f3384fb09b7db by sebastian.neubauer
[AMDGPU][GlobalISel] Allow amdgpu_gfx calling conv

Calling functions from shaders already works with the SelectionDAG.

Differential Revision: https://reviews.llvm.org/D103183
The file was modifiedllvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
Commit 772b58a641affcd786e3062250a0f51acb8b1553 by fraser
[SelectionDAG][RISCV] Don't unroll 0/1-type bool VSELECTs

This patch extends the cases in which the legalizer is able to express
VSELECT in terms of XOR/AND/OR. When dealing with a VSELECT between
boolean vector types, the mask itself is an all-ones or all-ones value
of the operand type, so a 0/1 boolean type behaves identically to a 0/-1
type.

This greatly helps RISC-V which relies on expansion for these nodes. It
also allows scalable-vector bool VSELECTs to use the default expansion,
where before it would crash in SelectionDAG::UnrollVectorOp.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103147
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/vselect-mask.ll
Commit 9a4506e7591fc5aaa9b69d35857908cadb4f5743 by flo
[Matrix] Include matrix pipeline for new PM in new-pm-defaults.ll.

-enable-matrix just adds a single pass, so it's easier to just check in
new-pm-default.ll rather than duplicating the full checks for -O3 with
the new pass manager.

Suggested post-commit by @aeubanks.
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedllvm/test/Other/opt-O3-pipeline-enable-matrix.ll
Commit 2ae58431873d449f63fa6dd20dbd280fa43b3ac2 by james.henderson
[lit][test] Improve testing of use_llvm_tool

Reviewed by: MaskRay

Differential Revision: https://reviews.llvm.org/D103154
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/path/case4.exe
The file was removedllvm/utils/lit/tests/Inputs/use-tool-search-env/lit.cfg
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/build/case6.exe
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/build/case7
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/env-case1
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/path/case6
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/path/case7.exe
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool-required/true.txt
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool-required/found.exe
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/path/case6.exe
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/build/case2
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/build/case7.exe
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/build/case6
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool-required/found
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool-required/lit.cfg
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/true.txt
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/path/case4
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/path/case5
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/path/case7
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/lit.cfg
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/build/case3.exe
The file was removedllvm/utils/lit/tests/Inputs/use-tool-search-env/test.tool
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/env-case6
The file was removedllvm/utils/lit/tests/use-tool-search-env.py
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/build/case3
The file was removedllvm/utils/lit/tests/Inputs/use-tool-search-env/true.txt
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/build/case2.exe
The file was addedllvm/utils/lit/tests/use-llvm-tool.py
The file was addedllvm/utils/lit/tests/Inputs/use-llvm-tool/path/case5.exe
Commit 1546c52d971292ed4145b6d41aaca0d02229ebff by benny.kra
Add triples to a bunch of x86-specific tests that currently fail on PPC
The file was modifiedllvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-1.ll
The file was modifiedllvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-2.ll
The file was modifiedllvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-3.ll
The file was modifiedllvm/test/DebugInfo/X86/basic-block-sections-debug-loc-split-range.ll
Commit 7faffdeb48d3d81ba8fc1353f1a9a563a25adf6d by bjoern
[clang-format] [NFC] realign documentation in Format.h...

... and ClanfFormatStyleOptions.rst for EmptyLineAfterAccessModifier

Differential-Revision: https://reviews.llvm.org/D102989
The file was modifiedclang/include/clang/Format/Format.h
Commit 1d5b976b778327901bfe35c164590f80169e5170 by david.green
[ARM] Extra test for reverted WLS memset. NFC
The file was modifiedllvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
Commit ea4c5fb04c6d9618d451fb2d2c360dc95c6d9131 by mats.petersson
[OpenMP]Add support for workshare loop modifier in lowering

When lowering the dynamic, guided, auto and runtime types of scheduling,
there is an optional monotonic or non-monotonic modifier. This patch
adds support in the OMP IR Builder to pass this down to the runtime
functions.

Also implements tests for the variants.

Differential Revision: https://reviews.llvm.org/D102008
The file was modifiedllvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPConstants.h
The file was modifiedllvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Commit 8b79dfb302acbcaf2b103759904146161a3e198d by Pushpinder.Singh
[AMDGPU][Libomptarget][NFC] Remove atmi_mem_place_t

This struct was used to specify the device on which memory was
being allocated/free in atmi_malloc/free. It has now been replaced
with int DeviceId.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D103239
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/atmi_interop_hsa.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/data.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/internal.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/atmi.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/atmi_runtime.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/system.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/rt.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/atmi_interop_hsa.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/atmi.cpp
Commit 86627be23312bd227e5afa88c206771a9aaf6589 by mats.petersson
Revert "[OpenMP]Add support for workshare loop modifier in lowering"

This reverts commit ea4c5fb04c6d9618d451fb2d2c360dc95c6d9131.
The file was modifiedllvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
The file was modifiedllvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPConstants.h
Commit 5f2d4b23b4c2229e27f1ee9c14c8bc82631b4861 by simon.giesecke
Add --quiet option to llvm-gsymutil to suppress output of warnings.

Differential Revision: https://reviews.llvm.org/D102829
The file was modifiedllvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
The file was modifiedllvm/lib/DebugInfo/GSYM/GsymCreator.cpp
The file was modifiedllvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
The file was modifiedllvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp
The file was modifiedllvm/test/tools/llvm-gsymutil/cmdline.test
Commit ce4f99e7f272d481d0689c551d9818019992c841 by nicolas.vasilache
[mlir][Linalg] Add comprehensive bufferization support for subtensor (5/n)

This revision refactors and simplifies the pattern detection logic: thanks to SSA value properties, we can actually look at all the uses of a given value and avoid having to pattern-match specific chains of operations.

A bufferization pattern for subtensor is added and specific inplaceability analysis is implemented for the simple case of subtensor. More advanced use cases will follow.

Differential revision: https://reviews.llvm.org/D102512
The file was modifiedmlir/lib/Interfaces/ViewLikeInterface.cpp
The file was modifiedmlir/include/mlir/Interfaces/ViewLikeInterface.td
The file was modifiedmlir/test/Dialect/Linalg/comprehensive-func-bufferize.mlir
The file was modifiedmlir/include/mlir/Interfaces/ViewLikeInterface.h
The file was modifiedmlir/include/mlir/Dialect/Linalg/Passes.td
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/ComprehensiveBufferize.cpp
Commit 8edd3464afbff65d7d5945b3a8b20009d6ff5deb by aaron
Add support for #elifdef and #elifndef

WG14 adopted N2645 and WG21 EWG has accepted P2334 in principle (still
subject to full EWG vote + CWG review + plenary vote), which add
support for #elifdef as shorthand for #elif defined and #elifndef as
shorthand for #elif !defined. This patch adds support for the new
preprocessor directives.
The file was modifiedclang/include/clang/Lex/PreprocessingRecord.h
The file was modifiedclang/lib/Basic/IdentifierTable.cpp
The file was modifiedclang/test/Preprocessor/macro_misc.c
The file was modifiedclang/test/Preprocessor/if_warning.c
The file was modifiedclang/lib/Lex/Lexer.cpp
The file was modifiedclang/lib/Lex/PPDirectives.cpp
The file was modifiedclang/lib/Lex/PreprocessingRecord.cpp
The file was modifiedclang/lib/Lex/Preprocessor.cpp
The file was modifiedclang/include/clang/Lex/DependencyDirectivesSourceMinimizer.h
The file was modifiedclang/unittests/Lex/DependencyDirectivesSourceMinimizerTest.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticLexKinds.td
The file was modifiedclang/test/Index/complete-preprocessor.m
The file was modifiedclang/include/clang/Lex/Preprocessor.h
The file was modifiedclang/test/Preprocessor/ifdef-recover.c
The file was modifiedclang/lib/Format/UnwrappedLineParser.cpp
The file was modifiedclang/include/clang/Lex/PPConditionalDirectiveRecord.h
The file was modifiedclang/include/clang/Lex/PPCallbacks.h
The file was modifiedclang/lib/Sema/SemaCodeComplete.cpp
The file was modifiedclang/include/clang/Basic/TokenKinds.def
The file was modifiedclang/lib/Lex/DependencyDirectivesSourceMinimizer.cpp
The file was modifiedclang/lib/Lex/PPConditionalDirectiveRecord.cpp
The file was addedclang/test/Preprocessor/elifdef.c
The file was modifiedclang/test/Preprocessor/macro_vaopt_check.cpp
The file was modifiedclang/lib/Index/IndexingAction.cpp
Commit 38641ddf3e5630db6ecb167b2d1b520b22e56405 by flo
[VPlan] Do not sink uniform recipes in sinkScalarOperands.

For uniform ReplicateRecipes, only the first lane should be used, so
sinking them would mean we have to compute the value of the first lane
multiple times. Also, at the moment, sinking them causes a crash because
the value of the first lane is re-used by all users.

Reported post-commit for D100258.
The file was modifiedllvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll
Commit 8c73a31c1175cc9dc8de9f056e10d557e470c10b by fraser
[RISCV] Allow passing fixed-length vectors via the stack

The vector calling convention dictates that when the vector argument
registers are exhaused, GPRs are used to pass the address via the stack.
When the GPRs themselves are exhausted, at best we would previously
crash with an assertion, and at worst we'd generate incorrect code.

This patch addresses this issue by passing fixed-length vectors via the
stack with their full fixed-length size and aligned to their element
type size. Since the calling convention lowering can't yet handle
scalable vector types, this patch adds a fatal error to make it clear
that we are lacking in this regard.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D102422
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/unsupported-calling-conv.ll
Commit b7101e218c215184b85fc740d726dc7652e4941e by fraser
[DAGCombine][RISCV] Don't try to trunc-store combined vector stores

DAGCombine's `mergeStoresOfConstantsOrVecElts` optimization is told
whether it's to use vector types and also whether it's to issue a
truncating store. However, the truncating store code path assumes a
scalar integer `ConstantSDNode`, and when using vector types it creates
either a `BUILD_VECTOR` or `CONCAT_VECTORS` to store: neither of which
is a constant.

The `riscv64` target is able to expose a crash here because it switches
on both code paths at the same time. The `f32` is stored as `i32` which
must be promoted to `i64`, necessitating a truncating store.
It also decides later that it prefers a vector store of `v2f32`.

While vector truncating stores are legal, this combine is not able to
emit them. We also don't have a test case. This patch adds an assert to
catch this case more gracefully, and updates one of the caller functions
to the function to turn off the use of truncating stores when preferring
vectors.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103173
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll
Commit ce276b7a6448d9c30f55235392c38b0416e91bbb by aaron
Fix -Wswitch warning; NFC
The file was modifiedclang/lib/Lex/PPDirectives.cpp
Commit 8a203ac6d22026fbb1b4b9cd9cdfdeffd17cb05d by Matthew.Arsenault
AMDGPU/GlobalISel: Remove redundant parameter from function
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit ee359000898c40ada69db3f20a87e6424c23596e by Matthew.Arsenault
AMDGPU/GlobalISel: Lower constant-32-bit zextload/sextload consistently

We were accidentally leaning on code in lowerLoad which expands
extending loads which should be removed.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 758f51c14ac3d4f243fce83e9733e2aea44dbd9e by aaron
Speculatively fix a -Woverloaded-virtual diagnostic; NFC
The file was modifiedclang/include/clang/Lex/PreprocessingRecord.h
Commit caf86d2959d5e900ed29af5e0ae2be23e3d299c5 by aaron
Speculatively fix this harder and with improved spelling capabilities.
The file was modifiedclang/lib/Index/IndexingAction.cpp
The file was modifiedclang/include/clang/Lex/PreprocessingRecord.h
Commit eba69b59d1a30dead07da2c279c8ecfd2b62ba9f by erich.keane
Reimplement __builtin_unique_stable_name-

The original version of this was reverted, and @rjmcall provided some
advice to architect a new solution.  This is that solution.

This implements a builtin to provide a unique name that is stable across
compilations of this TU for the purposes of implementing the library
component of the unnamed kernel feature of SYCL.  It does this by
running the Itanium mangler with a few modifications.

Because it is somewhat common to wrap non-kernel-related lambdas in
macros that aren't present on the device (such as for logging), this
uniquely generates an ID for all lambdas involved in the naming of a
kernel. It uses the lambda-mangling number to do this, except replaces
this with its own number (starting at 10000 for readabililty reasons)
for lambdas used to name a kernel.

Additionally, this implements itself as constexpr with a slight catch:
if a name would be invalidated by the use of this lambda in a later
kernel invocation, it is diagnosed as an error (see the Sema tests).

Differential Revision: https://reviews.llvm.org/D103112
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/Basic/StmtNodes.td
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
The file was modifiedclang/lib/Sema/SemaExceptionSpec.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/include/clang/Serialization/ASTBitCodes.h
The file was modifiedclang/include/clang/AST/TextNodeDumper.h
The file was modifiedclang/lib/AST/TextNodeDumper.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was modifiedclang/include/clang/Basic/TokenKinds.def
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/lib/Sema/SemaSYCL.cpp
The file was modifiedclang/include/clang/AST/ComputeDependence.h
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was addedclang/test/AST/ast-print-sycl-unique-stable-name.cpp
The file was modifiedclang/include/clang/Parse/Parser.h
The file was modifiedclang/lib/CodeGen/CGCUDANV.cpp
The file was addedclang/test/ParserSYCL/unique_stable_name_sycl_only.cpp
The file was modifiedclang/lib/Sema/TreeTransform.h
The file was modifiedclang/lib/Serialization/ASTReaderStmt.cpp
The file was modifiedclang/lib/AST/StmtProfile.cpp
The file was modifiedclang/lib/StaticAnalyzer/Core/ExprEngine.cpp
The file was modifiedclang/tools/libclang/CXCursor.cpp
The file was modifiedclang/include/clang/AST/Expr.h
The file was modifiedclang/include/clang/AST/JSONNodeDumper.h
The file was modifiedclang/lib/AST/JSONNodeDumper.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/lib/AST/ExprConstant.cpp
The file was modifiedclang/include/clang/AST/RecursiveASTVisitor.h
The file was modifiedclang/lib/Sema/SemaLambda.cpp
The file was modifiedclang/lib/AST/StmtPrinter.cpp
The file was modifiedclang/lib/AST/ComputeDependence.cpp
The file was addedclang/test/CodeGenSYCL/unique_stable_name.cpp
The file was modifiedclang/include/clang/AST/Mangle.h
The file was modifiedclang/lib/Serialization/ASTWriterStmt.cpp
The file was modifiedclang/lib/Parse/ParseExpr.cpp
The file was modifiedclang/lib/AST/ExprClassification.cpp
The file was modifiedclang/lib/Basic/IdentifierTable.cpp
The file was addedclang/test/ParserSYCL/unique_stable_name.cpp
The file was modifiedclang/docs/LanguageExtensions.rst
The file was modifiedclang/lib/AST/Expr.cpp
The file was addedclang/test/SemaSYCL/unique_stable_name.cpp
Commit 3879fcdb8733075cc5283199b89111d81b1f2d78 by schmeise
Reuse temporary files for print-changed=diff

Summary:
Make the file name and descriptors static so that they are reused by
print-changed=diff. This avoids errors about being unable to create
temporary files when doing the later comparisons in a large compile.

Author: Jamie Schmeiser <schmeise@ca.ibm.com>
Reviewed By: aeubanks (Arthur Eubanks)
Differential Revision: https://reviews.llvm.org/D100116
The file was modifiedllvm/lib/Passes/StandardInstrumentations.cpp
Commit 023fbf3df32d4100b57597a4e748c94931c1b936 by erich.keane
Correct the 'KEYALL' mask.

It should technically be a 1, since we are only setting the first bit.
The file was modifiedclang/lib/Basic/IdentifierTable.cpp
Commit 96ef4f4a24918642f2133522c8c686bd5cf8dc63 by aaron
Hopefully fix the Clang sphinx doc build.

This was broken several days ago in 826905787ae4c8540bb8a2384fac59c606c7eaff.
The file was modifiedclang/docs/OpenCLSupport.rst
Commit 9091ecdae0290d8c425d48a2c86bbdd4876d6507 by mats.petersson
[OpenMP]Add support for workshare loop modifier in lowering

When lowering the dynamic, guided, auto and runtime types of scheduling,
there is an optional monotonic or non-monotonic modifier. This patch
adds support in the OMP IR Builder to pass this down to the runtime
functions.

Also implements tests for the variants.

Differential Revision: https://reviews.llvm.org/D102008
The file was modifiedllvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
The file was modifiedllvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
The file was modifiedllvm/include/llvm/Frontend/OpenMP/OMPConstants.h
Commit 5a80dc498818d7f22a04d06986e78d151fb6e103 by fraser
[VP][SelectionDAG] Add a target-configurable EVL operand type

This patch adds a way for the target to configure the type it uses for
the explicit vector length operands of VP SDNodes. The type must be a
legal integer type (there is still no target-independent legalization of
this operand) and must currently be at least as big as i32, the type
used by the IR intrinsics. An implicit zero-extension takes place on
targets which choose a larger type. All VP nodes should be created with
this type used for the EVL operand.

This allows 64-bit RISC-V to avoid custom legalization of all VP nodes,
keeping them in their target-independent form for that bit longer.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D103027
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Commit 767d34e3bdddef6c1871006dd0a2d06a4e1bcd5d by aaron
Disable misc-no-recursion checking in Clang

We currently enable misc-no-recursion, but Clang uses recursion
intentionally in a fair number of places (like RecursiveASTVisitor).
Disabling this check reduces a noise in reviews that add new AST nodes,
like https://reviews.llvm.org/D103112#2780747 which has five CI
warnings that the author can do nothing about.
The file was modifiedclang/.clang-tidy
Commit 808dc6f8663c4c0696fc6eaf998db61a06330266 by Matthew.Arsenault
VirtRegMap: Preserve LiveDebugVariables

This avoids recomputing it between regalloc runs when allocation is
split, and also avoids a debug info test regression.
The file was modifiedllvm/test/CodeGen/AMDGPU/debug-value.ll
The file was modifiedllvm/lib/CodeGen/VirtRegMap.cpp
Commit aae7eb809e41d9e1e95175a017ca0fdccc87dedd by kiran.chandramohan
[Flang][Openmp] Fortran specific semantic checks for Allocate directive

This patch adds the following Fortran specific semantic checks for the OpenMP
Allocate directive.
1) A type parameter inquiry cannot appear in an ALLOCATE directive.
2) List items specified in the ALLOCATE directive must not have the ALLOCATABLE
attribute unless the directive is associated with an ALLOCATE statement.

Co-authored-by: Irina Dobrescu <irina.dobrescu@arm.com>

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D102061
The file was modifiedflang/lib/Semantics/check-omp-structure.h
The file was modifiedflang/include/flang/Semantics/symbol.h
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
The file was addedflang/test/Semantics/omp-allocate06.f90
The file was addedflang/test/Semantics/omp-allocate07.f90
The file was modifiedflang/lib/Semantics/resolve-directives.cpp
Commit 85f5272ffc58d73089bf77f0451b37176aa6b64f by sven.vanhaastregt
[OpenCL][NFC] Fix typos in test
The file was modifiedclang/test/Headers/opencl-c-header.cl
Commit e49d6e16235ac48e4dc55535a571989925b8da56 by llvm-dev
[X86][SSE] Regenerate some tests to expose the rip relative vector/broadcast loads
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-256.ll
The file was modifiedllvm/test/CodeGen/X86/combine-sdiv.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-256.ll
Commit fe8d97cbe5ecec50731650947b4e3b45f49228f8 by llvm-dev
[CostModel][X86] AVX512 truncation ops are slower than cost models indicate.

The SkylakeServer model (and later IceLake/TigerLake targets according to Agner) have the PMOV truncations as uops=2, rthroughput=2 instructions.

Noticed while trying to reduce the diffs between cost tables and llvm-mca analysis.
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/arith.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/trunc.ll
Commit 34046de04297dfbded824a756314bff0eb53de3d by Matthew.Arsenault
AMDGPU/GlobalISel: Fix broken test run line
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
Commit 5efc3bfd320712f6842a451fd3dae124380273ce by Matthew.Arsenault
AMDGPU/GlobalISel: Use IncomingValueAssigner for implicit return

This makes no real difference since we assign the same register either
way.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
Commit 1055cb91b48280da0c42c5287b227cfdaae633b2 by Louis Dionne
[libc++] Deprecate std::iterator and remove it as a base class

C++17 deprecated std::iterator and removed it as a base class for all
iterator adaptors. We implement that change, but we still provide a way
to inherit from std::iterator in the few cases where doing otherwise
would be an ABI break.

Supersedes D101729 and the std::iterator base parts of D103101 and D102657.

Differential Revision: https://reviews.llvm.org/D103171
The file was modifiedlibcxx/test/std/iterators/stream.iterators/istreambuf.iterator/types.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/reverse.iterators/reverse.iterator/types.pass.cpp
The file was modifiedlibcxx/include/iterator
The file was modifiedlibcxx/test/std/iterators/iterator.primitives/iterator.basic/iterator.pass.cpp
The file was addedlibcxx/test/libcxx/iterators/iterator.requirements/iterator.concepts/cpp20_iter_traits.compile.pass.cpp
The file was modifiedlibcxx/include/memory
The file was modifiedlibcxx/test/std/iterators/stream.iterators/ostreambuf.iterator/types.pass.cpp
The file was modifiedlibcxx/test/std/iterators/stream.iterators/istreambuf.iterator/istreambuf.iterator_proxy/proxy.pass.cpp
The file was modifiedlibcxx/include/__memory/raw_storage_iterator.h
The file was removedlibcxx/test/libcxx/iterators/iterator.requirements/iterator.concepts/cpp20_iter_traits.pass.cpp
The file was modifiedlibcxx/test/std/iterators/stream.iterators/istream.iterator/types.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/insert.iterators/back.insert.iterator/types.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/insert.iterators/front.insert.iterator/types.pass.cpp
The file was modifiedlibcxx/include/__config
The file was addedlibcxx/test/std/iterators/iterator.primitives/iterator.basic/deprecated.verify.cpp
The file was modifiedlibcxx/test/libcxx/iterators/iterator.requirements/iterator.concepts/cpp20_iter_concepts.pass.cpp
The file was modifiedlibcxx/test/std/iterators/predef.iterators/insert.iterators/insert.iterator/types.pass.cpp
The file was modifiedlibcxx/test/std/iterators/stream.iterators/ostream.iterator/types.pass.cpp
The file was addedlibcxx/test/std/utilities/memory/storage.iterator/types.compile.pass.cpp
Commit 73099e786aef9db88811338e217e1ea791bcaa2e by Louis Dionne
[libc++] NFC: Parenthesize expression to satisfy GCC 11

Otherwise it issues a -Werror=parentheses suggesting parentheses.
The file was modifiedlibcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/check_round_trip.h
Commit 192b4141f0d74dd08a4eacf2184a6881906993ed by thakis
Revert "Emit correct location lists with basic block sections."

Breaks check-llvm on non-linux, see comments on https://reviews.llvm.org/D85085
This reverts commit caae570978c490a137921b9516162a382831209e
and follow-up commit 1546c52d971292ed4145b6d41aaca0d02229ebff.
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp
The file was removedllvm/test/DebugInfo/X86/basic-block-sections-debug-loc-const-value-1.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was removedllvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-4.ll
The file was removedllvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-3.ll
The file was modifiedllvm/test/DebugInfo/X86/basic-block-sections-debug-loc.ll
The file was removedllvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-5.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
The file was removedllvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-2.ll
The file was removedllvm/test/DebugInfo/X86/basic-block-sections-debug-loc-const-value-2.ll
The file was removedllvm/test/DebugInfo/X86/basic-block-sections-debug-loclist-1.ll
The file was removedllvm/test/DebugInfo/X86/basic-block-sections-debug-loc-split-range.ll
The file was modifiedllvm/test/DebugInfo/X86/basic-block-sections_1.ll
Commit 3d64677c28072867ea6025a22805977386b767f8 by aaron.puchert
Thread safety analysis: Factor out function for merging locks (NFC)

It's going to become a bit more complicated, so let's have it separate.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D102025
The file was modifiedclang/lib/Analysis/ThreadSafety.cpp
Commit cf0b337c1b1f064c81fe40124ddba178572778d6 by aaron.puchert
Thread safety analysis: Allow exlusive/shared joins for managed and asserted capabilities

Similar to how we allow managed and asserted locks to be held and not
held in joining branches, we also allow them to be held shared and
exclusive. The scoped lock should restore the original state at the end
of the scope in any event, and asserted locks need not be released.

We should probably only allow asserted locks to be subsumed by managed,
not by (directly) acquired locks, but that's for another change.

Reviewed By: delesley

Differential Revision: https://reviews.llvm.org/D102026
The file was modifiedclang/lib/Analysis/ThreadSafety.cpp
The file was modifiedclang/test/SemaCXX/warn-thread-safety-analysis.cpp
Commit 7922ff601094585c4b46b2640b7d07986f722c1b by jasonliu
[AIX] Add -lc++abi and -lunwind for linking

Summary:
We are going to have libc++abi.a and libunwind.a on AIX.
Add the necessary linking command to pick the libraries up.

Reviewed By: daltenty

Differential Revision: https://reviews.llvm.org/D102813
The file was modifiedclang/lib/Driver/ToolChains/AIX.cpp
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.cpp
The file was modifiedclang/lib/Driver/ToolChain.cpp
The file was modifiedclang/test/Driver/aix-ld.c
Commit e892705d74c7366a1404a3b3471001edaa7659f8 by Matthew.Arsenault
GlobalISel: Do not change register types in lowerLoad

Adjusting the load register type is a widenScalar type action, not a
lowering. lowerLoad should be reserved for operations that change the
memory access size, such as unaligned load decomposition. With this
trying to adjust the register type, it was hard to avoid infinite
loops in the legalizer. Adds a bandaid to avoid regressing a few
AArch64 tests, but I'm not sure what the exact condition is and
there's probably a cleaner way to do this.

For AMDGPU this regresses handling of some cases for unaligned loads,
but the way this is currently working is a pretty ugly hack.
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Commit 6f4794feb60a9deb939873118a7182a8ea87732e by fraser
[RISCV] Add a test case showing incorrect call-conv lowering

@HsiangKai helped find a bug in the lowering of indirect split
scalable-vector types in our calling convention. An imminent patch will
fix this.
The file was addedllvm/test/CodeGen/RISCV/rvv/calling-conv.ll
Commit 6d2c0950205f50f926ba5e362e845faff22582b7 by Yaxun.Liu
[HIP] Check compatibility of -fgpu-sanitize with offload arch

-fgpu-sanitize is incompatible with offload arch containing xnack-.

This patch checks that.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D102975
The file was modifiedclang/test/Driver/hip-sanitize-options.hip
The file was modifiedclang/lib/Driver/ToolChains/HIP.h
The file was modifiedclang/lib/Driver/ToolChains/AMDGPU.cpp
The file was modifiedclang/lib/Driver/ToolChains/AMDGPU.h
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
Commit b44007bec2470db0d9f100c6a9216d8e05cef608 by thomasraoux
[mlir][gpu] Relax restriction on MMA store op to allow chain of mma ops.

In order to allow large matmul operations using the MMA ops we need to chain
operations this is not possible unless "DOp" and "COp" type have matching
layout so remove the "DOp" layout and force accumulator and result type to
match.
Added a test for the case where the MMA value is accumulated.

Differential Revision: https://reviews.llvm.org/D103023
The file was modifiedmlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32.mlir
The file was modifiedmlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUDialect.h
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
The file was modifiedmlir/test/Dialect/GPU/invalid.mlir
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp
The file was modifiedmlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f16.mlir
The file was modifiedmlir/include/mlir/Dialect/GPU/GPUOps.td
The file was modifiedmlir/test/Conversion/GPUToNVVM/wmma-ops-to-nvvm.mlir
Commit 5c18d1136665f74b15c0df599f56ac3e2e947fb8 by qiucofan
[SPE] Disable strict-fp for SPE by default

As discussed in PR50385, strict-fp on PowerPC SPE has not been handled
well. This patch disables it by default for SPE.

Reviewed By: nemanjai, vit9696, jhibbits

Differential Revision: https://reviews.llvm.org/D103235
The file was modifiedclang/test/CodeGen/builtins-ppc-fpconstrained.c
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
Commit 21653600034084e8335374ddc1eb8d362158d9a8 by konndennsa
[LoopUnrollAndJam] Change LoopUnrollAndJamPass to LoopNest pass

This patch changes LoopUnrollAndJamPass from FunctionPass to LoopNest pass.
The next patch will utilize LoopNest to effectively handle loop nests.

Reviewed By: Whitney

Differential Revision: https://reviews.llvm.org/D99149
The file was modifiedllvm/include/llvm/Transforms/Scalar/LoopUnrollAndJamPass.h
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/innerloop.ll
The file was modifiedllvm/include/llvm/Transforms/Scalar/LoopPassManager.h
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
Commit c412979cde54ec3b5d9f3b83f2b8b5b4b353ed65 by ezhulenev
[mlir] Async reference counting for block successors with divergent reference counted liveness

Support reference counted values implicitly passed (live) only to some of the successors.

Example: if branched to ^bb2 token will leak, unless `drop_ref` operation is properly created

```
^entry:
  %token = async.runtime.create : !async.token
   cond_br %cond, ^bb1, ^bb2
^bb1:
  async.runtime.await %token
  async.runtime.drop_ref %token
  br ^bb2
^bb2:
  return
```

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D103102
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncRuntimeRefCounting.cpp
The file was modifiedmlir/test/Dialect/Async/async-runtime-ref-counting.mlir
Commit 4fbc66cd6d90d8d5169c43fcc1b1e26e8a98d3a9 by elver
[Clang] Enable __has_feature(coverage_sanitizer)

Like other sanitizers, enable __has_feature(coverage_sanitizer) if clang
has enabled at least one SanitizerCoverage instrumentation type.

Because coverage instrumentation selection is not handled via normal
-fsanitize= (and thus not in SanitizeSet), passing this information
through to LangOptions required propagating the already parsed
-fsanitize-coverage= options from CodeGenOptions through to LangOptions
in FixupInvocation().

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D103159
The file was modifiedclang/include/clang/Basic/Features.def
The file was addedclang/test/Lexer/has_feature_coverage_sanitizer.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/docs/SanitizerCoverage.rst
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
Commit 39957aa4243cb9aec3a7114c0ecf710ecce96b72 by ezhulenev
[mlir] Add error state and error propagation to async runtime values

Depends On D103102

Not yet implemented:
1. Error handling after synchronous await
2. Error handling for async groups

Will be addressed in the followup PRs

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D103109
The file was modifiedmlir/test/Dialect/Async/runtime.mlir
The file was addedmlir/test/mlir-cpu-runner/async-error.mlir
The file was modifiedmlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
The file was modifiedmlir/test/Conversion/AsyncToLLVM/convert-runtime-to-llvm.mlir
The file was modifiedmlir/include/mlir/ExecutionEngine/AsyncRuntime.h
The file was modifiedmlir/include/mlir/Dialect/Async/IR/AsyncOps.td
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
The file was modifiedmlir/lib/ExecutionEngine/AsyncRuntime.cpp
The file was modifiedmlir/test/Dialect/Async/async-to-async-runtime.mlir
Commit b5f8ac26829385d98f730c2a76c5f9a6306df2f8 by craig.topper
[X86] Pre-commit tests for D103192. NFC
The file was modifiedllvm/test/CodeGen/X86/vec_shift5.ll
Commit a105d3024efec365961e940c489c4ed5198736d2 by craig.topper
[X86] Fold (shift undef, X)->0 for vector shifts by immediate.

We could previously do this by accident through the later
call to getTargetConstantBitsFromNode I think, but that only worked
if N0 had a single use. This patch makes it explicit for undef and
doesn't have a use count check.

I think this is needed to move the (shl X, 1)->(add X, X)
fold to isel for PR50468. We need to be sure X won't be IMPLICIT_DEF
which might prevent the same vreg from being used for both operands.

Differential Revision: https://reviews.llvm.org/D103192
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vec_shift5.ll
Commit d8c84d2a4efc87b756d9d3df42b80d6f8762f62a by ezhulenev
[mlir] Async: Add error propagation support to async groups

Depends On D103109

If any of the tokens/values added to the `!async.group` switches to the error state, than the group itself switches to the error state.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D103203
The file was modifiedmlir/lib/ExecutionEngine/AsyncRuntime.cpp
The file was modifiedmlir/test/Dialect/Async/runtime.mlir
The file was modifiedmlir/test/Dialect/Async/async-to-async-runtime.mlir
The file was modifiedmlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
The file was modifiedmlir/include/mlir/Dialect/Async/IR/AsyncOps.td
The file was modifiedmlir/test/mlir-cpu-runner/async-error.mlir
The file was modifiedmlir/include/mlir/ExecutionEngine/AsyncRuntime.h
Commit 750799b7bc3faeda0d4a14e556ce788e0452152e by thomasraoux
[mlir][NFC] Don't outline kernel in MMA integration tests

This matches better how other gpu integration tests are done.

Differential Revision: https://reviews.llvm.org/D103099
The file was modifiedmlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f16.mlir
The file was modifiedmlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32.mlir
Commit 527cd013144d3fb3b578640721530fa2d2da4da9 by craig.topper
[RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed.

This can help avoid needing a virtual register for the vsetvl output
when the AVL is X0. For other register AVLs it can shorter the live
range of the AVL register if it isn't needed later.

There's probably no advantage when AVL is a 5 bit immediate that
can use vsetivli. But do it anyway for consistency.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D103215
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
Commit 90d25808c4207d22eec27f2677b7e658308dd2f9 by llvm-dev
[CostModel][X86] Improve accuracy of sext/zext to 256-bit vector costs on AVX1 targets

Determined from llvm-mca analysis (btver2 vs bdver2 vs sandybridge), the split+extends+concat sequence on AVX1 capable targets are cheaper than the #ops that the cost was previously based on.
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-fix.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/extend.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-mul.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/rem.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/arith.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-overflow.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/cast.ll
Commit bafbec8535690d625f1ed770db77f762a825ac0b by lebedev.ri
[NFC][X86][Codegen] Re-autogenerate check lines in a few tests to remove noise from future changes
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-math.ll
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll
The file was modifiedllvm/test/CodeGen/X86/psubus.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-packus.ll
The file was modifiedllvm/test/CodeGen/X86/oddshuffles.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
The file was modifiedllvm/test/CodeGen/X86/avx2-conversions.ll
The file was modifiedllvm/test/CodeGen/X86/combine-sra.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-ssat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining.ll
The file was modifiedllvm/test/CodeGen/X86/combine-srl.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-usat.ll
Commit b6399e85d80d2bea522e4bce1c8c3744e45673e2 by Louis Dionne
Revert "[libc++] NFC: Parenthesize expression to satisfy GCC 11"

That fix was actually incorrect and caused tests to start failing.
The file was modifiedlibcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/check_round_trip.h
Commit eb69763ad8ea18ef1b0d739847da0be4ab099d51 by Vitaly Buka
[NFC][scudo] Rename internal function
The file was modifiedcompiler-rt/lib/scudo/standalone/linux.cpp
Commit 4cc5a971010efd48c60820b17c8de8ed086aa45f by Saleem Abdulrasool
MC: mark `dump` with `LLVM_DUMP_METHOD`

Mark the `ELFRelocationEntry::dump` method as `LLVM_DUMP_METHOD` to
annotate it properly as used to prevent the function being dead stripped
away.  This allows use of `dump` in the debugger.  This is purely to
improve the developer experience.
The file was modifiedllvm/include/llvm/MC/MCELFObjectWriter.h
Commit 9136b7d075d26a04db9dfed43c37e4c05cd3ccff by ezhulenev
[mlir] AsyncRefCounting: check that LivenessBlockInfo is not nullptr

Differential Revision: https://reviews.llvm.org/D103270
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncRuntimeRefCounting.cpp
Commit 5618a5a0594403bc8a22b60e06abd7f9d1e57afc by jpienaar
[mlir] Update cmake variable post D102976
The file was modifiedmlir/tools/mlir-vulkan-runner/CMakeLists.txt
Commit c261edb277020471b7670a8b2f826efc73c5d941 by Vitaly Buka
[NFC][scudo] Check zeros on smaller allocations

1Tb counting was the slowest test under the QEMU with MTE.
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/common_test.cpp
Commit 8d7d7f340ea0202cedddc786b484048da4bbc767 by Louis Dionne
[libc++] NFC: Refactor raw_storage_iterator test to use UNSUPPORTED markup

The test would previously disable itself using `#if TEST_STD_VER` instead
of using UNSUPPORTED markup.
The file was modifiedlibcxx/test/std/utilities/memory/storage.iterator/raw_storage_iterator.base.pass.cpp
Commit d7ae2438b9bd062159fa9bfa8e4db2b8a0d66e38 by craig.topper
[RISCV] Add a test showing missed opportunity to avoid a vsetvli in a loop.

This is another case we need to look through a phi to prove.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
Commit 32bacb74107e45cdcedaf3bb2be11bd6e3015390 by walter erquinigo
[lldb][intel-pt] Remove old plugin

Now that LLDB proper has built-in support for intel-pt traces, we can remove the old plugin written by Intel. It has less features and it's hard to work with.

As a test, I ran "ninja lldbIntelFeatures" and it worked.

Differential Revision: https://reviews.llvm.org/D102866
The file was removedlldb/tools/intel-features/intel-pt/CMakeLists.txt
The file was removedlldb/tools/intel-features/scripts/lldb-intel-features.swig
The file was removedlldb/tools/intel-features/scripts/CMakeLists.txt
The file was removedlldb/tools/intel-features/intel-pt/interface/PTDecoder.i
The file was removedlldb/tools/intel-features/scripts/python-typemaps.txt
The file was removedlldb/tools/intel-features/intel-pt/cli-wrapper-pt.h
The file was removedlldb/tools/intel-features/intel-pt/Decoder.cpp
The file was removedlldb/tools/intel-features/intel-pt/PTDecoder.cpp
The file was modifiedlldb/tools/intel-features/README.txt
The file was modifiedlldb/tools/intel-features/cli-wrapper.cpp
The file was removedlldb/tools/intel-features/intel-pt/PTDecoder.h
The file was removedlldb/tools/intel-features/intel-pt/cli-wrapper-pt.cpp
The file was removedlldb/tools/intel-features/intel-pt/README_CLI.txt
The file was modifiedlldb/tools/intel-features/CMakeLists.txt
The file was removedlldb/tools/intel-features/intel-pt/Decoder.h
The file was removedlldb/tools/intel-features/intel-pt/README_TOOL.txt
Commit 8f23fac4da254e8cd2a3160a4fa029613a284ebe by ezhulenev
[mlir:Async] Convert assertions to async errors only inside async functions

Differential Revision: https://reviews.llvm.org/D103278
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
Commit 50f17e9d313960ddc956c20e4f90cfbfed91ecb1 by Artem Dergachev
[analyzer] RetainCountChecker: Disable reference counting for OSMetaClass.

It is a reference-counted class but it uses different methods for that
and the checker doesn't understand them yet.

Differential Revision: https://reviews.llvm.org/D103081
The file was modifiedclang/test/Analysis/osobject-retain-release.cpp
The file was modifiedclang/lib/Analysis/RetainSummaryManager.cpp
The file was modifiedclang/test/Analysis/os_object_base.h
Commit f3869a5c32b78bc70e5051efbc2594f772b0176e by Adrian Prantl
Support stripping indirectly referenced DILocations from !llvm.loop metadata

in stripDebugInfo().  This patch fixes an oversight in
https://reviews.llvm.org/D96181 and also takes into account loop
metadata pointing to other MDNodes that point into the debug info.

rdar://78487175

Differential Revision: https://reviews.llvm.org/D103220
The file was addedllvm/test/Verifier/llvm.loop-cu-strip-indirect.ll
The file was modifiedllvm/lib/Transforms/Utils/CodeExtractor.cpp
The file was modifiedllvm/include/llvm/IR/DebugInfo.h
The file was modifiedllvm/lib/IR/DebugInfo.cpp
The file was modifiedllvm/lib/Transforms/Utils/InlineFunction.cpp
Commit 9712b16763602370f8f66775da6f3766c139ebab by lebedev.ri
[NFC][X86][Codegen] vector-interleaved-store-i16-stride-5.ll: precisely match the actual IR

Now that i've reimplemented the testcase generator
to produce actual IR (https://godbolt.org/z/s7PM8E6v9),
it turns out that this was the only discrepancy
from what the LV would produce.
The file was modifiedllvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
Commit 0d5219feb9b26f299823b43c3c478e98cb3a0915 by spatel
[x86] add tests for extend of vector compare; NFC
The file was addedllvm/test/CodeGen/X86/sext-vsetcc.ll
Commit cb66bf2c6d20da01ab57cb78ec5e5c0978b873be by erich.keane
Replace 'magic static' with a member variable for SCYL kernel names

I discovered when merging the __builtin_sycl_unique_stable_name into my
downstream that it is actually possible for the cc1 invocation to have
more than 1 Sema instance, if you pass it multiple input files, each
gets its own Sema instance and thus ASTContext instance.  The result was
that the call to Filter the SYCL kernels was using an
ItaniumMangleContext stored via a 'magic static', so it had an invalid
reference to ASTContext when processing the 2nd failure.

The failure is unfortunately flakey/transient, but the test that fails
was added anyway.

The magic-static was switched to a unique_ptr member variable in
ASTContext that is initialized when needed.
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was addedclang/test/SemaSYCL/unique-stable-name-multiple-target-crash.cpp
Commit aad878f11279305b55e43d7225a36dc0035ecc86 by Louis Dionne
[libc++] NFC: Make it easier for vendors to extend the run-buildbot script
The file was modifiedlibcxx/utils/ci/run-buildbot
Commit 0e4cf807aeaf54a10e02176498a7df13ac722b37 by martin
[clang] [MinGW] Don't mark emutls variables as DSO local

These actually can be automatically imported from another DLL. (This
works properly as long as the actual implementation of emutls is
linked dynamically from e.g. libgcc; if the implementation comes from
compiler-rt or a statically linked libgcc, it doesn't work as intended.)

This fixes PR50146 and https://github.com/msys2/MINGW-packages/issues/8706
(fixing calling std::call_once in a dynamically linked libstdc++);
since f73183958482602c4588b0f4a1c3a096e7542947 the dso_local attribute
on the TLS variable affected the actual generated code for accessing
the emutls variable.

The dso_local attribute on the emutls variable made those accesses to
use 32 bit relative addressing in code, which requires runtime pseudo
relocations in the text section, and breaks entirely if the actual
other variable ends up loaded too far away in the virtual address
space.

Differential Revision: https://reviews.llvm.org/D102970
The file was modifiedclang/test/CodeGen/dso-local-executable.c
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
Commit b3ceffdf35e5018958891215000b010ac614dbcc by martin
[libcxx] [test] Convert an XFAIL LIBCXX-WINDOWS-FIXME into UNSUPPORTED with explanation

Differential Revision: https://reviews.llvm.org/D103149
The file was modifiedlibcxx/test/libcxx/debug/extern-templates.sh.cpp
Commit d47dd11071322ad7be6ec7e35a89d0d8f26534b9 by riddleriver
[mlir] Add support for querying the ModRef behavior from the AliasAnalysis class

This allows for checking if a given operation may modify/reference/or both a given value. Right now this API is limited to Value based memory locations, but we should expand this to include attribute based values at some point. This is left for future work because the rest of the AliasAnalysis API also has this restriction.

Differential Revision: https://reviews.llvm.org/D101673
The file was modifiedmlir/lib/Analysis/AliasAnalysis.cpp
The file was modifiedmlir/lib/Analysis/AliasAnalysis/LocalAliasAnalysis.cpp
The file was modifiedmlir/include/mlir/Analysis/AliasAnalysis.h
The file was modifiedmlir/test/lib/Analysis/TestAliasAnalysis.cpp
The file was modifiedmlir/include/mlir/Analysis/AliasAnalysis/LocalAliasAnalysis.h
The file was addedmlir/test/Analysis/test-alias-analysis-modref.mlir
Commit 020df692d801c4fa9a67eb32e923927e33f9e4b5 by craig.topper
[RISCV] Fix typo, use addImm instead of addReg.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Commit 109aac92128ca958afe5141a59347c8a0733ea3e by rnk
[PDB] Enable parallel ghash type merging by default

Ghashing is probably going to be faster in most cases, even without
precomputed ghashes in object files.

Here is my table of results linking clang.pdb:

-------------------------------
| threads | GHASH   | NOGHASH |
-------------------------------
|  j1     | 51.031s | 25.141s |
|  j2     | 31.079s | 22.109s |
|  j4     | 18.609s | 23.156s |
|  j8     | 11.938s | 21.984s |
| j28     |  8.375s | 18.391s |
-------------------------------

This shows that ghashing is faster if at least four cores are available.
This may make the linker slower if most cores are busy in the middle of
a build, but in that case, the linker probably isn't on the critical
path of the build. Incremental build performance is arguably more
important than highly contended batch build link performance.

The -time output indicates that ghash computation is the dominant
factor:

    Input File Reading:             924 ms (  1.8%)
    GC:                             689 ms (  1.3%)
    ICF:                            527 ms (  1.0%)
    Code Layout:                    414 ms (  0.8%)
    Commit Output File:              24 ms (  0.0%)
    PDB Emission (Cumulative):    49938 ms ( 94.8%)
      Add Objects:                46783 ms ( 88.8%)
        Global Type Hashing:      38983 ms ( 74.0%)
        GHash Type Merging:        5640 ms ( 10.7%)
        Symbol Merging:            2154 ms (  4.1%)
      Publics Stream Layout:        188 ms (  0.4%)
      TPI Stream Layout:             18 ms (  0.0%)
      Commit to Disk:              2818 ms (  5.4%)
  --------------------------------------------------
  Total Link Time:                52669 ms (100.0%)

We can speed that up with a faster content hash (not SHA1).

Differential Revision: https://reviews.llvm.org/D102888
The file was modifiedlld/test/COFF/pdb-type-server-simple.test
The file was modifiedlld/COFF/Driver.cpp
Commit 62b5df7fe2b3fda1772befeda15598fbef96a614 by stefanp
[PowerPC] Added multiple PowerPC builtins

This is the first in a series of patches to provide builtins for
compatibility with the XL compiler. Most of the builtins already had
intrinsics and only needed to be implemented in the front end.
Intrinsics were created for the three iospace builtins, eieio, and icbt.
Pseudo instructions were created for eieio and iospace_eieio to
ensure that nops were inserted before the eieio instruction.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D102443
The file was modifiedllvm/test/CodeGen/PowerPC/eieio.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-sync.c
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedclang/lib/Basic/Targets/PPC.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
Commit 50770d8de56068312bd0e1baa63e86912ce2b631 by andrea.dibiagio
[MCA] Refactor the InOrderIssueStage stage. NFCI

Moved the logic that checks for RAW hazards from the InOrderIssueStage to the
RegisterFile.

Changed how the InOrderIssueStage keeps track of backend stalls. Stall events
are now generated from method notifyStallEvent().

No functional change intended.
The file was modifiedllvm/lib/MCA/Stages/ExecuteStage.cpp
The file was modifiedllvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
The file was modifiedllvm/include/llvm/MCA/Stages/ExecuteStage.h
The file was modifiedllvm/include/llvm/MCA/Stages/InOrderIssueStage.h
The file was modifiedllvm/include/llvm/MCA/HWEventListener.h
The file was modifiedllvm/include/llvm/MCA/Stages/InstructionTables.h
The file was modifiedllvm/lib/MCA/Stages/InOrderIssueStage.cpp
The file was modifiedllvm/include/llvm/MCA/HardwareUnits/RegisterFile.h
The file was modifiedllvm/lib/MCA/HardwareUnits/RegisterFile.cpp
Commit 8cbbc5d00b6a13ccef2b61d151aa56e9f851839c by riddleriver
[mlir-lsp-server] Add support for processing split files

MLIR tools very commonly use `// -----` to split a file into distinct sub documents, that are processed separately. This revision adds support to mlir-lsp-server for splitting MLIR files based on this sigil, and processing them separately.

Differential Revision: https://reviews.llvm.org/D102660
The file was addedmlir/test/mlir-lsp-server/definition-split-file.test
The file was modifiedmlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp
Commit b834d6309455e340d6f5dcb8b8de885da5cf25a0 by rprichard
[sanitizer] Android ELF TLS is supported from Q (API 29)

Reviewed By: oontvoo, MaskRay

Differential Revision: https://reviews.llvm.org/D103214
The file was modifiedcompiler-rt/CMakeLists.txt
The file was modifiedcompiler-rt/test/sanitizer_common/TestCases/Linux/use_tls_test.cpp
The file was modifiedcompiler-rt/test/lit.common.cfg.py
Commit ef1cc4e7aebea584c9e63837fc83f4f755cb7af3 by ajcbik
[mlir][capi] fix build issue with "all passes" registration

Some builds exposed missing dependences on trafo/conv passes.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D103283
The file was modifiedmlir/lib/CAPI/Registration/CMakeLists.txt
Commit ee544b8d868d5845798c37200a4b2bd9de889a96 by lebedev.ri
[NFC][X86][Codegen] Re-autogenerate a few tests to reduce noise in future changes
The file was modifiedllvm/test/CodeGen/X86/insertelement-zero.ll
The file was modifiedllvm/test/CodeGen/X86/vector-rotate-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
The file was modifiedllvm/test/CodeGen/X86/buildvec-extract.ll
Commit 2d2a9020785c6e02afebc876aa2778fa64c5cafd by aeubanks
[SanCov] Properly set ABI parameter attributes

Arguments need to have the proper ABI parameter attributes set.

Followup to D101806.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D103288
The file was modifiedllvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/const-cmp-tracing.ll
The file was modifiedllvm/test/Instrumentation/SanitizerCoverage/div-tracing.ll
Commit 0fa5aac292b8e1bafb00b55233c78466b06bc323 by craig.topper
[RISCV] Teach VSETVLI insertion to look through PHIs to prove we don't need to insert a vsetvli.

If an instruction's AVL operand is a PHI node in the same block,
we may be able to peek through the PHI to find vsetvli instructions
that produce the AVL in other basic blocks. If we can prove those
vsetvli instructions have the same VTYPE and were the last vsetvli
in their respective blocks, then we don't need to insert a vsetvli
for this pseudo instruction.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D103277
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Commit 8086f9d87ee81aacf829bdad94744a75cf692ebc by aeubanks
[ConstFold] Simplify a load's GEP operand through local aliases

MSVC-style RTTI produces loads through a GEP of a local alias which
itself is a GEP. Currently we aren't able to devirtualize any virtual
calls when MSVC RTTI is enabled.

This patch attempts to simplify a load's GEP operand by calling
SymbolicallyEvaluateGEP() with an option to look through local aliases.

Differential Revision: https://reviews.llvm.org/D101100
The file was addedllvm/test/Transforms/InstSimplify/ConstProp/gep-alias-gep-load.ll
The file was modifiedllvm/lib/Analysis/ConstantFolding.cpp
Commit 57646d38d54c6a52a4fac4b0ac1047b0dbaec94a by andrea.dibiagio
[MCA] Minor changes to the InOrderIssueStage. NFC

The constructor of InOrderIssueStage no longer takes as input a reference to the
target scheduling model. The stage can always query the subtarget to obtain a
reference to the scheduling model.
The ResourceManager is no longer stored internally as a unique_ptr.
Moved a couple of method definitions to the .cpp file.
The file was modifiedllvm/lib/MCA/Stages/InOrderIssueStage.cpp
The file was modifiedllvm/lib/MCA/Context.cpp
The file was modifiedllvm/include/llvm/MCA/Stages/InOrderIssueStage.h
Commit e41aaea26238d0a5cb19163863819786e24f0e02 by rupprecht
[NFC][libObject] clang-format Archive{.h,.cpp}

In preparation for D100651
The file was modifiedllvm/include/llvm/Object/Archive.h
The file was modifiedllvm/lib/Object/Archive.cpp
Commit 80e684b194235c0637c16b4163ed984859980852 by joker.eph
Fix comment to reflect what the method is doing (NFC)
The file was modifiedmlir/lib/IR/MLIRContext.cpp
Commit fc1d39849e8d57ec8cb2ce0e1581faa88ae72fbe by jianzhouzh
[dfsan] Add a flag about whether to propagate offset labels at gep

DFSan has flags to control flows between pointers and objects referred
by pointers. For example,

a = *p;
L(a) = L(*p)        when -dfsan-combine-pointer-labels-on-load = false
L(a) = L(*p) + L(p) when -dfsan-combine-pointer-labels-on-load = true

*p = b;
L(*p) = L(b)        when -dfsan-combine-pointer-labels-on-store = false
L(*p) = L(b) + L(p) when -dfsan-combine-pointer-labels-on-store = true
The question is what to do with p += c.

In practice we found many confusing flows if we propagate labels from c
to p. So a new flag works like this

p += c;
L(p) = L(p)        when -dfsan-propagate-via-pointer-arithmetic = false
L(p) = L(p) + L(c) when -dfsan-propagate-via-pointer-arithmetic = true

Reviewed-by: gbalats

Differential Revision: https://reviews.llvm.org/D103176
The file was modifiedllvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
The file was addedcompiler-rt/test/dfsan/gep.c
The file was addedllvm/test/Instrumentation/DataFlowSanitizer/dont_combine_offset_labels_on_gep.ll
Commit b2581196eb036bd1310afd39f440e348e0e1a580 by Jinsong Ji
[AIX] Enable stackprotect feature

AIX use `__ssp_canary_word` instead of `__stack_chk_guard`.
This patch update the target hook to use correct symbol,
so that the basic stackprotect feature can work.

The traceback will be handled in follow up patch.

Reviewed By: #powerpc, shchenz

Differential Revision: https://reviews.llvm.org/D103100
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/lib/Transforms/IPO/Internalize.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/stack-guard-oob.ll
The file was modifiedllvm/test/Transforms/Internalize/stackguard.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/test/CodeGen/PowerPC/stack-protector.ll
Commit 99f023656b785b79253dd1ddae6aa2f822180aab by rnk
[PDB] Fix ubsan complaint about memcpy from null pointer
The file was modifiedlld/COFF/DebugTypes.cpp
Commit 59b8afe50274be975c62a4b11db49c84a874c0c0 by zequanwu
[clang-cl] Bump default -fms-compatibility-version to 19.14

MSVC required version is 19.14 now (https://reviews.llvm.org/D92515). Update the
default -fms-compatibility-version to 19.14.

Differential Revision: https://reviews.llvm.org/D103293
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/lib/Driver/ToolChains/MSVC.cpp
The file was modifiedclang/test/Driver/cl-options.c
Commit ef4cfd83223890fdbd69fbc9899089365f4588b4 by rnk
Pass -gcodeview-ghash when using clang-cl and lld-link

This precomputes some hashes that LLD uses for type merging to speed up
linking when PDBs are enabled. Only do this if any kind of /DEBUG flag
is passed to the linker. -gcodeview-ghash is orthogonal to /Z7, -g, -g1,
or -gmlt, so it is safe to set it independently from those flags. It
will not increase debug info emission.

Differential Revision: https://reviews.llvm.org/D103287
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
Commit 6a2af607ad3523ddc3778b0efb7bb1d5d42a1edb by mkazantsev
Revert "[NFCI] Lazily evaluate SCEVs of PHIs"

This reverts commit 51d334a845a082338735b0fdfc620a4b15fa26fe.

Reported failures, need to analyze.
The file was modifiedllvm/lib/Transforms/Scalar/LoopDeletion.cpp
Commit 59a4ee97288b1297bb98edd7f24fecd5e9c57170 by Amara Emerson
[AArch64][GlobalISel] Legalize oversize G_EXTRACT_VECTOR_ELT sources.

Also changes the fewerElements helper to use the lookthrough constant helper
instead of m_ICst, since m_ICst doesn't look through extends.

Differential Revision: https://reviews.llvm.org/D103227
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Summary

  1. Removed abandoned lldb-sphinx-docs builder. (details)
  2. [sanitizer] Switch to patched QEMU (details)
Commit f395d4d0c7d3e9f063d6becd5933d77eb32c1089 by gkistanova
Removed abandoned lldb-sphinx-docs builder.
The file was modifiedbuildbot/osuosl/master/config/builders.py
Commit 6e3e7926bcf8e4d83d83d9072990ddc33e02bb11 by Vitaly Buka
[sanitizer] Switch to patched QEMU
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh