Changes

Summary

  1. [jenkins] Update script to use cross project lit test suite (details)
  2. Add chown to buildbot_qemu local repro instructions. (details)
  3. [sanitizer] Fix mips QEMU build (details)
  4. [scudo] Disable mips 32bit tests (details)
  5. [sanitizer] Don't tie builders with particular workers (details)
  6. [sanitizer] Missing image is infra issues (details)
  7. [sanitizer] Set EXE_LINKER_FLAGS same as SHARED_LINKER_FLAGS (details)
Commit e48da4b7b382fe94b714ce5aaaf02ee45e32825e by medismail.bennani
[jenkins] Update script to use cross project lit test suite

To reflect changes announced in
https://lists.llvm.org/pipermail/llvm-dev/2021-January/148048.html,
this patch updates all occurrences of `debuginfo-tests` to
`cross-project-debuginfo-tests`.

Differential Revision: https://reviews.llvm.org/D105134

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedzorg/jenkins/jobs/jobs/lldb-cmake (diff)
The file was modifiedzorg/jenkins/jobs/jobs/llvm-coverage (diff)
Commit 6b155f2b6b876096a8506594ddb627e0fed8e014 by 31459023+hctim
Add chown to buildbot_qemu local repro instructions.
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh (diff)
Commit 93ca31c2900b341a5f1535cae0243a454a832a1b by Vitaly Buka
[sanitizer] Fix mips QEMU build
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh (diff)
Commit 2a09e457cf5d095778714696a6bd2c061e5ac1e8 by Vitaly Buka
[scudo] Disable mips 32bit tests

It times out for unknown reasons.
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh (diff)
Commit d37259ec73a4341700e981214b9032631adfdda0 by Vitaly Buka
[sanitizer] Don't tie builders with particular workers

This simplifies management of VMs. We don't need to care which
are online. If some is gone we will just see less frequent builds.

Differential Revision: https://reviews.llvm.org/D105227
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)
Commit cef62f035b80b575d0b93b217880503f7558b1f9 by Vitaly Buka
[sanitizer] Missing image is infra issues

This avoids spamming blame list

Differential Revision: https://reviews.llvm.org/D105241
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh (diff)
Commit f4f163eefefeb65c22cf2d5c541406d0eefc4b6b by Vitaly Buka
[sanitizer] Set EXE_LINKER_FLAGS same as SHARED_LINKER_FLAGS
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh (diff)

Summary

  1. [MLIR] Fix generateCopyForMemRefRegion (details)
  2. [PowerPC][AIX] Re-generate test aix-framepointer-save-restore.ll. NFC. (details)
  3. [clang] Fix UB when string.front() is used for the empty string (details)
  4. Recommit "[AArch64] Custom lower <4 x i8> loads" (details)
  5. [mlir][llvm] Add a test for memref.copy lowering to llvm (details)
  6. [ARM][NFC] Remove an unused method (details)
  7. [mlir][linalg][python] Explicit shape and dimension order in OpDSL. (details)
  8. [ARMInstPrinter] Print the target address of a branch instruction (details)
  9. [analyzer][satest][NFC] Relax dependencies requirements (details)
  10. [TableGen] Allow identical MnemonicAliases with no predicate (details)
  11. [MTE] Remove redundant helper function. (details)
  12. [NFC] Rename shadowed variable in InnerLoopVectorizer::createInductionVariable (details)
  13. [hwasan] Make sure we retag with a new tag on free. (details)
  14. [ConstantRanges] Use APInt for constant case for urem/srem. (details)
  15. [AMDGPU] Simplify getReservedNumSGPRs (details)
  16. [clang] NFC: add line break at the end of if expressions (details)
  17. [OPENMP]Fix PR50929: Ignored initializer clause in user-defined reduction. (details)
  18. Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. (details)
  19. [clang-offload-bundler] Add unbundling of archives containing bundled object files into device specific archives (details)
  20. [mlir][linalg][python] Update the OpDSL doc (NFC). (details)
  21. [TargetLowering][AArch64][SVE] Take into account accessed type when clamping address (details)
  22. [LLD][ELF][ARM] Fix case of patched unrelocated BLX (details)
  23. [AMDGPU] PHI node cost should not be counted for the size and latency. (details)
  24. [LLD][ELF][ARM] Tidy up test to hook up missing filecheck patterns [NFC] (details)
  25. [Matrix] Add tests for hoisting address computations. (details)
  26. [MLIR] Eliminate unnecessary affine stores (details)
  27. [OpenMP] Add additional remarks for OpenMPOpt (details)
  28. [clang][patch] Add builtin __arithmetic_fence and option fprotect-parens (details)
  29. [MLIR][SCF] Inline ExecuteRegion if parent can contain multiple blocks (details)
  30. [MLIR] Update description of SCF.execute_region op (details)
  31. Revert "[Coroutine] Add statistics for the number of elided coroutine" (details)
  32. [CostModel][X86] Adjust fp<->int vXi32 AVX1+ costs based on llvm-mca reports (details)
  33. [hwasan] Add missing newline in report. (details)
  34. [lit] Add the ability to parse regexes in Lit boolean expressions (details)
  35. [ARM] Fix incorrect assignment of Changed variable in MVEGatherScatterLowering::optimiseOffsets. (details)
  36. [libc++] Remove broken links and outdated information in the docs (details)
  37. [test] precommit a test for missing (0 /u %x) SCEV fold (details)
  38. [SCEV] Fold (0 udiv %x) to 0 (details)
  39. [clangd] Correct SelectionTree behavior around anonymous field access. (details)
  40. [clangd] Log feature configuration (linux+asan+grpc) of the clangd build (details)
  41. [clangd] Show padding following a field on field hover. (details)
  42. [OpenMP] Change analysis remarks to not emit on cold functions (details)
  43. [LiveDebugValues][InstrRef][1/2] Recover more clobbered variable locations (details)
  44. [gn build] Port 0c96a92d8666 (details)
  45. [mlir][VectorToGPU] Support converting vetor.broadcast to MMA op (details)
  46. [mlir] Fix wrong type in WmmaConstantOpToNVVMLowering (details)
  47. [lldb] Replace SVE_PT* macros in NativeRegisterContextLinux_arm64.{cpp,h} with their equivalent defintions in LinuxPTraceDefines_arm64sve.h (details)
  48. [clangd] Fix highlighting for implicit ObjC property refs (details)
  49. [ELF] -pie: produce dynamic relocations for absolute relocations referencing undef weak (details)
  50. [clangd] Unbreak mac build after 0c96a92d8666b8 (details)
  51. [gn build] add dep needed after b56e5f8a10c1e (details)
  52. [AMDGPU] Add builtin functions image_bvh_intersect_ray (details)
  53. [NPM] Resolve llvmGetPassPluginInfo to the plugin being loaded (details)
  54. [instcombine] umin(x, 1) == zext(x != 0) (details)
  55. [libc] Fix feclearexcept for x86_64. (details)
  56. [instcombine] Precommit tests for umin(a,b) ne/eq 0 fold (details)
  57. [libc] Clear all exceptions before setting in fesetexceptflag. (details)
  58. [libc] Allow reading and writing __FE_DENORM if available on x86_64. (details)
  59. [InstCombine][test] add tests for icmp with constant and offset; NFC (details)
  60. [InstCombine] fold icmp of offset value with constant (details)
  61. [X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760) (details)
  62. [AIX][XCOFF][BUG-Fixed] need to switch back to text section after emit a dumy eh structure (details)
  63. Fix shared build. (details)
  64. [ARM] Set the immediate cost of GEP operands to 0 (details)
  65. [clang][Fuchsia] Remove relative-vtables multilibs (details)
  66. [ELF] Preserve section order within an INSERT AFTER command (details)
  67. Add linalg.batch_matvec named op (details)
  68. [Coroutines] Add the newly generated SCCs back to the CGSCC work queue after CoroSplit actually happened (details)
  69. [AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants (details)
  70. autogen two tests for ease of update (details)
  71. [gn build] (manually) port f617ab104451 (DoublerPlugin) (details)
  72. [gn build] Port 381ded345bdd (details)
  73. [BasicAA] Add test for incorrectly inferring noalias due to scale sign. (details)
  74. [BasicAA] Use separate scale variable for GCD. (details)
  75. [mlir][tosa] Use 3D tensors in tosa.matmul (details)
  76. [GISel] Support llvm.memcpy.inline (details)
  77. [OpenMP][Offloading] Replace all calls to `isSPMDMode` with `__kmpc_is_spmd_exec_mode` (details)
  78. [Orc] Fix name of LLVMOrcIRTransformLayerSetTransform (details)
  79. [Orc] Run the examples as part of the tests (details)
  80. [CMake] Don't use -Bsymbolic-functions for MinGW targets (details)
  81. [libc][NFC] Clear all exceptions in exception_flags_test before raising another. (details)
  82. CodeGen: Print/parse LLTs in MachineMemOperands (details)
  83. [clangd][nfc] Show more information in logs when compiler instance prepare fails (details)
  84. [MCStreamer]  Move emission of attributes section into MCELFStreamer (details)
  85. AMDGPU/GlobalISel: Remove some problematic testcases (details)
  86. GlobalISel: Preserve memory type when reducing load/store width (details)
  87. GlobalISel: Lower non-byte loads and stores (details)
  88. [libomptarget][amdgpu][nfc] Fix build warnings, drop some headers (details)
  89. Add dumping support for RequiresExpr. (details)
  90. [Clang] allow overriding -fbasic-block-sections (details)
  91. [libc++] graph_header_deps.py: Detect files that include themselves. (details)
  92. [libomptarget][nfc] Replace out arguments with struct return (details)
  93. GlobalISel: Use LLT in memory legality queries (details)
  94. [LiveDebugValues][InstrRef][2/2] Emit entry value variable locations (details)
  95. [libc][NFC] Remove few deprecated FPUtil header files and test patterns. (details)
  96. [lld-macho] -section_rename should work on synthetic sections too (details)
  97. [lld-macho] Only enable `__DATA_CONST` for newer platforms (details)
  98. [InstCombine][test] add tests for icmp ult with constant and offset; NFC (details)
  99. [InstCombine] fold icmp ult of offset value with constant (details)
  100. [mlir][vector] Extend vector distribution to all elementwise and contract (details)
  101. [Bazel] Update README with examples (details)
  102. [Bazel] Rework LLVM target selection (details)
  103. Fix test following Clang change ef227b3. (details)
  104. Reapply "[M68k][GloballSel] Formal arguments lowering in IRTranslator" (details)
  105. Revert "[libomptarget] [amdgpu] Fix default setting of max flat workgroup size" (details)
  106. Add a target triple to fix failures on MS build bots. (details)
  107. [AArch64] Remove unneeded ExternalSymbolSDNode code for machine constraint "S". NFC (details)
  108. [mlir][tensor] Add tensor.dim operation (details)
  109. [AArch64][SVEIntrinsicOpts] Convect cntb/h/w/d to vscale intrinsic or constant. (details)
  110. [clang][AArch64][SVE] Handle PRValue under VLAT <-> VLST cast (details)
  111. [Bazel] add missing load to submodule example (details)
  112. [llvm-objdump/mac] Print symbols at the same address deterministically (details)
  113. [Coroutine] Recommit Add statistics for the number of elided coroutine (details)
  114. [ORC] Rename TargetProcessControl to ExecutorProcessControl. NFC. (details)
  115. [scudo] GWP_ASAN runs on untagged pointers (details)
  116. [GWP_ASAN] Enable ARM tests (details)
  117. [gn build] Port 662c55442f17 (details)
  118. [Compiler-rt] Add delete for noncopyable (details)
  119. [hexagon] Add {hvx,}hexagon_{protos,circ_brev...} (details)
  120. [gn build] Port 28b01c59c93d (details)
  121. Fail gracefully if no inlining model is available to download. (details)
  122. Add list of LWG papers accepted by WG21 during the June 2021 plenary (details)
Commit 071d26f8082391612f3a3f71b1135cbdceb0a30a by uday
[MLIR] Fix generateCopyForMemRefRegion

Fix generateCopyForMemRefRegion for a missing check: in some cases, when
the thing to generate copies for itself is empty, no fast buffer/copy
loops would have been allocated/generated. Add an extra assertion there
while at this.

Differential Revision: https://reviews.llvm.org/D105170
The file was modifiedmlir/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedmlir/test/Dialect/Affine/affine-data-copy.mlir
Commit 1f169a774cb865659cefe085e70a56a884e3711e by lkail
[PowerPC][AIX] Re-generate test aix-framepointer-save-restore.ll. NFC.
The file was modifiedllvm/test/CodeGen/PowerPC/aix-framepointer-save-restore.ll
Commit fceaf8621179aa758c44f3eaee02d789abfd455b by dmitry.polukhin
[clang] Fix UB when string.front() is used for the empty string

Compilation database might have empty string as a command line argument.
But ExpandResponseFilesDatabase::expand doesn't expect this and assumes
that string.front() can be used for any argument. It is undefined behaviour if
string is empty. With debug build mode it causes crash in clangd.

Test Plan: check-clang

Differential Revision: https://reviews.llvm.org/D105120
The file was modifiedclang/lib/Tooling/ExpandResponseFilesCompilationDatabase.cpp
The file was modifiedclang/unittests/Tooling/CompilationDatabaseTest.cpp
Commit b062fff87adcfa2e252cbce43d92b61b76614bd5 by sjoerd.meijer
Recommit "[AArch64] Custom lower <4 x i8> loads"

This recommits D104782 including a fix for adding a wrong operand to the new
load node.

Differential Revision: https://reviews.llvm.org/D105110
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-load-ext.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat_vec.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/usub_sat_vec.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-vshift.ll
The file was removedllvm/test/CodeGen/AArch64/neon-extload.ll
The file was modifiedllvm/test/CodeGen/AArch64/uadd_sat_vec.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat_vec.ll
Commit db2de8d7f1eb37f5a7c1d2de61cdd9d79647ea78 by herhut
[mlir][llvm] Add a test for memref.copy lowering to llvm

This was missing and also there was a bug in the lowering itself, which went unnoticed due to it.

Differential Revision: https://reviews.llvm.org/D105122
The file was addedmlir/test/mlir-cpu-runner/copy.mlir
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/FunctionCallUtils.cpp
Commit 17bcae8906949374495fb396b0baf540feafb1a5 by ikudrin
[ARM][NFC] Remove an unused method

`ARMInstPrinter::printMveAddrModeQOperand()` was added in D62680, but
was never used. It looks like `printT2AddrModeImm8Operand<false>()` is
used instead.

Differential Revision: https://reviews.llvm.org/D105124
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
Commit 4361bd9b7b38c73b69f9a37e52d0b72989e84947 by gysit
[mlir][linalg][python] Explicit shape and dimension order in OpDSL.

Extend the OpDSL syntax with an optional `domain` function to specify an explicit dimension order. The extension is needed to provide more control over the dimension order instead of deducing it implicitly depending on the formulation of the tensor comprehension. Additionally, the patch also ensures the symbols are ordered according to the operand definitions of the operation.

Differential Revision: https://reviews.llvm.org/D105117
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/lang/config.py
The file was modifiedmlir/test/python/dialects/linalg/opdsl/shape_maps_iteration.py
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
The file was modifiedmlir/test/python/dialects/linalg/opdsl/interfaces.py
The file was modifiedmlir/test/python/dialects/linalg/opdsl/arguments.py
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/lang/dsl.py
The file was modifiedmlir/test/python/dialects/linalg/opdsl/emit_structured_generic.py
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
Commit 657e067bb58c585400d62d6b260301ca0fdb7b48 by ikudrin
[ARMInstPrinter] Print the target address of a branch instruction

This follows other patches that changed printing immediate values of
branch instructions to target addresses, see D76580 (x86), D76591 (PPC),
D77853 (AArch64).

As observing immediate values might sometimes be useful, they are
printed as comments for branch instructions.

// llvm-objdump -d output (before)
000200b4 <_start>:
   200b4: ff ff ff fa   blx     #-4 <thumb>
000200b8 <thumb>:
   200b8: ff f7 fc ef   blx     #-8 <_start>

// llvm-objdump -d output (after)
000200b4 <_start>:
   200b4: ff ff ff fa   blx     0x200b8 <thumb>         @ imm = #-4
000200b8 <thumb>:
   200b8: ff f7 fc ef   blx     0x200b4 <_start>        @ imm = #-8

// GNU objdump -d.
000200b4 <_start>:
   200b4:       faffffff        blx     200b8 <thumb>
000200b8 <thumb>:
   200b8:       f7ff effc       blx     200b4 <_start>

Differential Revision: https://reviews.llvm.org/D104701
The file was modifiedlld/test/COFF/delayimports-armnt.yaml
The file was modifiedlld/test/ELF/arm-branch-rangethunk.s
The file was modifiedlld/test/ELF/arm-thunk-multipass.s
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
The file was modifiedllvm/test/tools/llvm-objdump/ELF/ARM/invalid-instruction.s
The file was modifiedlld/test/ELF/arm-fix-cortex-a8-thunk.s
The file was modifiedlld/test/ELF/arm-thumb-interwork-thunk-v5.s
The file was modifiedlld/test/COFF/arm-thumb-thunks-multipass.s
The file was modifiedlld/test/ELF/arm-bl-v6-inrange.s
The file was modifiedllvm/test/MC/ARM/coff-relocations.s
The file was modifiedllvm/test/MC/ARM/thumb1-relax-bcc.s
The file was modifiedllvm/test/MC/ARM/branch-disassemble.s
The file was modifiedllvm/test/tools/llvm-objdump/ELF/ARM/branch-symbols.s
The file was modifiedlld/test/ELF/arm-bl-v6.s
The file was modifiedlld/test/ELF/arm-fix-cortex-a8-blx.s
The file was modifiedlld/test/ELF/arm-fix-cortex-a8-nopatch.s
The file was modifiedlld/test/ELF/arm-blx.s
The file was modifiedlld/test/ELF/arm-long-thunk-converge.s
The file was modifiedllvm/test/CodeGen/ARM/Windows/division-range.ll
The file was modifiedlld/test/ELF/arm-gnu-ifunc.s
The file was modifiedlld/test/ELF/arm-thunk-re-add.s
The file was modifiedlld/test/ELF/arm-fix-cortex-a8-plt.s
The file was modifiedlld/test/ELF/arm-thumb-interwork-thunk.s
The file was modifiedlld/test/ELF/arm-thunk-multipass-plt.s
The file was modifiedlld/test/ELF/arm-thumb-undefined-weak.s
The file was modifiedlld/test/ELF/arm-fix-cortex-a8-thunk-align.s
The file was modifiedlld/test/ELF/arm-thunk-linkerscript-large.s
The file was modifiedlld/test/ELF/arm-thunk-linkerscript-sort.s
The file was modifiedlld/test/COFF/arm-thumb-thunks.s
The file was modifiedlld/test/ELF/arm-force-pi-thunk.s
The file was modifiedllvm/test/tools/llvm-objdump/ELF/ARM/tblxi-target.s
The file was modifiedlld/test/ELF/arm-branch-undef-weak-plt-thunk.s
The file was modifiedlld/test/ELF/arm-thumb-mix-range-thunk-os.s
The file was modifiedllvm/test/MC/ARM/thumb2-b.w-target.s
The file was modifiedlld/test/ELF/arm-gnu-ifunc-plt.s
The file was modifiedlld/test/ELF/arm-extreme-range-pi-thunk.s
The file was modifiedlld/test/ELF/arm-thumb-interwork-shared.s
The file was modifiedllvm/test/MC/ARM/thumb2-cbn-to-next-inst.s
The file was modifiedllvm/test/tools/llvm-objdump/ELF/ARM/unknown-instr.test
The file was modifiedlld/test/ELF/arm-plt-reloc.s
The file was modifiedlld/test/ELF/arm-fix-cortex-a8-recognize.s
The file was modifiedlld/test/ELF/arm-thumb-branch.s
The file was modifiedlld/test/ELF/arm-thumb-plt-reloc.s
The file was modifiedlld/test/ELF/arm-thumb-undefined-weak-narrow.test
The file was modifiedlld/test/ELF/arm-thumb-condbranch-thunk.s
The file was modifiedlld/test/ELF/arm-branch.s
The file was modifiedllvm/test/MC/ARM/thumb-cb-thumbfunc.s
The file was modifiedllvm/test/MC/Disassembler/ARM/mve-lol.txt
The file was modifiedllvm/test/MC/ARM/arm-macho-calls.s
The file was modifiedlld/test/ELF/arm-thunk-linkerscript.s
The file was modifiedlld/test/ELF/arm-thumb-interwork-notfunc.s
The file was modifiedlld/test/ELF/arm-thumb-thunk-v6m.s
The file was modifiedlld/test/ELF/arm-thumb-range-thunk-os.s
The file was modifiedlld/test/ELF/arm-thunk-linkerscript-dotexpr.s
The file was modifiedlld/test/COFF/armnt-branch24t.test
The file was modifiedlld/test/ELF/arm-thumb-plt-range-thunk-os.s
The file was modifiedlld/test/ELF/arm-undefined-weak.s
The file was modifiedlld/test/COFF/armnt-blx23t.test
The file was modifiedllvm/test/MC/ARM/thumb1-relax-br.s
The file was modifiedlld/test/ELF/arm-thunk-largesection.s
The file was modifiedlld/test/ELF/arm-thunk-arm-thumb-reuse.s
The file was modifiedlld/test/ELF/arm-thumb-thunk-empty-pass.s
The file was modifiedlld/test/ELF/arm-exidx-canunwind.s
The file was modifiedlld/test/ELF/arm-thumb-interwork-abs.s
The file was modifiedlld/test/ELF/arm-thunk-linkerscript-orphan.s
The file was modifiedlld/test/ELF/arm-exidx-gc.s
The file was modifiedlld/test/ELF/arm-thumb-no-undefined-thunk.s
The file was modifiedlld/test/ELF/arm-thumb-interwork-ifunc.s
The file was modifiedlld/test/ELF/arm-thunk-nosuitable.s
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
The file was modifiedlld/test/ELF/arm-thumb-narrow-branch-check.s
The file was modifiedlld/test/ELF/arm-thunk-many-passes.s
Commit c818cb96ad4aa65bceadc72199677c852e8c22bd by vsavchenko
[analyzer][satest][NFC] Relax dependencies requirements
The file was modifiedclang/utils/analyzer/Dockerfile
Commit 2da58826a5e0716163d3b91afcde1218a211d714 by jay.foad
[TableGen] Allow identical MnemonicAliases with no predicate

My use case for this is illustrated in the test case: I want to define
the same instruction twice with different (disjoint) predicates, because
the instruction has different operands on different subtargets. It's
convenient to do this with a multiclass that also defines an alias for
the instruction.

Previously tablegen would complain if this alias was defined twice with
no predicate. One way to fix this would be to add a predicate on each
definition of the alias, matching the predicate on the instruction. But
this (a) is slightly awkward to do in the real world use case I had, and
(b) leads to an inefficient matcher that will do something like this:

  if (Mnemonic == "foo_alias") {
    if (Features.test(Feature_Subtarget1Bit))
      Mnemonic == "foo";
    else if (Features.test(Feature_Subtarget2Bit))
      Mnemonic == "foo";
    return;
  }

It would be more efficient to skip the feature tests and return "foo"
unconditionally.

Overall it seems better to allow multiple definitions of the identical
alias with no predicate.

Differential Revision: https://reviews.llvm.org/D105033
The file was addedllvm/test/TableGen/MnemonicAlias.td
The file was modifiedllvm/utils/TableGen/AsmMatcherEmitter.cpp
Commit a24f104645f3faf4d0e4ea6047f933caddb85de5 by fmayer
[MTE] Remove redundant helper function.

Looking at PostDominatorTree::dominates, we can see that has the same
logic (with the addition of handling Phi nodes - which are not used as inputs in
this pass) as the helper function.

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D105141
The file was modifiedllvm/lib/Target/AArch64/AArch64StackTagging.cpp
Commit 7b7b5b5a2669ff40882c1a5e1d92a75e15b925c4 by david.sherwood
[NFC] Rename shadowed variable in InnerLoopVectorizer::createInductionVariable

Avoid creating a IRBuilder stack variable with the same name as the
class member.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit ad8494c021d711779900bf63f01423f615b413a4 by fmayer
[hwasan] Make sure we retag with a new tag on free.

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D105021
The file was modifiedcompiler-rt/lib/hwasan/hwasan_allocator.cpp
Commit 611a02cce509d304ebf66054b7816f1e0b5a792c by flo
[ConstantRanges] Use APInt for constant case for urem/srem.

Currently UREM & SREM on constant ranges produces overly pessimistic
results for single element constant ranges.

Delegate to APInt's implementation if both operands are single element
constant ranges. We already do something similar for other binary
operators, like binary AND.

Fixes PR49731.

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D105115
The file was modifiedllvm/test/Transforms/SCCP/binaryops-range-special-cases.ll
The file was modifiedllvm/lib/IR/ConstantRange.cpp
Commit a7ed55f64c5fdce9af3257458779402fb9de1f8b by Madhur.Amilkanthwar
[AMDGPU] Simplify getReservedNumSGPRs

This is a followup patch on D103636 where
it seemed checking on amdgpu-calls and
amdgpu-stack-objects is unnecessary. Removing these
checks didn't regress any tests functionally.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D104513
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
Commit 2fd75507d1855300d0a59451337d0a55b081887c by pengfei.wang
[clang] NFC: add line break at the end of if expressions

Hi,

In function TransformTemplateArgument,
would it be better to add line break at the end of "if" expressions?

I use clang-format to do the job for me.

Thanks a lot

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D104604
The file was modifiedclang/lib/Sema/TreeTransform.h
Commit 7fab1146e42ca76a78cccd0aa274168c628d01de by a.bataev
[OPENMP]Fix PR50929: Ignored initializer clause in user-defined reduction.

No need to try to create the default constructor for private copy, it
will be called automatically in the initializer of the declare
reduction. Fixes balance between constructors/destructors calls.

Differential Revision: https://reviews.llvm.org/D105143
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/test/OpenMP/for_reduction_codegen_UDR.cpp
Commit fcd0cb39214e5abc89bfb1926397fe668172ecaa by llvm-dev
Fix MSVC "32-bit shift implicitly converted to 64 bits" warning.
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
Commit f7ce532d622dc26eddd25f87faec0ff35dc0c2e9 by Saiyedul.Islam
[clang-offload-bundler] Add unbundling of archives containing bundled object files into device specific archives

This patch adds unbundling support of an archive file. It takes an
archive file along with a set of offload targets as input.
Output is a device specific archive for each given offload target.
Input archive contains bundled code objects bundled using
clang-offload-bundler. Each generated device specific archive contains
a set of device code object files which are named as
<Parent Bundle Name>-<CodeObject-GPUArch>.

Entries in input archive can be of any binary type which is
supported by clang-offload-bundler, like *.bc. Output archives will
contain files in same type.

Example Usuage:
  clang-offload-bundler --unbundle --inputs=lib-generic.a -type=a
      -targets=openmp-amdgcn-amdhsa--gfx906,openmp-amdgcn-amdhsa--gfx908
      -outputs=devicelib-gfx906.a,deviceLib-gfx908.a

Reviewed By: jdoerfert, yaxunl

Differential Revision: https://reviews.llvm.org/D93525
The file was modifiedclang/test/Driver/clang-offload-bundler.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
The file was modifiedclang/test/Driver/hip-rdc-device-only.hip
The file was modifiedclang/docs/ClangOffloadBundler.rst
The file was modifiedclang/test/Driver/hip-toolchain-rdc-separate.hip
Commit 42d99bc3767644311707c66033b6fc8a4eeba56a by gysit
[mlir][linalg][python] Update the OpDSL doc (NFC).

Update the OpDSL documentation to reflect recent changes. In particular, the updated documentation discusses:
- Attributes used to parameterize index expressions
- Shape-only tensor support
- Scalar parameters

Differential Revision: https://reviews.llvm.org/D105123
The file was modifiedmlir/docs/Tools/LinalgOpDsl.md
Commit 002911503fe29ac30ef0aa0a15b624982814548b by bradley.smith
[TargetLowering][AArch64][SVE] Take into account accessed type when clamping address

When clamping the index for a memory access to a stacked vector we must
take into account the entire type being accessed, not just assume that
we are accessing only a single element.

Differential Revision: https://reviews.llvm.org/D105016
The file was modifiedllvm/test/CodeGen/AArch64/sve-insert-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-extract-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/split-vector-insert.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Commit dd4d3f74062c64d57a5881dceac028ec6c231b73 by peter.smith
[LLD][ELF][ARM] Fix case of patched unrelocated BLX

There are a couple of problems with the code to patch
unrelocated BLX instructions:
1. The calculation of the PC needs to take into account
   the alignment of the instruction. The Thumb BLX
   uses alignDown(PC, 4) for the source address.
2. The calculation of the PC bias is hard-coded to 4
   which works for Thumb, but when there is a BLX the
   branch will be in Arm state so it needs an 8 byte
   PC bias.

No asssembler generates an unrelocated BLX instruction
so these problems do not affect real world programs.
However we should still fix them.

Differential Revision: https://reviews.llvm.org/D104905
The file was modifiedlld/test/ELF/arm-fix-cortex-a8-blx.s
The file was modifiedlld/ELF/ARMErrataFix.cpp
Commit e585b332e42321870b2cf1eeefcd68b0717570e2 by Alexander Timofeev
[AMDGPU] PHI node cost should not be counted for the size and latency.

  Details: https://reviews.llvm.org/D96805 changed the GCNTTIImpl::getCFInstrCost to return 1 for the PHI nodes
  for the TTI::TCK_CodeSize and TTI::TCK_SizeAndLatency. This is incorrect because the value moves that are the
  result of the PHI lowering are inserted into the basic block predecessors - not into the block itself.
  As a result of this change LoopRotate and LoopUnroll were broken because of the incorrect Loop header and loop
  body size/cost estimation.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D105104
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/AMDGPU/control-flow.ll
Commit fc1cb3104b6bde0cbba8e92ec97878076c39737d by peter.smith
[LLD][ELF][ARM] Tidy up test to hook up missing filecheck patterns [NFC]

A couple of filecheck patterns had not been hooked up with
the patterns suffering from some drift. As this test is old
and llvm-objdump has improved a lot, take this opportunity to
hide the instruction encoding. I've also taken out a lot of
the explanatory comments that llvm-objdump improvements make
redundant, as these comments oftern don't get updated when addresses
change.

Differential Revision: https://reviews.llvm.org/D104907
The file was modifiedlld/test/ELF/arm-thumb-interwork-thunk.s
Commit 8db9cb262fa159b2f8742d5652aec45d2c3713b2 by flo
[Matrix] Add tests for hoisting address computations.
The file was addedllvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-dominance.ll
Commit 0cd8422e8caa4aeccbf9b9c92c9acb23a4ffa9c3 by gh
[MLIR] Eliminate unnecessary affine stores

Deduce circumstances where an affine load could not possibly be read by an operation (such as an affine load), and if so, eliminate the load

Differential Revision: https://reviews.llvm.org/D105041
The file was modifiedmlir/lib/Dialect/Affine/Transforms/AffineScalarReplacement.cpp
The file was modifiedmlir/test/Dialect/Affine/scalrep.mlir
Commit 0edb87773b1a086cb5bb960f7f4f6ca815bc8bb4 by huberjn
[OpenMP] Add additional remarks for OpenMPOpt

This patch adds additional remarks, suggesting the use of `noescape` for failed
globalization and indicating when internalization failed.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105150
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
The file was modifiedllvm/test/Transforms/OpenMP/single_threaded_execution.ll
The file was modifiedllvm/test/Transforms/OpenMP/remove_globalization.ll
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
Commit e773216f46368cd927a3c67bfa2516913acb75e7 by melanie.blower
[clang][patch] Add builtin __arithmetic_fence and option fprotect-parens

This patch adds a new clang builtin, __arithmetic_fence. The purpose of the
builtin is to provide the user fine control, at the expression level, over
floating point optimization when -ffast-math (-ffp-model=fast) is enabled.
The builtin prevents the optimizer from rearranging floating point expression
evaluation. The new option fprotect-parens has the same effect on
parenthesized expressions, forcing the optimizer to respect the parentheses.

Reviewed By: aaron.ballman, kpn

Differential Revision: https://reviews.llvm.org/D100118
The file was modifiedclang/include/clang/Basic/TargetInfo.h
The file was modifiedclang/include/clang/Basic/LangOptions.def
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was addedclang/test/AST/arithmetic-fence-builtin.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/include/clang/Basic/Builtins.def
The file was modifiedclang/lib/Basic/Targets/X86.h
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp
The file was modifiedclang/docs/UsersManual.rst
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/lib/Basic/TargetInfo.cpp
The file was addedclang/test/CodeGen/arithmetic-fence-builtin.c
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/lib/AST/ExprConstant.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/include/clang/Driver/Options.td
The file was addedclang/test/Sema/arithmetic-fence-builtin.c
The file was modifiedclang/test/Driver/clang_f_opts.c
Commit dfb34c0df9d00a10f2563e989f257d3736969784 by gh
[MLIR][SCF] Inline ExecuteRegion if parent can contain multiple blocks

The executeregionop is used to allow multiple blocks within SCF constructs. If the container allows multiple blocks, inline the region

Differential Revision: https://reviews.llvm.org/D104960
The file was modifiedmlir/lib/Dialect/SCF/SCF.cpp
The file was modifiedmlir/test/Dialect/SCF/canonicalize.mlir
The file was modifiedmlir/include/mlir/Dialect/SCF/SCFOps.td
Commit ad4152d1b833f4696d6f9deccc021f240bab3d9d by gh
[MLIR] Update description of SCF.execute_region op

See https://reviews.llvm.org/D104865
The file was modifiedmlir/include/mlir/Dialect/SCF/SCFOps.td
Commit db86e5c91477286b6432a75857edf012652c58d9 by thakis
Revert "[Coroutine] Add statistics for the number of elided coroutine"

This reverts commit 1d9539cf49a585e7c3cd8faa1b8e7291e0ce285c.
Test fails in LLVM_ENABLE_ASSERTIONS=OFF builds (such as regular
release builds).
The file was modifiedllvm/lib/Transforms/Coroutines/CoroElide.cpp
The file was modifiedllvm/test/Transforms/Coroutines/coro-elide.ll
Commit 47941d601debe2d543a5f9452c777072c708ccdd by llvm-dev
[CostModel][X86] Adjust fp<->int vXi32 AVX1+ costs based on llvm-mca reports

Based off the worse case numbers generated by D103695, the AVX1/2/512 sitofp/uitofp/fptosi/fptoui costs were higher than necessary (based off instruction counts instead of actual throughput).

The SSE costs still need further fixes, but I hit an issue with the order in which SSE costs are checked - we need to check CUSTOM costs (with non-legal types) first, and then fallback to LEGALIZED types. I'm looking at this now, and this should let us start thinning out a lot of the duplicates in the costs tables.

Then we can finally start work on vXi64 / vXi16 / vXi8 / vXi1 integers, which should let us look at sub-128-bit vectorization (D103925).
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/uitofp.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/cast.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fptosi.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/sitofp.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fptoui.ll
Commit 90f244c8432357337a12b2582b20e2aedeb3e742 by fmayer
[hwasan] Add missing newline in report.

Reviewed By: glider

Differential Revision: https://reviews.llvm.org/D105190
The file was modifiedcompiler-rt/lib/hwasan/hwasan_report.cpp
Commit fec521a7b206815ad995f7247e671a8f25d144fc by Louis Dionne
[lit] Add the ability to parse regexes in Lit boolean expressions

This patch augments Lit with the ability to parse regular expressions
in boolean expressions. This includes REQUIRES:, XFAIL:, UNSUPPORTED:,
and all other special Lit markup that evaluates to a boolean expression.

Regular expressions can be specified by enclosing them in {{...}},
similarly to how FileCheck handles such regular expressions. The regular
expression can either be on its own, or it can be part of an identifier.
For example, a match expression like {{.+}}-apple-darwin{{.+}} would match
the following variables:

     x86_64-apple-darwin20.0
     arm64-apple-darwin20.0
     arm64-apple-darwin22.0
     etc...

In the long term, this could be used to remove the need to handle the
target triple specially when parsing boolean expressions.

Differential Revision: https://reviews.llvm.org/D104572
The file was modifiedllvm/utils/lit/tests/show-used-features.py
The file was modifiedllvm/utils/lit/lit/BooleanExpression.py
The file was modifiedllvm/utils/lit/tests/Inputs/show-used-features/mixed.txt
The file was modifiedllvm/utils/lit/lit/Test.py
The file was modifiedllvm/docs/TestingGuide.rst
Commit 0f1f92156f3caafe9567b853ecb57212b709e68d by craig.topper
[ARM] Fix incorrect assignment of Changed variable in MVEGatherScatterLowering::optimiseOffsets.

I believe this Changed flag should be initialized to false,
otherwise the if (!Changed) is always dead. This doesn't
manifest in a functional issue because the PHINode checks will
fail if nothing changed. They are identical to the earlier
checks that must have already failed to get into this else block.

While there remove an else after return to reduce indentation.

Differential Revision: https://reviews.llvm.org/D105159
The file was modifiedllvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
Commit c69cfbfd71626e0ebcfc1fc79014ee0fea25103b by Louis Dionne
[libc++] Remove broken links and outdated information in the docs

The various design docs have been moved to RST, and the linked blog post
does not apply anymore since libc++ is the default library used by Clang
on Apple platforms.
The file was modifiedlibcxx/docs/index.rst
Commit 5e630a9202a363aae37e4e10655e894490f150f9 by listmail
[test] precommit a test for missing (0 /u %x) SCEV fold
The file was modifiedllvm/test/Analysis/ScalarEvolution/fold.ll
Commit 14d8f1546a0483ef54a7a09442848d0a470c94c0 by listmail
[SCEV] Fold (0 udiv %x) to 0

We have analogous rules in instsimplify, etc.., but were missing the same in SCEV.  The fold is near trivial, but came up in the context of a larger change.
The file was modifiedllvm/test/Analysis/ScalarEvolution/fold.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit bb41f8569138f9f87baf7f4b4e26b3cdcdfd42c6 by sam.mccall
[clangd] Correct SelectionTree behavior around anonymous field access.

struct A { struct { int b; }; };
A().^b;

This should be considered a reference to b, but currently it's
considered a reference to the anonymous struct field.

Fixes https://github.com/clangd/clangd/issues/798

Differential Revision: https://reviews.llvm.org/D104376
The file was modifiedclang-tools-extra/clangd/Selection.cpp
The file was modifiedclang-tools-extra/clangd/unittests/XRefsTests.cpp
Commit 0c96a92d8666b8eb69eb1275aed572f857182d9a by sam.mccall
[clangd] Log feature configuration (linux+asan+grpc) of the clangd build

Included in logs, --version, remote index queries, and LSP serverInfo.

Differential Revision: https://reviews.llvm.org/D100553
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/unittests/ConfigCompileTests.cpp
The file was modifiedclang-tools-extra/clangd/tool/ClangdMain.cpp
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
The file was addedclang-tools-extra/clangd/Features.h
The file was modifiedclang-tools-extra/clangd/index/remote/Client.cpp
The file was modifiedclang-tools-extra/clangd/index/remote/server/Server.cpp
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.h
The file was modifiedclang-tools-extra/clangd/Features.inc.in
The file was addedclang-tools-extra/clangd/Features.cpp
The file was modifiedclang-tools-extra/clangd/ConfigCompile.cpp
Commit b447445eaa6f8ff826a7eab276c10bc6f133aeb0 by sam.mccall
[clangd] Show padding following a field on field hover.

This displays as: `Size: 4 bytes (+4 padding)`

Also stop showing (byte) offset/size for bitfields. They're not
meaningful and using them to calculate padding is dangerous!

Differential Revision: https://reviews.llvm.org/D98377
The file was modifiedclang-tools-extra/clangd/Hover.h
The file was modifiedclang-tools-extra/clangd/unittests/HoverTests.cpp
The file was modifiedclang-tools-extra/clangd/Hover.cpp
Commit ecabc6684f23cb65925d62fac9a14ab52d07951a by huberjn
[OpenMP] Change analysis remarks to not emit on cold functions

The remarks will trigger on some functions that are marked cold, such as the
`__muldc3` intrinsic functions. Change the remarks to avoid these functions.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105196
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
The file was modifiedllvm/test/Transforms/OpenMP/single_threaded_execution.ll
Commit 49555441628a0ec620581bba371e6bb20c2b3f5f by jeremy.morse
[LiveDebugValues][InstrRef][1/2] Recover more clobbered variable locations

In various circumstances, when we clobber a register there may be
alternative locations that the value is live in. The classic example would
be a value loaded from the stack, and then clobbered: the value is still
available on the stack. InstrRefBasedLDV was coping with this at block
starts where it's forced to pick a location, however it wasn't searching
for alternative locations when values were clobbered.

This patch notifies the "Transfer Tracker" object when clobbers occur, and
it's able to find alternatives and issue DBG_VALUEs for that location. See:
the added test.

Differential Revision: https://reviews.llvm.org/D88405
The file was modifiedllvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
The file was addedllvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
The file was modifiedllvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
Commit 0596f7d828436e7db85154f2815eb3ff32d505af by llvmgnsyncbot
[gn build] Port 0c96a92d8666
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit 439284194959a896eab273c5c2cda2b983aa85af by thomasraoux
[mlir][VectorToGPU] Support converting vetor.broadcast to MMA op

Differential Revision: https://reviews.llvm.org/D105175
The file was modifiedmlir/test/Conversion/VectorToGPU/vector-to-mma-ops.mlir
The file was modifiedmlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
Commit 0298f2cfb1df80741a08fb7cd1eec9da70ed3441 by thomasraoux
[mlir] Fix wrong type in WmmaConstantOpToNVVMLowering

InsertElement takes a scalar integer attribute not an array of integer.

Differential Revision: https://reviews.llvm.org/D105174
The file was modifiedmlir/test/Conversion/GPUToNVVM/wmma-ops-to-nvvm.mlir
The file was modifiedmlir/lib/Conversion/GPUToNVVM/WmmaOpsToNvvm.cpp
Commit 05915400b7f9933b95686116f2dc1370e7f96cfb by cmtice
[lldb] Replace SVE_PT* macros in NativeRegisterContextLinux_arm64.{cpp,h} with their equivalent defintions in LinuxPTraceDefines_arm64sve.h

Commit 090306fc80dbf (August 2020) changed most of the arm64 SVE_PT*
macros, but apparently did not make the changes in the
NativeRegisterContextLinux_arm64.* files (or those files were pulled
over from someplace else after that commit). This change replaces the
macros NativeRegisterContextLinux_arm64.cpp with the replacement
definitions in LinuxPTraceDefines_arm64sve.h. It also includes
LinuxPTraceDefines_arm64sve.h in NativeRegisterContextLinux_arm64.h.

Differential Revision: https://reviews.llvm.org/D104826
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
The file was modifiedlldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
Commit 570984204f24c326699dedcc05793b77b013f068 by davg
[clangd] Fix highlighting for implicit ObjC property refs

Objective-C lets you use the `self.prop` syntax as sugar for both
`[self prop]` and `[self setProp:]`, but clangd previously did not
provide a semantic token for `prop`.

Now, we provide a semantic token, treating it like a normal property
except it's backed by a `ObjCMethodDecl` instead of a
`ObjCPropertyDecl`.

Differential Revision: https://reviews.llvm.org/D104117
The file was modifiedclang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp
The file was modifiedclang-tools-extra/clangd/SemanticHighlighting.cpp
Commit 7b06bfc49ec9d560fa50996ecf7f16b7c2f47c9d by i
[ELF] -pie: produce dynamic relocations for absolute relocations referencing undef weak

See the comment for my understanding of -no-pie and -shared expectation.
-no-pie has freedom on choices. We choose dynamic relocations to be consistent
with the handling of GOT-generating relocations.

Note: GNU ld has arch-varying behaviors and its x86 -pie has a very
complex rule:
if there is at least one GOT-generating or PLT-generating relocation and
-z dynamic-undefined-weak (enabled by default) is in effect, generate a
dynamic relocation.

We don't emulate its rule.

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D105164
The file was modifiedlld/ELF/Relocations.cpp
The file was modifiedlld/test/ELF/weak-undef-rw.s
Commit b56e5f8a10c1ec4fd3750bdd269fbad778820326 by thakis
[clangd] Unbreak mac build after 0c96a92d8666b8

That commit removed the include of Features.inc from ClangdLSPServer.h,
but ClangdMain.cpp relied on this include to pull in Features.inc for
the #if at the bottom of Transport.h.

Since the include is needed in Transport.h, just add it to there
directly.
The file was modifiedclang-tools-extra/clangd/Transport.h
Commit f6db88535cb4c47bec8cf117f549f4ad27dcd6d6 by thakis
[gn build] add dep needed after b56e5f8a10c1e
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/xpc/BUILD.gn
Commit 434bd5bf5479615ea42e64a80ff994059f31f5f4 by Yaxun.Liu
[AMDGPU] Add builtin functions image_bvh_intersect_ray

Reviewed by: Stanislav Mekhanoshin, Matt Arsenault

Differential Revision: https://reviews.llvm.org/D104946
The file was modifiedclang/include/clang/Basic/BuiltinsAMDGPU.def
The file was addedclang/test/CodeGenOpenCL/builtins-amdgcn-raytracing.cl
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
Commit f617ab10445148ae44d67484f9dc9486efcfbcc8 by tomas.matheson
[NPM] Resolve llvmGetPassPluginInfo to the plugin being loaded

Dynamically loaded plugins for the new pass manager are initialised by
calling llvmGetPassPluginInfo. This is defined as a weak symbol so that
it is continually redefined by each plugin that is loaded. When loading
a plugin from a shared library, the intention is that
llvmGetPassPluginInfo will be resolved to the definition in the most
recent plugin. However, using a global search for this resolution can
fail in situations where multiple plugins are loaded.

Currently:

* If a plugin does not define llvmGetPassPluginInfo, then it will be
  silently resolved to the previous plugin's definition.

* If loading the same plugin twice with another in between, e.g. plugin
  A/plugin B/plugin A, then the second load of plugin A will resolve to
  llvmGetPassPluginInfo in plugin B.

* The previous case can also occur when a dynamic library defines both
  NPM and legacy plugins; the legacy plugins are loaded first and then
  with `-fplugin=A -fpass-plugin=B -fpass-plugin=A`: A will be loaded as
  a legacy plugin and define llvmGetPassPluginInfo; B will be loaded
  and redefine it; and finally when A is loaded as an NPM plugin it will
  be resolved to the definition from B.

Instead of searching globally, restrict the symbol lookup to the library
that is currently being loaded.

Differential Revision: https://reviews.llvm.org/D104916
The file was modifiedllvm/unittests/Passes/TestPlugin.cpp
The file was modifiedllvm/unittests/Passes/CMakeLists.txt
The file was addedllvm/unittests/Passes/DoublerPlugin.cpp
The file was modifiedllvm/lib/Passes/PassPlugin.cpp
The file was modifiedllvm/unittests/Passes/PluginsTest.cpp
Commit c4fc2cb5b2d98125e9035d9498640c7d6f17c8da by listmail
[instcombine] umin(x, 1) == zext(x != 0)

We already implemented this for the select form, but the intrinsic form was missing.  Note that this doesn't change poison behavior as 1 is non-poison, and the optimized form is still poison exactly when x is.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/minmax-intrinsics.ll
Commit 9474ddc3ac8637596f87dd796864353317622672 by sivachandra
[libc] Fix feclearexcept for x86_64.

Previously, feclearexcept cleared all exceptions irrespective of the
argument. This change brings it in line with the aarch64 flavors wherein
only those exceptions listed in the argument will be cleared.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D105081
The file was modifiedlibc/test/src/fenv/CMakeLists.txt
The file was modifiedlibc/utils/FPUtil/x86_64/FEnv.h
The file was addedlibc/test/src/fenv/feclearexcept_test.cpp
Commit 0c2f40f91622c57ff343a47594bd84a747afe6e3 by listmail
[instcombine] Precommit tests for umin(a,b) ne/eq 0 fold
The file was modifiedllvm/test/Transforms/InstCombine/minmax-intrinsics.ll
Commit 804dc3dcf27d10d4cd0af06fdf2999ea81ba751f by sivachandra
[libc] Clear all exceptions before setting in fesetexceptflag.

Previously, exceptions from the flag were being added. This patch
changes it such that only the exceptions in the flag will be set.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D105085
The file was modifiedlibc/src/fenv/fesetexceptflag.cpp
The file was modifiedlibc/test/src/fenv/exception_flags_test.cpp
Commit 230df8a419f244827895ffe5b6db298a209b741a by sivachandra
[libc] Allow reading and writing __FE_DENORM if available on x86_64.

Some libcs define __FE_DENORM on x86_64. This change allows reading the
bits corresponding to that non-standard exception.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D105004
The file was modifiedlibc/utils/FPUtil/x86_64/FEnv.h
Commit 36bd25db3dd5b76f3ab31fc95bd04f18a8af6347 by spatel
[InstCombine][test] add tests for icmp with constant and offset; NFC
The file was modifiedllvm/test/Transforms/InstCombine/icmp-add.ll
Commit c7b658aeb526c3e68b0cea89f0746f45b5366827 by spatel
[InstCombine] fold icmp of offset value with constant

There must be a better way to describe this pattern in words?
(X + C2) >u C --> X <s -C2 (if C == C2 + SMAX)

This could be extended to handle the more general (non-constant)
pattern too:
https://alive2.llvm.org/ce/z/rdfNFP

  define i1 @src(i8 %a, i8 %c1) {
    %t = add i8 %a, %c1
    %c2 = add i8 %c1, 127 ; SMAX
    %ov = icmp ugt i8 %t, %c2
    ret i1 %ov
  }

  define i1 @tgt(i8 %a, i8 %c1) {
    %neg_c1 = sub i8 0, %c1
    %ov = icmp slt i8 %a, %neg_c1
    ret i1 %ov
  }

The pattern was noticed as a by-product of D104932.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modifiedllvm/test/Transforms/InstCombine/icmp-add.ll
Commit 59fa435ea66629b4c45d9e6b62fa6cc1cdf5d5aa by llvm-dev
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)

This demonstrates a possible fix for PR48760 - for compares with constants, canonicalize the SGT/UGT condition code to use SGE/UGE which should reduce the number of EFLAGs bits we need to read.

As discussed on PR48760, some EFLAG bits are treated independently which can require additional uops to merge together for certain CMOVcc/SETcc/etc. modes.

I've limited this to cases where the constant increment doesn't result in a larger encoding or additional i64 constant materializations.

Differential Revision: https://reviews.llvm.org/D101074
The file was modifiedllvm/test/CodeGen/X86/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/X86/select_const.ll
The file was modifiedllvm/test/CodeGen/X86/or-branch.ll
The file was modifiedllvm/test/CodeGen/X86/ssub_sat.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/atomic-eflags-reuse.ll
The file was modifiedllvm/test/CodeGen/X86/smul_fix_sat_constants.ll
The file was modifiedllvm/test/CodeGen/X86/umul_fix_sat.ll
The file was modifiedllvm/test/CodeGen/X86/lack-of-signed-truncation-check.ll
The file was modifiedllvm/test/CodeGen/X86/pr5145.ll
The file was modifiedllvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
The file was modifiedllvm/test/CodeGen/X86/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/X86/smul_fix_sat.ll
The file was modifiedllvm/test/CodeGen/X86/srem-seteq.ll
The file was modifiedllvm/test/CodeGen/X86/pr45995-2.ll
The file was modifiedllvm/test/CodeGen/X86/setcc-logic.ll
The file was modifiedllvm/test/CodeGen/X86/cmov.ll
The file was modifiedllvm/test/CodeGen/X86/mul-constant-result.ll
The file was modifiedllvm/test/CodeGen/X86/setcc.ll
The file was modifiedllvm/test/CodeGen/X86/vector-mulfix-legalize.ll
The file was modifiedllvm/test/CodeGen/X86/zext-sext.ll
The file was modifiedllvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/X86/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/X86/urem-seteq.ll
The file was modifiedllvm/test/CodeGen/X86/select.ll
The file was modifiedllvm/test/CodeGen/X86/sdiv_fix_sat.ll
Commit 9a9e6189d7973c16535233b5efcb38d13a651c56 by zhijian
[AIX][XCOFF][BUG-Fixed] need to switch back to text section after emit a dumy eh structure

Summary:

in the patch https://reviews.llvm.org/D103651 [AIX][XCOFF] generate eh_info when vector registers are saved according to the traceback table.

when generate eh_info, it switch to other section, when it done, it need to switch back to text section again.

Reviewers: Jason Liu
Differential Revision: https://reviews.llvm.org/105195
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll
Commit 4339d3bd84a9bc1b5ecc58ddfc935d53e9de4fd4 by michael.hliao
Fix shared build.
The file was modifiedllvm/unittests/Passes/CMakeLists.txt
Commit cd76f43b4995cf01bae9f97a54ca0e79c2355032 by david.green
[ARM] Set the immediate cost of GEP operands to 0

This prevents constant gep operands from being hoisted by the Constant
Hoisting pass, leaving them to CodegenPrepare which can usually do a
better job at splitting large offsets. This can, in general, improve
performance and decrease codesize, especially for v6m where many
constants have a high cost.

Differential Revision: https://reviews.llvm.org/D104877
The file was modifiedllvm/test/CodeGen/ARM/gep-imm.ll
The file was modifiedllvm/test/Transforms/ConstantHoisting/ARM/gep-struct-index.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
Commit 9b0ddc2662addaa563b632c577996e515e1a7802 by leonardchan
[clang][Fuchsia] Remove relative-vtables multilibs

As of D102374, relative vtables is enabled on Fuchsia by default, so we don't need any of the RV multilibs.

Differential revision: https://reviews.llvm.org/D105145
The file was modifiedclang/cmake/caches/Fuchsia-stage2.cmake
Commit 03051f7ac8a3e2eda44b8280290c90863a064f0e by i
[ELF] Preserve section order within an INSERT AFTER command

For
```
SECTIONS {
  text.0 : {}
  text.1 : {}
  text.2 : {}
} INSERT AFTER .data;
```

the current order is `.data text.2 text.1 text.0`. It makes more sense to
preserve the specified order and thus improve compatibility with GNU ld.

For
```
SECTIONS { text.0 : {} } INSERT AFTER .data;
SECTIONS { text.3 : {} } INSERT AFTER .data;
```

GNU ld somehow collects sections with `INSERT AFTER .data` together (IMO
inconsistent) but I think it makes more sense to execute the commands in order
and get `.data text.3 text.0` instead.

Reviewed By: peter.smith

Differential Revision: https://reviews.llvm.org/D105158
The file was modifiedlld/ELF/ScriptParser.cpp
The file was addedlld/test/ELF/linkerscript/insert-multi.test
The file was modifiedlld/ELF/LinkerScript.h
The file was modifiedlld/ELF/LinkerScript.cpp
Commit 2c4f5690ab5e435691aafe554725dbbd521b3754 by ataei
Add linalg.batch_matvec named op

    Similarly to batch_mat vec outer most dim is a batching dim
    and this op does |b| matrix-vector-products :
    C[b, i] = sum_k(A[b, i, k] * B[b, k])

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D104739
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
The file was modifiedmlir/test/Dialect/Linalg/generalize-named-ops.mlir
The file was modifiedmlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py
Commit 822b92aae439c4ba2946980c8a27bd2c8a62d90c by lxfind
[Coroutines] Add the newly generated SCCs back to the CGSCC work queue after CoroSplit actually happened

Relevant discussion can be found at: https://lists.llvm.org/pipermail/llvm-dev/2021-January/148197.html
In the existing design, An SCC that contains a coroutine will go through the folloing passes:
Inliner -> CoroSplitPass (fake) -> FunctionSimplificationPipeline -> Inliner -> CoroSplitPass (real) -> FunctionSimplificationPipeline

The first CoroSplitPass doesn't do anything other than putting the SCC back to the queue so that the entire pipeline can repeat.
As you can see, we run Inliner twice on the SCC consecutively without doing any real split, which is unnecessary and likely unintended.
What we really wanted is this:
Inliner -> FunctionSimplificationPipeline -> CoroSplitPass -> FunctionSimplificationPipeline
(note that we don't really need to run Inliner again on the ramp function after split).

Hence the way we do it here is to move CoroSplitPass to the end of the CGSCC pipeline, make it once for real, insert the newly generated SCCs (the clones) back to the pipeline so that they can be optimized, and also add a function simplification pipeline after CoroSplit to optimize the post-split ramp function.

This approach also conforms to how the new pass manager works instead of relying on an adhoc post split cleanup, making it ready for full switch to new pass manager eventually.

By looking at some of the changes to the tests, we can already observe that this changes allows for more optimizations applied to coroutines.

Reviewed By: aeubanks, ChuanqiXu

Differential Revision: https://reviews.llvm.org/D95807
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-musttail.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-musttail1.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloca-01.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-once-value.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-async.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-frame.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-once-value2.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-00.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-padding.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-byval-param.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-alloc.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-dbg.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-spill-defs-before-corobegin.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-hidden.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-zero-alloca.ll
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/test/Transforms/Coroutines/restart-trigger.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloc-with-param-O2.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-04.ll
The file was modifiedllvm/test/Transforms/Coroutines/ArgAddr.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-01.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-eh-aware-edge-split-00.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-swifterror.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-eh-aware-edge-split-01.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-materialize.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-musttail2.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-02.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-alloca.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-sink-lifetime-04.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-spill-after-phi.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-02.ll
The file was modifiedllvm/test/Transforms/Coroutines/smoketest.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-frame-arrayalloca.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-unreachable.ll
The file was modifiedclang/test/CodeGenCoroutines/coro-newpm-pipeline.cpp
The file was modifiedllvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-03.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloca-05.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-frame-unreachable.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-value.ll
The file was modifiedllvm/test/Transforms/Coroutines/no-suspend.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-sink-lifetime-01.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloca-02.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloca-03.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-musttail3.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroSplit.cpp
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-00.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloc-with-param-O0.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloca-08.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-recursive.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-eh-01.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-resume-values.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-sink-lifetime-02.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-catchswitch.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-param-copy.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloca-04.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-catchswitch-cleanuppad.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-eh-00.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-frame.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-spill-corobegin.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-spill-promise.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloca-07.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-debug.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-eh-aware-edge-split-02.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-split-sink-lifetime-03.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-frame-reuse-alloca-05.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-alloca-06.ll
The file was modifiedllvm/test/Transforms/Coroutines/coro-retcon-resume-values2.ll
Commit 381ded345bdd59edcea9a87f399f67b18be7622a by Stanislav.Mekhanoshin
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants

This is to allow 64 bit constant rematerialization. If a constant
is split into two separate moves initializing sub0 and sub1 like
now RA cannot rematerizalize a 64 bit register.

This gives 10-20% uplift in a set of huge apps heavily using double
precession math.

Fixes: SWDEV-292645

Differential Revision: https://reviews.llvm.org/D104874
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/srem64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
The file was modifiedllvm/lib/Target/AMDGPU/CMakeLists.txt
The file was modifiedllvm/test/CodeGen/AMDGPU/urem64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/shift-i128.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/inline-asm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/sopk-compares.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/test/CodeGen/AMDGPU/inline-constraints.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/udiv64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
The file was addedllvm/test/CodeGen/AMDGPU/combine-sreg64-inits.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdiv64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/promote-alloca-vector-to-vector.ll
The file was addedllvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/packed-fp32.ll
The file was addedllvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ds_write2.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
Commit f0693bc0ae47e4f7237e4e8d17ee96481c370e0a by listmail
autogen two tests for ease of update
The file was modifiedllvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll
The file was modifiedllvm/test/Transforms/LoopReroll/nonconst_lb.ll
Commit 51c3e3f80c7e6c1e8bf704e75bab999f2a8661e9 by thakis
[gn build] (manually) port f617ab104451 (DoublerPlugin)
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Passes/BUILD.gn
Commit ec74192f52472c1ce928f8ca3cfeed8038a68066 by llvmgnsyncbot
[gn build] Port 381ded345bdd
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Commit f4ea6531e677b1a3c107d7009a7e2f195c8fa915 by flo
[BasicAA] Add test for incorrectly inferring noalias due to scale sign.

This patch adds a test where we currently incorrectly determine noalias,
because the sign of Scale is adjusted after 91fa3565da16.
The file was modifiedllvm/test/Analysis/BasicAA/gep-modulo.ll
Commit e6d22d0174e09fa01342d9ed1dca47bc1eb58303 by flo
[BasicAA] Use separate scale variable for GCD.

Use separate variable for adjusted scale used for GCD computations. This
fixes an issue where we incorrectly determined that all indices are
non-negative and returned noalias because of that.

Follow up to 91fa3565da16.
The file was modifiedllvm/lib/Analysis/BasicAliasAnalysis.cpp
The file was modifiedllvm/test/Analysis/BasicAA/gep-modulo.ll
Commit 2eb7bbbe65b6374e6137772f1c2c46e6daa5c33d by rob.suderman
[mlir][tosa] Use 3D tensors in tosa.matmul

Signed-off-by: Suraj Sudhir <suraj.sudhir@arm.com>

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D105213
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
The file was modifiedmlir/test/Dialect/Tosa/ops.mlir
Commit a64287247633da36b58d65e4c5e248f2b4c6fe61 by Jon Roelofs
[GISel] Support llvm.memcpy.inline

Differential revision: https://reviews.llvm.org/D105072
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-memcpy-inline.mir
The file was addedllvm/test/MachineVerifier/test_g_memcpy_inline.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
The file was addedllvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir
The file was modifiedllvm/include/llvm/Target/GenericOpcodes.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/include/llvm/Support/TargetOpcodes.def
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was addedllvm/test/MachineVerifier/test_g_memmove.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
The file was modifiedllvm/test/MachineVerifier/test_g_bzero.mir
The file was modifiedllvm/docs/GlobalISel/GenericOpcode.rst
The file was modifiedllvm/test/MachineVerifier/test_g_memcpy.mir
The file was modifiedllvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp
Commit 24a36ce58b773332dbb28df87270251686c9430d by tianshilei1992
[OpenMP][Offloading] Replace all calls to `isSPMDMode` with `__kmpc_is_spmd_exec_mode`

In our ongoing work, we are using `AbstractAttributor` to deduct execution model
of device functions, and potententially remove unnecessary function calls to
`__kmpc_is_spmd_exec_mode`. In current device runtime, we have mixed use of
`isSPMDMode` and `__kmpc_is_spmd_exec_mode`, but in fact in `__kmpc_is_spmd_exec_mode`
it simply calls `isSPMDMode`. Since all functions starting with `__kmpc` is C
function, which doesn't have things like name mangling. It is more optimization
friendly. In this patch, we simply replaced all calls to `isSPMDMode` with
`__kmpc_is_spmd_exec_mode` to pave the way for the optimization.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D105211
The file was modifiedopenmp/libomptarget/deviceRTLs/common/src/data_sharing.cu
The file was modifiedopenmp/libomptarget/deviceRTLs/common/src/support.cu
The file was modifiedopenmp/libomptarget/deviceRTLs/common/support.h
The file was modifiedopenmp/libomptarget/deviceRTLs/common/src/libcall.cu
The file was modifiedopenmp/libomptarget/deviceRTLs/common/src/loop.cu
The file was modifiedopenmp/libomptarget/deviceRTLs/common/src/omptarget.cu
Commit 69e0f790e03221b65fbf9f9fb340a7bb916bb12c by v.churavy
[Orc] Fix name of LLVMOrcIRTransformLayerSetTransform

In https://reviews.llvm.org/D103855 we added access to IRTransformLayer, but I
just noticed that the function name is following the wrong pattern.

Differential Revision: https://reviews.llvm.org/D104840
The file was modifiedllvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
The file was modifiedllvm/examples/OrcV2Examples/OrcV2CBindingsIRTransforms/OrcV2CBindingsIRTransforms.c
The file was modifiedllvm/include/llvm-c/Orc.h
Commit 9762f12c6c60d7306040dd1717b708763cc803a4 by v.churavy
[Orc] Run the examples as part of the tests

Enable the Orc C-Bindings for testing.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D104637
The file was modifiedllvm/test/lit.cfg.py
The file was addedllvm/test/Examples/OrcV2Examples/orcv2-cbindings-basic-usage.test
The file was addedllvm/test/Examples/OrcV2Examples/orcv2-cbindings-reflect-process-symbols.test
The file was modifiedllvm/test/CMakeLists.txt
The file was addedllvm/test/Examples/OrcV2Examples/orcv2-cbindings-add-object-file.test
The file was addedllvm/test/Examples/OrcV2Examples/orcv2-cbindings-removable-code.test
Commit bf6770f9bd606643c8ea8a7ab03da5da5960e98e by martin
[CMake] Don't use -Bsymbolic-functions for MinGW targets

This is an ELF specific option which isn't supported for Windows/MinGW
targets, even if the MinGW linker otherwise uses an ld.bfd like linker
interface.

Differential Revision: https://reviews.llvm.org/D105148
The file was modifiedllvm/tools/llvm-shlib/CMakeLists.txt
The file was modifiedclang/tools/clang-shlib/CMakeLists.txt
Commit 578a4cfe19121df5e5e02bf03482233e3bc56a0d by sivachandra
[libc][NFC] Clear all exceptions in exception_flags_test before raising another.

This is because, raising some exceptions can raise other ones. For
example, raising FE_OVERFLOW can raise FE_INEXACT. So, we need to clear all
exceptions if we want a clean slate.
The file was modifiedlibc/test/src/fenv/exception_flags_test.cpp
Commit fae05692a36f9ebbd201d93c2a6b0f927564d7e6 by Matthew.Arsenault
CodeGen: Print/parse LLTs in MachineMemOperands

This will currently accept the old number of bytes syntax, and convert
it to a scalar. This should be removed in the near future (I think I
converted all of the tests already, but likely missed a few).

Not sure what the exact syntax and policy should be. We can continue
printing the number of bytes for non-generic instructions to avoid
test churn and only allow non-scalar types for generic instructions.

This will currently print the LLT in parentheses, but accept parsing
the existing integers and implicitly converting to scalar. The
parentheses are a bit ugly, but the parser logic seems unable to deal
without either parentheses or some keyword to indicate the start of a
type.
The file was modifiedllvm/test/CodeGen/Mips/unaligned-memops.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memcpy-scoped-aa.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/test/CodeGen/MIR/X86/diexpr-win32.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir
The file was modifiedllvm/test/CodeGen/SystemZ/fp-conv-17.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-bzero.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
The file was modifiedllvm/test/CodeGen/AArch64/loop-sink.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/contract-store.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/legalize-fp-load-invariant.ll
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-static.mir
The file was modifiedllvm/test/CodeGen/PowerPC/licm-tocReg.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/irtranslator/var_arg.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/begin-vpt-without-inst.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-crash.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/load_4_unaligned.mir
The file was modifiedllvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
The file was modifiedllvm/test/CodeGen/AArch64/elim-dead-mi.mir
The file was modifiedllvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
The file was modifiedllvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/opt-overlapping-and.mir
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/load-store-opt-dlc.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir
The file was modifiedllvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
The file was modifiedllvm/test/CodeGen/MIR/AArch64/swp.mir
The file was modifiedllvm/test/CodeGen/Mips/micromips-eva.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-cse.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmax.ll
The file was modifiedllvm/test/CodeGen/PowerPC/setcr_bc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/hard-clauses.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-pic.mir
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-iterative-2.mir
The file was modifiedllvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/nsa-reassign.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
The file was modifiedllvm/test/CodeGen/AArch64/settag-merge.mir
The file was modifiedllvm/test/CodeGen/PowerPC/livephysregs.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/labels-are-not-dead.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
The file was modifiedllvm/test/CodeGen/Thumb/tbb-reuse.mir
The file was modifiedllvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
The file was modifiedllvm/test/CodeGen/PowerPC/nofpexcept.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-cc-byval-split.ll
The file was modifiedllvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec_builtin.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
The file was modifiedllvm/test/CodeGen/SystemZ/load-and-test-RA-hints.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
The file was modifiedllvm/test/CodeGen/ARM/constant-island-movwt.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
The file was modifiedllvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/irtranslator/split_args.ll
The file was modifiedllvm/test/CodeGen/ARM/machine-sink-multidef.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
The file was modifiedllvm/test/CodeGen/Thumb2/store-prepostinc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir
The file was modifiedllvm/test/CodeGen/Hexagon/packetize-load-store-aliasing.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee-split.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
The file was modifiedllvm/test/CodeGen/AArch64/wineh-frame7.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/irtranslator/call.ll
The file was modifiedllvm/test/CodeGen/AArch64/spill-fold.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
The file was modifiedllvm/test/CodeGen/Thumb/machine-cse-deadreg.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
The file was modifiedllvm/test/CodeGen/Hexagon/bank-conflict.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was modifiedllvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
The file was modifiedllvm/test/CodeGen/Thumb2/tbb-removeadd.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-bzero.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-binops.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
The file was modifiedllvm/test/CodeGen/Hexagon/addrmode-immop.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
The file was modifiedllvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/store-wro-addressing-modes.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir
The file was modifiedllvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
The file was modifiedllvm/test/CodeGen/Lanai/peephole-compare.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
The file was modifiedllvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
The file was modifiedllvm/test/CodeGen/ARM/nonreserved-callframe-with-basereg.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh2.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-image-load.mir
The file was modifiedllvm/test/CodeGen/SystemZ/multiselect-02.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh3.mir
The file was modifiedllvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh6.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
The file was modifiedllvm/test/CodeGen/ARM/fp16-litpool-arm.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/floating_point_vec_arithmetic_operations.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir
The file was modifiedllvm/test/CodeGen/ARM/const-load-align-thumb.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh5.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs_vec.mir
The file was modifiedllvm/test/CodeGen/PowerPC/two-address-crash.mir
The file was modifiedllvm/test/CodeGen/SystemZ/int-cmp-56.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
The file was modifiedllvm/test/CodeGen/AArch64/spill-undef.mir
The file was modifiedllvm/test/CodeGen/AArch64/machine-outliner-bti.mir
The file was modifiedllvm/test/CodeGen/ARM/cmpxchg.mir
The file was modifiedllvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir
The file was modifiedllvm/test/CodeGen/PowerPC/livevars-crash1.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-ops.mir
The file was modifiedllvm/test/CodeGen/PowerPC/remove-redundant-li-skip-imp-kill.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
The file was modifiedllvm/test/CodeGen/PowerPC/livevars-crash2.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir
The file was modifiedllvm/test/CodeGen/PowerPC/phi-eliminate.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-large.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wls-search-killed.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/fold-global-offsets.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
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The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir
The file was modifiedllvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned.mir
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
The file was modifiedllvm/test/CodeGen/AArch64/seqpairspill.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix-csr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
The file was modifiedllvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
The file was modifiedllvm/test/CodeGen/AArch64/zext-reg-coalesce.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir
The file was modifiedllvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
The file was modifiedllvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned_r6.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
The file was modifiedllvm/test/CodeGen/AArch64/stack-guard-reassign.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-scavenge-sgpr-carry-out.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
The file was modifiedllvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
The file was modifiedllvm/test/CodeGen/PowerPC/stack-coloring-vararg.mir
The file was modifiedllvm/test/CodeGen/SystemZ/debuginstr-01.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-cmp.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
The file was modifiedllvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
The file was modifiedllvm/test/CodeGen/SystemZ/cond-move-08.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh1.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
The file was modifiedllvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
The file was modifiedllvm/test/CodeGen/SystemZ/foldmemop-msc.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr-debugloc.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/endpgm-dce.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
The file was modifiedllvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
The file was modifiedllvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir
The file was modifiedllvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir
The file was modifiedllvm/test/CodeGen/SystemZ/foldmemop-vec-cc.mir
The file was modifiedllvm/test/CodeGen/Mips/copy-fp64.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
The file was modifiedllvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
The file was modifiedllvm/test/CodeGen/ARM/register-scavenger-exceptions.mir
The file was modifiedllvm/test/CodeGen/Thumb2/block-placement.mir
The file was modifiedllvm/test/CodeGen/SystemZ/combine_loads_from_build_pair.ll
The file was modifiedllvm/test/CodeGen/AArch64/branch-folder-merge-mmos.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations_builtin.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/load_store_vec.mir
The file was modifiedllvm/test/CodeGen/AArch64/branch-relax-block-size.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
The file was modifiedllvm/test/CodeGen/Thumb2/scavenge-lr.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix32-crsave.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-trunc.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-retaining.mir
The file was modifiedllvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir
The file was modifiedllvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-stacksplot.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
The file was modifiedllvm/test/CodeGen/MIR/AArch64/mirnamer.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
The file was modifiedllvm/test/CodeGen/MIR/AArch64/base-memoperands.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir
The file was modifiedllvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
The file was modifiedllvm/test/CodeGen/Thumb2/constant-islands-cbzundef.mir
The file was modifiedllvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh-frame6.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
The file was modifiedllvm/test/CodeGen/Hexagon/packetize-dccleana.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
The file was modifiedllvm/test/CodeGen/Hexagon/early-if-predicator.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir
The file was modifiedllvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-max-address-space.ll
The file was modifiedllvm/test/CodeGen/ARM/vldm-liveness.mir
The file was modifiedllvm/test/CodeGen/AArch64/branch-target-enforcement.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
The file was modifiedllvm/test/CodeGen/Hexagon/cext-opt-stack-no-rr.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
The file was modifiedllvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir
The file was modifiedllvm/test/CodeGen/AArch64/falkor-hwpf-fix.mir
The file was modifiedllvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
The file was modifiedllvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix-csr-vector.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
The file was modifiedllvm/test/CodeGen/SystemZ/isel-debug.ll
The file was modifiedllvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
The file was modifiedllvm/test/CodeGen/PowerPC/block-placement.mir
The file was modifiedllvm/test/CodeGen/Thumb2/constant-islands-cbz.mir
The file was modifiedllvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
The file was modifiedllvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll
The file was modifiedllvm/test/CodeGen/ARM/constant-island-SOImm-limit16.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
The file was modifiedllvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
The file was modifiedllvm/test/CodeGen/PowerPC/unal-vec-negarith.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-build-spill.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-reloc-symb.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
Commit a62579fc008e22b6c9e1544788644f5fceef15ce by platonov.aleksandr
[clangd][nfc] Show more information in logs when compiler instance prepare fails

Without this patch clangd silently process compiler instance prepare failure and only LSP errors "Invalid AST" could be found in logs.
E.g. the reason of the problem https://github.com/clangd/clangd/issues/734 is impossible to understand without verbose logs or with disabled background index.
This patch adds more information into logs to help understand the reason of such failures.

Logs without this patch:
```
E[...] Could not build a preamble for file test.cpp version 1
```

Logs with this patch:
```
E[...] Could not build a preamble for file test.cpp version 1: CreateTargetInfo() return null
..
E[...] Failed to prepare a compiler instance: unknown target ABI 'lp64'
```

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D104056
The file was modifiedclang-tools-extra/clangd/Preamble.cpp
The file was modifiedclang-tools-extra/clangd/ParsedAST.cpp
Commit 7aef99351ac3ff56a34de91ba5ad3d3d9815fa20 by paulsson
[MCStreamer]  Move emission of attributes section into MCELFStreamer

Enable the emission of a GNU attributes section by reusing the code for
emitting the ARM build attributes section.

The GNU attributes follow the exact same section format as the ARM
BuildAttributes section, so this can be factored out and reused for GNU
attributes generally.

The immediate motivation for this is to emit a GNU attributes section for the
vector ABI on SystemZ (https://reviews.llvm.org/D105067).

Review: Logan Chien, Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D102894
The file was modifiedllvm/lib/MC/MCAsmStreamer.cpp
The file was modifiedllvm/include/llvm/MC/MCParser/MCAsmParser.h
The file was modifiedllvm/lib/MC/MCParser/MCAsmParser.cpp
The file was modifiedllvm/lib/MC/MCELFStreamer.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
The file was modifiedllvm/include/llvm/MC/MCStreamer.h
The file was modifiedllvm/include/llvm/MC/MCELFStreamer.h
Commit d6270125fc2dd771973f20c33bdb7fd9f91b51d6 by Matthew.Arsenault
AMDGPU/GlobalISel: Remove some problematic testcases

These testcases are a bit nonsensical and won't be handled correctly
for a long time. Remove them to unblock load/store legalization work.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
Commit 748e0b07dcebfd9beaadc28be940354b9207b195 by Matthew.Arsenault
GlobalISel: Preserve memory type when reducing load/store width
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-fpext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
Commit a601b308d91eabf008cf13a041dc0238550e3c0c by Matthew.Arsenault
GlobalISel: Lower non-byte loads and stores

Previously we didn't preserve the memory type and had to blindly
interpret a number of bytes. Now that non-byte memory accesses are
representable, we can handle these correctly.

Ported from DAG version (minus some weird special case i1 legality
checking which I don't fully understand, and we don't have a way to
query for)

For now, this is NFC and the test changes are placeholders. Since the
legality queries are still relying on byte-flattened memory sizes, the
legalizer can't actually see these non-byte accesses. This keeps this
change self contained without merging it with the larger patch to
switch to LLT memory queries.
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
Commit d86b0073cf283849ef9beaa94efe13fef1a0a615 by jonathanchesterfield
[libomptarget][amdgpu][nfc] Fix build warnings, drop some headers

Removes stdarg header, drops uses of iostream, fix some format string errors.
Also changes a C style struct to C++ style to avoid a warning from clang/

Reviewed By: pdhaliwal

Differential Revision: https://reviews.llvm.org/D104923
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/data.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/rt.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/internal.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/utils.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/system.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/atmi.cpp
Commit ef227b32b63c53ca81ebd410c7fbd5af8fc22ec5 by richard
Add dumping support for RequiresExpr.

In passing, fix an ast-print bug that inserted a spurious extra `;`
after a concept definition.
The file was modifiedclang/include/clang/AST/TextNodeDumper.h
The file was modifiedclang/lib/AST/JSONNodeDumper.cpp
The file was modifiedclang/include/clang/AST/ASTNodeTraverser.h
The file was modifiedclang/lib/AST/DeclPrinter.cpp
The file was modifiedclang/lib/AST/TextNodeDumper.cpp
The file was modifiedclang/test/Coverage/cxx-language-features.inc
The file was modifiedclang/include/clang/AST/JSONNodeDumper.h
The file was modifiedclang/test/Coverage/ast-printing.cpp
Commit cab5f89cfd9efa9166e1362972e460323b8254ef by tra
[Clang] allow overriding -fbasic-block-sections

We should not error out on non-x86 targets if `-fbasic-block-sections=none` is in effect.

Also, filter it out for GPU-side compilations, as we do with other options not
supported on the GPU.

Differential Revision: https://reviews.llvm.org/D105226
The file was modifiedclang/test/Driver/fbasic-block-sections.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit e5fbe9f3150b5f810673590ca50a0ee793e120d1 by arthur.j.odwyer
[libc++] graph_header_deps.py: Detect files that include themselves.

This wasn't happening before, which led to one slipping in.
The file was modifiedlibcxx/include/__ranges/subrange.h
The file was modifiedlibcxx/utils/graph_header_deps.py
Commit 4b0926b044b972ac34c84082face86061900471d by jonathanchesterfield
[libomptarget][nfc] Replace out arguments with struct return

A step towards making this function adequately self contained that it
can be tested easily. No functional change intended here, left variable
names unchanged.

Reviewed By: ronlieb

Differential Revision: https://reviews.llvm.org/D105229
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
Commit 28f2f66200c5719a637d857387922c91d8b12c34 by Matthew.Arsenault
GlobalISel: Use LLT in memory legality queries

This enables proper lowering of non-byte sized loads. We still aren't
faithfully preserving memory types everywhere, so the legality checks
still only consider the size.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
The file was modifiedllvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir
The file was modifiedllvm/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp
The file was modifiedllvm/lib/Target/Mips/MipsLegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-trunc.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
The file was modifiedllvm/lib/Target/ARM/ARMLegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
The file was modifiedllvm/lib/Target/ARM/ARMInstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
Commit 1575583f2ad9c8f519ea96e44b900a62493cf7bf by jeremy.morse
[LiveDebugValues][InstrRef][2/2] Emit entry value variable locations

This patch adds support to the instruction-referencing LiveDebugValues
implementation for emitting entry values. The instruction referencing
implementations tracking by value rather than location means that we can
get around two of the issues with VarLocs. DBG_VALUE instructions that
re-assign the same value to a variable are no longer a problem, because we
can "see through" to the value being assigned. We also don't need to do
anything special during the dataflow stages: the "variable value problem"
doesn't need to know whether a value is available most of the time, and the
times it deoes need to know are always when entry values need to be
terminated.

The patch modifies the "TransferTracker" class, adding methods to identify
when a variable ias an entry value candidate, and when a machine value is
an entry value. recoverAsEntryValue tests these two things and emits an
entry-value expression if they're true. It's used when we clobber or
otherwise lose a value and can't find a replacement location for the value
it contained.

Differential Revision: https://reviews.llvm.org/D88406
The file was modifiedllvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
The file was modifiedllvm/test/DebugInfo/Mips/dw_op_entry_value_64bit.ll
The file was modifiedllvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
The file was modifiedllvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
The file was modifiedllvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
The file was modifiedllvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll
The file was modifiedllvm/test/DebugInfo/Mips/dw_op_entry_value_32bit.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/debug-entry-value-operation.mir
The file was modifiedllvm/test/DebugInfo/MIR/X86/live-debug-values-entry-transfer.mir
The file was modifiedllvm/test/DebugInfo/X86/no-entry-values-with-O0.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
The file was modifiedllvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
Commit e7e71e9454ed76c1b3d8140170b5333c28bef1be by sivachandra
[libc][NFC] Remove few deprecated FPUtil header files and test patterns.

Few tests have been converted to the new test patterns to facilitate
this.
The file was modifiedlibc/test/src/math/frexp_test.cpp
The file was modifiedlibc/test/src/math/logb_test.cpp
The file was modifiedlibc/test/src/math/sdcomp26094.h
The file was modifiedlibc/test/src/math/frexpl_test.cpp
The file was removedlibc/utils/FPUtil/ClassificationFunctions.h
The file was modifiedlibc/test/src/math/logbl_test.cpp
The file was addedlibc/test/src/math/ModfTest.h
The file was modifiedlibc/test/src/math/modff_test.cpp
The file was modifiedlibc/test/src/math/sincosf_test.cpp
The file was addedlibc/test/src/math/FrexpTest.h
The file was modifiedlibc/test/src/math/modf_test.cpp
The file was modifiedlibc/test/src/math/modfl_test.cpp
The file was modifiedlibc/utils/FPUtil/CMakeLists.txt
The file was removedlibc/utils/FPUtil/BitPatterns.h
The file was modifiedlibc/test/src/math/CMakeLists.txt
The file was modifiedlibc/test/src/math/exp2f_test.cpp
The file was modifiedlibc/test/src/math/logbf_test.cpp
The file was addedlibc/test/src/math/LogbTest.h
The file was modifiedlibc/test/src/math/expf_test.cpp
The file was modifiedlibc/test/src/math/frexpf_test.cpp
The file was modifiedlibc/test/src/math/cosf_test.cpp
The file was modifiedlibc/test/src/math/expm1f_test.cpp
The file was modifiedlibc/test/src/math/sinf_test.cpp
The file was modifiedlibc/test/src/math/sin_test.cpp
The file was removedlibc/utils/FPUtil/FloatOperations.h
Commit 0d6d35e63bb01c7021b116c0f14227e353668627 by jezng
[lld-macho] -section_rename should work on synthetic sections too

Previously, we only applied the renames to
ConcatOutputSections.

Reviewed By: #lld-macho, thakis

Differential Revision: https://reviews.llvm.org/D105079
The file was modifiedlld/MachO/SyntheticSections.cpp
The file was modifiedlld/MachO/Writer.cpp
The file was modifiedlld/test/MachO/rename.s
The file was modifiedlld/MachO/SyntheticSections.h
The file was modifiedlld/MachO/Writer.h
Commit b41b4148e7b9e0cb8482674875449ae3f223cdfe by jezng
[lld-macho] Only enable `__DATA_CONST` for newer platforms

Matches ld64.

Reviewed By: #lld-macho, alexander-shaposhnikov

Differential Revision: https://reviews.llvm.org/D105080
The file was modifiedlld/test/MachO/builtin-rename.s
The file was modifiedlld/MachO/Driver.cpp
Commit b2fe025707aae780d88db2446fc1ce618e40bdb3 by spatel
[InstCombine][test] add tests for icmp ult with constant and offset; NFC

This is the 'ult' sibling pattern for:
c7b658aeb526c3e6
The file was modifiedllvm/test/Transforms/InstCombine/icmp-add.ll
Commit 0c400e8953069888315f85d62780839dccbaa33c by spatel
[InstCombine] fold icmp ult of offset value with constant

This is one sibling of the fold added with c7b658aeb526 .

(X + C2) <u C --> X >s ~C2 (if C == C2 + SMIN)
I'm still not sure how to describe it best, but we're
translating 2 constants from an unsigned range comparison
to signed because that eliminates the offset (add) op.

This could be extended to handle the more general (non-constant)
pattern too:
https://alive2.llvm.org/ce/z/K-fMBf

  define i1 @src(i8 %a, i8 %c2) {
    %t = add i8 %a, %c2
    %c = add i8 %c2, 128 ; SMIN
    %ov = icmp ult i8 %t, %c
    ret i1 %ov
  }

  define i1 @tgt(i8 %a, i8 %c2) {
    %not_c2 = xor i8 %c2, -1
    %ov = icmp sgt i8 %a, %not_c2
    ret i1 %ov
  }
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modifiedllvm/test/Transforms/InstCombine/icmp-add.ll
Commit 627733b5f045e870577e5abf70944d3ffac7a6fb by thomasraoux
[mlir][vector] Extend vector distribution to all elementwise and contract

Uses elementwise interface to generalize canonicalization pattern and add a new
pattern for vector.contract case.

Differential Revision: https://reviews.llvm.org/D104343
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.h
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
The file was modifiedmlir/test/Dialect/Vector/vector-distribution.mlir
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorTransforms.h
Commit 9cc1ddd393c9d8856e3fc7dce675a4d95de55adc by gcmn
[Bazel] Update README with examples

Reviewed By: chandlerc

Differential Revision: https://reviews.llvm.org/D105245
The file was modifiedutils/bazel/.gitignore
The file was addedutils/bazel/examples/submodule/WORKSPACE
The file was modifiedutils/bazel/README.md
The file was addedutils/bazel/examples/http_archive/WORKSPACE
Commit 4aa1c141bd674564aaee83516b7e338aa3aae9e3 by gcmn
[Bazel] Rework LLVM target selection

This patch introduces a custom rule for expanding the LLVM target
enumeration .def files. This provides a slightly cleaner API for these
rules, but is mostly to permit selects to be used when determining which
LLVM targets to build. Right now the target list is generated at Bazel
configure time, but this will allows us to add functionality to also
control which targets are built based on config settings.

Tested: Ran `bazel test --config=rbe ... @llvm-project//...`

Reviewed By: chandlerc

Differential Revision: https://reviews.llvm.org/D104969
The file was modifiedutils/bazel/llvm-project-overlay/llvm/BUILD.bazel
The file was addedutils/bazel/llvm-project-overlay/llvm/enum_targets_gen.bzl
Commit 5b8ddd2ccceb8de04bd020f286bc3ca38638ecb1 by richard
Fix test following Clang change ef227b3.
The file was modifiedclang-tools-extra/clangd/unittests/FindTargetTests.cpp
Commit 557bed31e41b62afc2e5682ccacbe008eb081414 by minyihh
Reapply "[M68k][GloballSel] Formal arguments lowering in IRTranslator"

Implementation of formal arguments lowering in the IRTranslator for the
M68k backend

Differential Revision: https://reviews.llvm.org/D104542
The file was modifiedllvm/lib/Target/M68k/M68kISelLowering.cpp
The file was modifiedllvm/lib/Target/M68k/M68kISelLowering.h
The file was modifiedllvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp
The file was modifiedllvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
The file was modifiedllvm/lib/Target/M68k/GlSel/M68kCallLowering.h
Commit 98c36f0079d46c83bf03a7bce1b9d7e22abe0cba by Dhruva.Chakrabarti
Revert "[libomptarget] [amdgpu] Fix default setting of max flat workgroup size"

This reverts commit 2240b41ee4f30fe938975677a0a5a2c5c26d271b.
A value of 0 for KernDescVal WG_Size implies it is unknown, so it should be
set to the default. The above change was made without this assumption.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D105250
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
Commit e95106f50190d7a25dfad57adf0317ca6cfa9a4f by richard
Add a target triple to fix failures on MS build bots.

-ast-dump=json tries to mangle every declaration, and under the MS ABI
there are still a few things we can't mangle, which caused this test to
assert.
The file was modifiedclang/test/Coverage/ast-printing.cpp
Commit 17858da0229520dacd52a4675cdc7d3e84e45111 by i
[AArch64] Remove unneeded ExternalSymbolSDNode code for machine constraint "S". NFC

ExternalSymbolSDNode is implicitly generated libcalls but with an address taking
operation we cannot reference an ExternalSymbolSDNode.
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit c0a6318d96344b475eec1229b664dd04b569a375 by springerm
[mlir][tensor] Add tensor.dim operation

* Split memref.dim into two operations: memref.dim and tensor.dim. Both ops have the same builder interface and op argument names, so that they can be used with templates in patterns that apply to both tensors and memrefs (e.g., some patterns in Linalg).
* Add constant materializer to TensorDialect (needed for folding in affine.apply etc.).
* Remove some MemRefDialect dependencies, make some explicit.

Differential Revision: https://reviews.llvm.org/D105165
The file was modifiedmlir/test/Dialect/Tensor/bufferize.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
The file was modifiedmlir/lib/Dialect/Tensor/Transforms/Bufferize.cpp
The file was modifiedmlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
The file was modifiedmlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/lib/Conversion/ShapeToStandard/ShapeToStandard.cpp
The file was modifiedmlir/include/mlir/Dialect/Tensor/IR/TensorBase.td
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir
The file was modifiedmlir/test/IR/core-ops.mlir
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Loops.cpp
The file was modifiedmlir/test/Dialect/Linalg/fusion-tensor.mlir
The file was modifiedmlir/test/IR/invalid-ops.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
The file was modifiedmlir/test/Dialect/Linalg/resolve-shaped-type-result-dims.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_2d.mlir
The file was modifiedmlir/test/Dialect/Linalg/subtensor-of-padtensor.mlir
The file was modifiedmlir/test/Dialect/Linalg/convert-elementwise-to-linalg.mlir
The file was modifiedmlir/include/mlir/Conversion/Passes.td
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/lib/Dialect/Affine/IR/AffineOps.cpp
The file was modifiedmlir/test/Dialect/Tensor/canonicalize.mlir
The file was modifiedmlir/test/Transforms/constant-fold.mlir
The file was modifiedmlir/test/Dialect/Linalg/fusion-elementwise-options.mlir
The file was modifiedmlir/test/Dialect/Standard/bufferize.mlir
The file was modifiedmlir/test/Dialect/Linalg/tile-tensors.mlir
The file was modifiedmlir/lib/Dialect/Tensor/Transforms/PassDetail.h
The file was modifiedmlir/test/Dialect/MemRef/canonicalize.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_3d.mlir
The file was modifiedmlir/test/lib/Dialect/Test/TestPatterns.cpp
The file was modifiedmlir/test/Conversion/ShapeToStandard/shape-to-standard.mlir
The file was modifiedmlir/test/lib/Dialect/Test/TestDialect.cpp
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalgPass.cpp
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
The file was modifiedmlir/test/Dialect/Linalg/fusion-sequence.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/ComprehensiveBufferize.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
The file was modifiedmlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
The file was modifiedmlir/test/Transforms/canonicalize.mlir
The file was modifiedmlir/test/Transforms/pipeline-data-transfer.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/Transforms/Passes.td
The file was modifiedmlir/test/Dialect/SparseTensor/conversion.mlir
The file was modifiedmlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
The file was modifiedmlir/lib/Dialect/MemRef/Transforms/ResolveShapedTypeResultDims.cpp
The file was modifiedmlir/lib/Dialect/StandardOps/Transforms/Bufferize.cpp
The file was modifiedmlir/lib/Conversion/ShapeToStandard/CMakeLists.txt
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
The file was modifiedmlir/test/Dialect/Linalg/hoist-padding.mlir
The file was modifiedmlir/test/Dialect/Linalg/vectorization.mlir
The file was modifiedmlir/include/mlir/Dialect/Tensor/Transforms/Passes.td
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
The file was modifiedmlir/test/Dialect/Linalg/fusion-tensor-pattern.mlir
The file was modifiedmlir/test/Dialect/Linalg/bufferize.mlir
The file was modifiedmlir/test/Dialect/Linalg/tile-and-fuse-tensors.mlir
The file was modifiedmlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
The file was modifiedmlir/lib/Conversion/TosaToLinalg/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/MemRef/IR/MemRef.h
The file was modifiedmlir/lib/Dialect/MemRef/IR/MemRefDialect.cpp
The file was modifiedmlir/lib/Dialect/Tensor/IR/TensorOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/reshape_fusion.mlir
The file was modifiedmlir/test/Interfaces/InferShapedTypeOpInterface/resolve-shaped-type-result-dims.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_1d.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
Commit ae5433945f915c2f0e39f8a026166cbdc8b0469c by JunMa
[AArch64][SVEIntrinsicOpts] Convect cntb/h/w/d to vscale intrinsic or constant.

As is mentioned above

Differential Revision: https://reviews.llvm.org/D104852
The file was addedllvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-counting-elems.ll
The file was modifiedclang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c
The file was modifiedclang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c
The file was modifiedclang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedclang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c
Commit 3afbf898044aa5839ed75273fa38a897abe9d3d4 by JunMa
[clang][AArch64][SVE] Handle PRValue under VLAT <-> VLST cast

This change fixes the crash that PRValue cannot be handled by
EmitLValue.

Differential Revision: https://reviews.llvm.org/D105097
The file was modifiedclang/lib/CodeGen/CGExprScalar.cpp
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-call.c
Commit d08f8960d06a07171bec722cc8fa813770801c4a by gcmn
[Bazel] add missing load to submodule example

I missed this in https://reviews.llvm.org/D105245

Reviewed By: chandlerc

Differential Revision: https://reviews.llvm.org/D105252
The file was modifiedutils/bazel/examples/submodule/WORKSPACE
Commit 68751651235562b27b83788a5da4d23e431443c1 by jezng
[llvm-objdump/mac] Print symbols at the same address deterministically

By using stable_sort.

Added a test case which previously failed when expensive checks were
enabled.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D105240
The file was modifiedllvm/tools/llvm-objdump/MachODump.cpp
The file was addedllvm/test/tools/llvm-objdump/MachO/disassemble-symbol-same-addr.test
Commit 51fbd187066fe4a0ba0deb1beb75106b088edd21 by yedeng.yd
[Coroutine] Recommit Add statistics for the number of elided coroutine

Now we lack a benchmark to measure the performance change for each
commit.
Since coro elide is the main optimization in coroutine module, I wonder
it may be an estimation to count the number of elided coroutine in
private code bases.
e.g., for a certain commit, if we found that the number of elided goes
down, we could find it before the commit check-in.

Reviewed By: lxfind

Differential Revision: https://reviews.llvm.org/D105095
The file was addedllvm/test/Transforms/Coroutines/coro-elide-count.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroElide.cpp
Commit 662c55442f17cd32a4d31de5f8c6f8961e2a3b71 by Lang Hames
[ORC] Rename TargetProcessControl to ExecutorProcessControl. NFC.

This is a first step towards consistently using the term 'executor' for the
process that executes JIT'd code. I've opted for 'executor' as the preferred
term over 'target' as target is already heavily overloaded ("the target
machine for the executor" is much clearer than "the target machine for the
target").
The file was modifiedllvm/include/llvm-c/LLJIT.h
The file was removedllvm/include/llvm/ExecutionEngine/Orc/TPCDynamicLibrarySearchGenerator.h
The file was removedllvm/lib/ExecutionEngine/Orc/TPCEHFrameRegistrar.cpp
The file was addedllvm/include/llvm/ExecutionEngine/Orc/EPCIndirectionUtils.h
The file was modifiedllvm/examples/Kaleidoscope/BuildingAJIT/Chapter1/KaleidoscopeJIT.h
The file was modifiedllvm/examples/OrcV2Examples/LLJITWithTargetProcessControl/LLJITWithTargetProcessControl.cpp
The file was removedllvm/include/llvm/ExecutionEngine/Orc/TPCDebugObjectRegistrar.h
The file was modifiedllvm/examples/Kaleidoscope/include/KaleidoscopeJIT.h
The file was removedllvm/include/llvm/ExecutionEngine/Orc/OrcRPCTargetProcessControl.h
The file was removedllvm/include/llvm/ExecutionEngine/Orc/TargetProcessControl.h
The file was modifiedllvm/examples/Kaleidoscope/BuildingAJIT/Chapter2/KaleidoscopeJIT.h
The file was addedllvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp
The file was modifiedllvm/tools/lli/lli.cpp
The file was removedllvm/lib/ExecutionEngine/Orc/TPCDebugObjectRegistrar.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/DebugObjectManagerPlugin.h
The file was removedllvm/include/llvm/ExecutionEngine/Orc/TPCEHFrameRegistrar.h
The file was removedllvm/lib/ExecutionEngine/Orc/TPCIndirectionUtils.cpp
The file was modifiedllvm/examples/Kaleidoscope/BuildingAJIT/Chapter4/KaleidoscopeJIT.h
The file was removedllvm/include/llvm/ExecutionEngine/Orc/TPCIndirectionUtils.h
The file was addedllvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
The file was addedllvm/lib/ExecutionEngine/Orc/EPCEHFrameRegistrar.cpp
The file was addedllvm/include/llvm/ExecutionEngine/Orc/OrcRPCExecutorProcessControl.h
The file was removedllvm/lib/ExecutionEngine/Orc/TPCDynamicLibrarySearchGenerator.cpp
The file was modifiedllvm/tools/llvm-jitlink/llvm-jitlink.h
The file was modifiedllvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h
The file was removedllvm/lib/ExecutionEngine/Orc/TargetProcessControl.cpp
The file was modifiedllvm/tools/llvm-jitlink/llvm-jitlink.cpp
The file was addedllvm/include/llvm/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.h
The file was addedllvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/CMakeLists.txt
The file was modifiedllvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.h
The file was addedllvm/include/llvm/ExecutionEngine/Orc/EPCDebugObjectRegistrar.h
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
The file was addedllvm/lib/ExecutionEngine/Orc/EPCDebugObjectRegistrar.cpp
The file was modifiedllvm/lib/ExecutionEngine/Orc/LLJIT.cpp
The file was modifiedllvm/include/llvm-c/Orc.h
The file was addedllvm/include/llvm/ExecutionEngine/Orc/EPCEHFrameRegistrar.h
The file was addedllvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
The file was modifiedllvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.cpp
Commit b1fd009aab4bfe4f16bd78b7ac779c3f665ae060 by Vitaly Buka
[scudo] GWP_ASAN runs on untagged pointers

It's already covered by multiple tests, but to trigger
this path we need MTE+GWP which disabled.

Reviewed By: hctim, pcc

Differential Revision: https://reviews.llvm.org/D105232
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
Commit 00f474e9b1c5e3b1504fb112f7f95a7c85a4145e by Vitaly Buka
[GWP_ASAN] Enable ARM tests

Reviewed By: hctim

Differential Revision: https://reviews.llvm.org/D105233
The file was modifiedcompiler-rt/cmake/config-ix.cmake
Commit f16029e3f7649259dfa4224bc922b6a42b868dbf by llvmgnsyncbot
[gn build] Port 662c55442f17
The file was modifiedllvm/utils/gn/secondary/llvm/lib/ExecutionEngine/Orc/BUILD.gn
Commit ae7c3959e0e9a9f6acb854f2eb9afd32fa930168 by Vitaly Buka
[Compiler-rt] Add delete for noncopyable

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D105077
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mutex.h
Commit 28b01c59c93d10ed3a775dd13ff827048b59cda8 by bcain
[hexagon] Add {hvx,}hexagon_{protos,circ_brev...}

Add definitions for Hexagon, Hexagon circular/bit-reverse and HVX
intrinsics.
The file was modifiedclang/lib/Headers/CMakeLists.txt
The file was addedclang/lib/Headers/hvx_hexagon_protos.h
The file was addedclang/test/Headers/hexagon-audio-headers.c
The file was addedclang/lib/Headers/hexagon_types.h
The file was addedclang/test/Headers/hexagon-hvx-headers.c
The file was addedclang/lib/Headers/hexagon_protos.h
The file was addedclang/test/Headers/hexagon-headers.c
The file was addedclang/lib/Headers/hexagon_circ_brev_intrinsics.h
Commit 9184090c967c08aa78a87665e0cde20177cfc9ae by llvmgnsyncbot
[gn build] Port 28b01c59c93d
The file was modifiedllvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Commit 96f15aa5bbb0c6b2a56fa5fcbbd58f5b69fe4076 by jacobhegna
Fail gracefully if no inlining model is available to download.

Differential Revision: https://reviews.llvm.org/D104829
The file was modifiedllvm/cmake/modules/TensorFlowCompile.cmake
Commit b9c24257c7b4da398798934ffefdd30015152180 by cjdb
Add list of LWG papers accepted by WG21 during the June 2021 plenary

Reviewed By: #libc, Quuxplusone, ldionne

Differential Revision: https://reviews.llvm.org/D105103
The file was modifiedlibcxx/docs/FormatIssuePaperStatus.csv
The file was modifiedlibcxx/docs/Cxx2aStatusPaperStatus.csv
The file was modifiedlibcxx/docs/Cxx2bStatusPaperStatus.csv
The file was modifiedlibcxx/docs/RangesIssuePaperStatus.csv

Summary

  1. [jenkins] Update script to use cross project lit test suite (details)
  2. Add chown to buildbot_qemu local repro instructions. (details)
  3. [sanitizer] Fix mips QEMU build (details)
  4. [scudo] Disable mips 32bit tests (details)
  5. [sanitizer] Don't tie builders with particular workers (details)
  6. [sanitizer] Missing image is infra issues (details)
  7. [sanitizer] Set EXE_LINKER_FLAGS same as SHARED_LINKER_FLAGS (details)
Commit e48da4b7b382fe94b714ce5aaaf02ee45e32825e by medismail.bennani
[jenkins] Update script to use cross project lit test suite

To reflect changes announced in
https://lists.llvm.org/pipermail/llvm-dev/2021-January/148048.html,
this patch updates all occurrences of `debuginfo-tests` to
`cross-project-debuginfo-tests`.

Differential Revision: https://reviews.llvm.org/D105134

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedzorg/jenkins/jobs/jobs/lldb-cmake
The file was modifiedzorg/jenkins/jobs/jobs/llvm-coverage
Commit 6b155f2b6b876096a8506594ddb627e0fed8e014 by 31459023+hctim
Add chown to buildbot_qemu local repro instructions.
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh
Commit 93ca31c2900b341a5f1535cae0243a454a832a1b by Vitaly Buka
[sanitizer] Fix mips QEMU build
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh
Commit 2a09e457cf5d095778714696a6bd2c061e5ac1e8 by Vitaly Buka
[scudo] Disable mips 32bit tests

It times out for unknown reasons.
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh
Commit d37259ec73a4341700e981214b9032631adfdda0 by Vitaly Buka
[sanitizer] Don't tie builders with particular workers

This simplifies management of VMs. We don't need to care which
are online. If some is gone we will just see less frequent builds.

Differential Revision: https://reviews.llvm.org/D105227
The file was modifiedbuildbot/osuosl/master/config/builders.py
Commit cef62f035b80b575d0b93b217880503f7558b1f9 by Vitaly Buka
[sanitizer] Missing image is infra issues

This avoids spamming blame list

Differential Revision: https://reviews.llvm.org/D105241
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh
Commit f4f163eefefeb65c22cf2d5c541406d0eefc4b6b by Vitaly Buka
[sanitizer] Set EXE_LINKER_FLAGS same as SHARED_LINKER_FLAGS
The file was modifiedzorg/buildbot/builders/sanitizers/buildbot_qemu.sh