Commit
6017cb31bb3548641465ea66219e11abc3106d38
by vsavchenko[analyzer][solver] Use all sources of constraints
Prior to this patch, we always gave priority to constraints that we actually know about symbols in question. However, these can get outdated and we can get better results if we look at all possible sources of knowledge, including sub-expressions.
Differential Revision: https://reviews.llvm.org/D105436
|
 | clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp |
 | clang/test/Analysis/constant-folding.c |
Commit
51ab17b91d2e3280d08c09648bb4950c0e217d20
by Raphael Isemann[lldb][docs] Fix reference warnings in python-reference.rst
References with a single '`' around them are interpreted as references instead of text with monospaced font since the introduction of the new Python API generator. This meant that all the single-quoted code in this document that doesn't reference any Python class was throwing sphinx errors. This just adds the neede extra ` around this code and fixed up the legitimate typos (e.g. `SBframe` -> `SBFrame`).
|
 | lldb/docs/use/python-reference.rst |
Commit
cbb09c5b2c2e0558de50355f4cbbbe2d2840073e
by akuegelRevert "[clang] fixes named return of variables with dependent alignment"
This reverts commit 21106388eb96c87b3f580c42a322c76a61605261. It causes a segfault in certain cases.
|
 | clang/lib/Sema/SemaStmt.cpp |
 | clang/test/CodeGen/nrvo-tracking.cpp |
 | clang/lib/AST/Decl.cpp |
 | clang/include/clang/AST/Decl.h |
 | clang/lib/Sema/SemaDecl.cpp |
Commit
f482497c381cf9beee513864123cf975bd72babf
by patacca[Polly][Isl] Use isl::set::tuple_dim, isl::map::domain_tuple_dim and isl::map::range_tuple_dim. NFC
This is part of an effort to reduce the differences between the custom C++ bindings used right now by polly in `lib/External/isl/include/isl/isl-noxceptions.h` and the official isl C++ interface.
Changes made: - Use `isl::set::tuple_dim` instead of `isl::set::dim` and `isl::set::n_dim` - Use `isl::map::domain_tuple_dim` instead of `isl::map::dim` - Use `isl::map::range_tuple_dim` instead of `isl::map::dim` - isl-noexceptions.h has been generated by this https://github.com/patacca/isl/commit/45576e1b4260f91946e4cf819485f57bd2ed5490
Note that not all the usage of `isl::{set,map}::dim` where replaced
Reviewed By: Meinersbur
Differential Revision: https://reviews.llvm.org/D104994
|
 | polly/lib/Transform/FlattenAlgo.cpp |
 | polly/lib/Support/ISLTools.cpp |
 | polly/lib/Transform/MatmulOptimizer.cpp |
 | polly/lib/Analysis/ScopInfo.cpp |
 | polly/lib/Transform/ScheduleTreeTransform.cpp |
 | polly/lib/Analysis/DependenceInfo.cpp |
 | polly/lib/Analysis/ScopBuilder.cpp |
 | polly/lib/External/isl/include/isl/isl-noexceptions.h |
 | polly/lib/CodeGen/PPCGCodeGeneration.cpp |
 | polly/lib/Transform/MaximalStaticExpansion.cpp |
 | polly/lib/Transform/ZoneAlgo.cpp |
Commit
17b701c43ca6459db020bff075b119f33a4a8ec5
by kerry.mclaughlin[LV] Collect a list of all element types found in the loop (NFC)
Splits `getSmallestAndWidestTypes` into two functions, one of which now collects a list of all element types found in the loop (`ElementTypesInLoop`). This ensures we do not have to iterate over all instructions in the loop again in other places, such as in D102253 which disables scalable vectorization of a loop if any of the instructions use invalid types.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D105437
|
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
Commit
0c29f45ac9e8e67a6481c0810e2e335a12bf3877
by uday[MLIR] Fix dialect conversion cancelRootUpdate
Fix dialect conversion ConversionPatternRewriter::cancelRootUpdate: the erasure of operations here from the list of root update was off by one. Should have been: ``` rootUpdates.erase(rootUpdates.begin() + (rootUpdates.rend() - it - 1)); ``` instead of ``` rootUpdates.erase(rootUpdates.begin() + (rootUpdates.rend() - it)); ```
or more directly: ``` rootUpdates.erase(it.base() - 1) ```
While on this, add an assertion to improve dev experience when a cancel is called on an op on which a root update hasn't been started.
Differential Revision: https://reviews.llvm.org/D105397
|
 | mlir/lib/Transforms/Utils/DialectConversion.cpp |
Commit
db646de3ee0181c93744b69cb51baeff17d70a00
by sebastian.neubauer[AMDGPU] Set optional PAL metadata
Set informational fields in the .shader_functions table.
Also correct the documentation, .scratch_memory_size and .lds_size are integers.
Differential Revision: https://reviews.llvm.org/D105116
|
 | llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp |
 | llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h |
 | llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp |
 | llvm/docs/AMDGPUUsage.rst |
 | llvm/test/CodeGen/AMDGPU/amdpal-callable.ll |
Commit
a0b1f3aac57a9becb28d6a9c50f4d2eee7ba6c82
by fmayer[hwasan] Check for overflow when searching candidates.
If the fault address is at the boundary of memory regions, this could cause us to segfault otherwise.
Ran test with old compiler_rt to make sure it fails.
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D105032
|
 | compiler-rt/lib/hwasan/hwasan_mapping.h |
 | compiler-rt/test/hwasan/TestCases/tag-mismatch-border-address.c |
 | compiler-rt/lib/hwasan/hwasan_report.cpp |
Commit
6c3451cd76cbd0cd973d9c2b08b168dcd0bce3c2
by flo[VPlan] Add VPReductionPHIRecipe (NFC).
This patch is a first step towards splitting up VPWidenPHIRecipe into separate recipes for the 3 distinct cases they model:
1. reduction phis, 2. first-order recurrence phis, 3. pointer induction phis.
This allows untangling the code generation and allows us to reduce the reliance on LoopVectorizationCostModel during VPlan code generation.
Discussed/suggested in D100102, D100113, D104197.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D104989
|
 | llvm/test/Transforms/LoopVectorize/vplan-printing.ll |
 | llvm/lib/Transforms/Vectorize/VPlanValue.h |
 | llvm/lib/Transforms/Vectorize/VPlan.cpp |
 | llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll |
 | llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp |
 | llvm/lib/Transforms/Vectorize/VPlan.h |
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
Commit
c9d747e9cd6db4a104980ad4358f70cba0a1a634
by jay.foad[AMDGPU] Remove outdated comment and tidy up. NFC.
This was left over from D94746.
|
 | llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp |
Commit
bbcbf21ae60c928e07dde6a1c468763b3209d1e6
by flo[VPlan] Add destructor to VPReductionRecipe to unbreak build.
Attempt to unbreak https://lab.llvm.org/buildbot/#/builders/67/builds/3363/steps/6/logs/stdio
|
 | llvm/lib/Transforms/Vectorize/VPlan.h |
Commit
3fed6d443f802c43aade1b5b1b09f5e2f8b3edb1
by flo[VPlan] Mark overriden function in VPWidenPHIRecipe as virtual.
VPReductionRecipe overrides those implementations. Mark them as virtual in the VPWidenPHIRecipe to unbreak build in certain configurations.
|
 | llvm/lib/Transforms/Vectorize/VPlan.h |
Commit
706bbfb35bd31051e46ac77aab3e9b2dbc3abe78
by floRevert "[VPlan] Add VPReductionPHIRecipe (NFC)." and follow-ups
This reverts commit 3fed6d443f802c43aade1b5b1b09f5e2f8b3edb1, bbcbf21ae60c928e07dde6a1c468763b3209d1e6 and 6c3451cd76cbd0cd973d9c2b08b168dcd0bce3c2.
The changes causing build failures with certain configurations, e.g. https://lab.llvm.org/buildbot/#/builders/67/builds/3365/steps/6/logs/stdio
lib/libLLVMVectorize.a(LoopVectorize.cpp.o): In function `llvm::VPRecipeBuilder::tryToCreateWidenRecipe(llvm::Instruction*, llvm::ArrayRef<llvm::VPValue*>, llvm::VFRange&, std::unique_ptr<llvm::VPlan, std::default_delete<llvm::VPlan> >&) [clone .localalias.8]': LoopVectorize.cpp:(.text._ZN4llvm15VPRecipeBuilder22tryToCreateWidenRecipeEPNS_11InstructionENS_8ArrayRefIPNS_7VPValueEEERNS_7VFRangeERSt10unique_ptrINS_5VPlanESt14default_deleteISA_EE+0x63b): undefined reference to `vtable for llvm::VPReductionPHIRecipe' collect2: error: ld returned 1 exit status
|
 | llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp |
 | llvm/lib/Transforms/Vectorize/VPlanValue.h |
 | llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll |
 | llvm/lib/Transforms/Vectorize/VPlan.cpp |
 | llvm/test/Transforms/LoopVectorize/vplan-printing.ll |
 | llvm/lib/Transforms/Vectorize/VPlan.h |
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
Commit
745758acf3c295e3bf9f9dd283a3568c912a1827
by fmayer[hwasan] Fix incorrect candidate matching for stack OOB.
We would find an address with matching tag, only to discover in ShowCandidate that it's very far away from [stack].
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D105197
|
 | compiler-rt/test/hwasan/TestCases/stack-oob.c |
 | compiler-rt/lib/hwasan/hwasan_report.cpp |
Commit
c5dfee44b983d7a96f2c1a234f83abf41c7e2443
by peter.waller[CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory
This avoids the use of the vector unit for copying from scalar to vector. There is an extra ptrue instruction, but a predicate register with the ptrue pattern populated is likely to be free in the context of real code.
Tests were generated from a template to cover the axes mentioned at the top of the test file.
Co-authored-by: Francesco Petrogalli <francesco.petrogalli@arm.com>
Differential Revision: https://reviews.llvm.org/D103170
|
 | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp |
 | llvm/test/CodeGen/AArch64/sve-ld1r.mir |
 | llvm/test/CodeGen/AArch64/sve-vector-splat.ll |
 | llvm/lib/Target/AArch64/AArch64InstrFormats.td |
 | llvm/test/CodeGen/AArch64/sve-ld1r.ll |
 | llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll |
 | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td |
 | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp |
Commit
a7512401e5a2cc7a1d0805fc4daf0c808e9d502d
by kerry.mclaughlin[LV] Prevent vectorization with unsupported element types.
This patch adds a TTI function, isElementTypeLegalForScalableVector, to query whether it is possible to vectorize a given element type. This is called by isLegalToVectorizeInstTypesForScalable to reject scalable vectorization if any of the instruction types in the loop are unsupported, e.g:
int foo(__int128_t* ptr, int N) #pragma clang loop vectorize_width(4, scalable) for (int i=0; i<N; ++i) ptr[i] = ptr[i] + 42;
This example currently crashes if we attempt to vectorize since i128 is not a supported type for scalable vectorization.
Reviewed By: sdesmalen, david-arm
Differential Revision: https://reviews.llvm.org/D102253
|
 | llvm/test/Transforms/LoopVectorize/AArch64/scalable-reductions.ll |
 | llvm/include/llvm/Analysis/TargetTransformInfo.h |
 | llvm/include/llvm/Analysis/TargetTransformInfoImpl.h |
 | llvm/lib/Analysis/TargetTransformInfo.cpp |
 | llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp |
 | llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h |
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
 | llvm/test/Transforms/LoopVectorize/AArch64/sve-illegal-type.ll |
Commit
f7d8754312bf3d10fb902d94f2bc84e3adf12ba4
by Louis Dionne[runtimes] Move enable_32bit to the DSL
This is necessary for from-scratch configurations to support the 32-bit mode of the test suite.
Differential Revision: https://reviews.llvm.org/D105435
|
 | libcxxabi/test/lit.site.cfg.in |
 | libunwind/test/lit.site.cfg.in |
 | libcxx/utils/libcxx/test/params.py |
 | libcxx/test/CMakeLists.txt |
 | libcxx/utils/libcxx/test/config.py |
 | libcxxabi/test/CMakeLists.txt |
 | libunwind/test/CMakeLists.txt |
 | libcxx/test/configs/legacy.cfg.in |
Commit
f814cd7406aa13e082fdf6fe8296178a77735a5a
by thakisRevert "[profile][test] Improve coverage-linkage.cpp"
This reverts commit 36ba86fe8a29cdf3251b786db7f342efde666cb2. Fails on some bots, see comments on https://reviews.llvm.org/rG36ba86fe8a29cdf3251b786db7f342efde666cb2
|
 | compiler-rt/test/profile/Linux/coverage-linkage.cpp |
Commit
6f3f9535fcafcde11d3b3ef72fdc0f357813e9da
by llvm-dev[CostModel][X86] i8/i16 sitofp/uitofp are sext/zext to i32 for sitofp
Provide a generic fallback that extends sub-i32 scalars before using the existing sitofp instructions.
These numbers can be tweaked for specific sse levels, but we should get the default handling in place first.
We get the extension for free for non-vector loads.
|
 | llvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll |
 | llvm/lib/Target/X86/X86TargetTransformInfo.cpp |
 | llvm/test/Analysis/CostModel/X86/uitofp.ll |
 | llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll |
 | llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll |
 | llvm/test/Analysis/CostModel/X86/sitofp.ll |
 | llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll |
 | llvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll |
Commit
ef0d147cdcaf170de80ca6bb0208a2a519fbf083
by floRecommit "[VPlan] Add VPReductionPHIRecipe (NFC)." and follow-ups.
This reverts commit 706bbfb35bd31051e46ac77aab3e9b2dbc3abe78.
The committed version moves the definition of VPReductionPHIRecipe out of an ifdef only intended for ::print helpers. This should resolve the build failures that caused the revert
|
 | llvm/lib/Transforms/Vectorize/VPlan.h |
 | llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll |
 | llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp |
 | llvm/test/Transforms/LoopVectorize/vplan-printing.ll |
 | llvm/lib/Transforms/Vectorize/VPlan.cpp |
 | llvm/lib/Transforms/Vectorize/VPlanValue.h |
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
Commit
cf005c4c5061ed34b2bd21ae104923c28b8a1b04
by Louis Dionne[libc++] NFC: Move the status docs to their own subdirectory
This cleans up the libcxx/doc directory quite a bit and will avoid the proliferation of status files in that directory as new standards are voted.
|
 | libcxx/docs/Status/Cxx17Issues.csv |
 | libcxx/docs/Status/Format.rst |
 | libcxx/docs/Status/RangesPaper.csv |
 | libcxx/docs/Status/Cxx20Issues.csv |
 | libcxx/docs/Cxx2aStatusPaperStatus.csv |
 | libcxx/docs/Cxx2aStatusIssuesStatus.csv |
 | libcxx/docs/Status/Cxx17.rst |
 | libcxx/docs/FormatProposalStatus.csv |
 | libcxx/docs/Cxx2bStatusIssuesStatus.csv |
 | libcxx/docs/Cxx1yStatus.rst |
 | libcxx/docs/index.rst |
 | libcxx/docs/Status/Cxx2bIssues.csv |
 | libcxx/docs/Status/FormatIssues.csv |
 | libcxx/docs/Cxx1zStatus.rst |
 | libcxx/docs/Cxx1yStatusIssuesStatus.csv |
 | libcxx/docs/RangesStatus.rst |
 | libcxx/docs/Cxx1zStatusIssuesStatus.csv |
 | libcxx/docs/Status/Cxx17Papers.csv |
 | libcxx/docs/Cxx2aStatus.rst |
 | libcxx/docs/Status/Cxx20Papers.csv |
 | libcxx/docs/RangesIssuePaperStatus.csv |
 | libcxx/docs/Status/Cxx14.rst |
 | libcxx/docs/OneRangesProposalStatus.csv |
 | libcxx/docs/Status/Cxx14Papers.csv |
 | libcxx/docs/Cxx2bStatusPaperStatus.csv |
 | libcxx/docs/Status/RangesIssues.csv |
 | libcxx/docs/Status/Cxx14Issues.csv |
 | libcxx/docs/Cxx2bStatus.rst |
 | libcxx/docs/Status/Cxx2bPapers.csv |
 | libcxx/docs/Status/FormatPaper.csv |
 | libcxx/docs/Status/Ranges.rst |
 | libcxx/docs/Status/Cxx20.rst |
 | libcxx/docs/FormatIssuePaperStatus.csv |
 | libcxx/docs/Status/Cxx2b.rst |
 | libcxx/docs/Cxx1yStatusPaperStatus.csv |
 | libcxx/docs/Cxx1zStatusPaperStatus.csv |
 | libcxx/docs/FormatStatus.rst |
Commit
5ffa051447c103b3950d7642c36e7c7f59c1a86d
by Louis Dionne[libc++] NFC: Remove outdated link to TS status
|
 | libcxx/docs/index.rst |
Commit
5ab9000fbb3057336ca33721096bb8766cb5b675
by bradley.smith[AArch64][SVE] Fix selection failures for scalable MLOAD nodes with passthru
Differential Revision: https://reviews.llvm.org/D105348
|
 | llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll |
 | llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll |
 | llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.h |
Commit
3eb2fc4b505159cd34f1cfe4ec2359420e44b916
by thakis[lld/mac] Partially implement -export_dynamic
This implements the part of -export_dynamic that adds external symbols as dead strip roots even for executables.
It does not yet implement the effect -export_dynamic has for LTO. I tried just replacing `config->outputType != MH_EXECUTE` with `(config->outputType != MH_EXECUTE || config->exportDynamic)` in LTO.cpp, but then local symbols make it into the symbol table too, which is too much (and also doesn't match ld64). So punt on this for now until I understand it better. (D91583 may or may not be related too).
Differential Revision: https://reviews.llvm.org/D105482
|
 | lld/MachO/Options.td |
 | lld/test/MachO/dead-strip.s |
 | lld/MachO/LTO.cpp |
 | lld/MachO/MarkLive.cpp |
 | lld/MachO/Config.h |
 | lld/MachO/Driver.cpp |
Commit
130ea3ceb47d36d247da83c897011d1b374e54fe
by aschwaighoferUse swift mangling for resume functions
The resume partial functions generated for swift suspend points will now use a Swift mangling suffix.
Await resume partial functions will use the suffix 'TQ'[0-9]+'_' (e.g "...TQ0_") and suspend resume partial functions will use the suffix 'TY'[0-9]+'_' (e.g "...TY1_").
Reviewed By: nate_chandler
Differential Revision: https://reviews.llvm.org/D104144
|
 | llvm/lib/Transforms/Coroutines/CoroSplit.cpp |
 | llvm/test/Transforms/Coroutines/coro-async.ll |
Commit
4e1a0684f13d833e6ddec94d9f7738b0a004e4c1
by a.bataev[SLP]Fix non-determinism in PHI sorting.
Compare type IDs and DFS numbering for basic block instead of addresses to fix non-determinism.
Differential Revision: https://reviews.llvm.org/D105031
|
 | llvm/test/Transforms/SLPVectorizer/X86/remark_unsupported.ll |
 | llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp |
Commit
ddfb074a80a24f94290d895b74d2c80626d953ba
by jonathanchesterfield[libomptarget][nfc] Group environment variables, drop accesses to DeviceInfo global
[libomptarget][nfc] Group environment variables, drop accesses to DeviceInfo global
Folds some duplicates logic into a helper function, passes the new environment struct into getLaunchVals which no longer reads the DeviceInfo global.
Implemented on top of D105237
Reviewed By: dhruvachak
Differential Revision: https://reviews.llvm.org/D105239
|
 | openmp/libomptarget/plugins/amdgpu/src/rtl.cpp |
Commit
37a92f3b03bf165245a9d0dc4830dcc6fed7c253
by paulsson[SystemZ] Generate XC loop for memset 0 of variable length.
Benchmarking has shown that it is worthwhile to implement a variable length memset of 0 with XC (exclusive or) like gcc does, instead of using a libcall.
This requires the use of the EXecute Relative Long (EXRL) instruction which can now be done in a framework that can also be used with other target instructions (not just XC).
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D103865
|
 | llvm/lib/Target/SystemZ/SystemZInstrFormats.td |
 | llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp |
 | llvm/lib/Target/SystemZ/SystemZAsmPrinter.h |
 | llvm/lib/Target/SystemZ/SystemZInstrInfo.td |
 | llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp |
 | llvm/lib/Target/SystemZ/SystemZISelLowering.cpp |
 | llvm/test/CodeGen/SystemZ/memset-05.ll |
Commit
f1cbea3e527547fc08c55235c11970a8d9f2637e
by shihpo.hung[RISCV] Remove Zvamo implication for v1.0-rc change
As v1.0-rc specs say Zvamo is removed from standard extension, Zvamo has to be specified explicitly.
Reviewed By: evandro
Differential Revision: https://reviews.llvm.org/D105396
|
 | clang/lib/Driver/ToolChains/Arch/RISCV.cpp |
 | clang/test/Preprocessor/riscv-target-features.c |
Commit
b298308ba2544a00c3e2ae0c1cc06fa058a4000c
by llvm-dev[CostModel][X86] fptosi/fptoui to i8/i16 are truncated from fptosi to i32
Provide a generic fallback that performs the fptosi to i32 types, then truncates to sub-i32 scalars.
These numbers can be tweaked for specific sse levels, but we should get the default handling in place first.
|
 | llvm/test/Analysis/CostModel/X86/fptoui.ll |
 | llvm/test/Analysis/CostModel/X86/fptosi.ll |
 | llvm/lib/Target/X86/X86TargetTransformInfo.cpp |
Commit
846a530e7db28bdd50c9a9fb08cddc210134b579
by aschwaighoferFix coro lowering of single predecessor phis
Code assumes that uses of single predecessor phis are not live accross suspend points. Cleanup any single predecessor phis preceeding the code making this assumption.
rdar://76020301
Differential Revision: https://reviews.llvm.org/D105488
|
 | llvm/test/Transforms/Coroutines/coro-async-phi.ll |
 | llvm/lib/Transforms/Coroutines/CoroFrame.cpp |
Commit
2b5e53111a24eebaa025d12832380638cb0598a1
by craig.topper[RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors.
This adds a DAG combine to detect sext/zext inputs and emit a new ISD opcode. The extends will either be removed or replaced with narrower extends.
Isel patterns are used to match add and widening mul to vwmacc similar to the recently added vmacc patterns.
There's still some work to be to match vmulsu. We should also rewrite splats that were extended as scalars and then splatted.
Reviewed By: arcbbb
Differential Revision: https://reviews.llvm.org/D104802
|
 | llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll |
 | llvm/lib/Target/RISCV/RISCVISelLowering.h |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaccu.ll |
 | llvm/lib/Target/RISCV/RISCVISelLowering.cpp |
 | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwacc.ll |
Commit
2b2ffb7bdc21bce33372fdd02571b94c2a5e774a
by jeremy.morse[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable locations that weren't supported: copies, and inter-block VRegs. There are still some locations that must be represented by DBG_VALUE such as constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks, vregs are allocated before isel begins, but the defining instruction might not exist until late in isel. To get around this, emit DBG_INSTR_REFs in a "half done" state, where the first operand refers to a VReg. Then at the end of isel, patch these back up to refer to instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I really don't want to have to put instruction numbers on copies. They don't define a value: they move them. To address this isel, salvageCopySSA interprets: * COPYs, * SUBREG_TO_REG, * Anything that isCopyInstr thinks is a copy. And follows chains of copies back to the defining instruction that they read from. This relies on any physical registers that COPYs read being defined in the same block, or being entry-block arguments. For the former we can put an instruction number on the defining instruction; for the latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
|
 | llvm/test/DebugInfo/X86/dbg-val-list-undef.ll |
 | llvm/include/llvm/CodeGen/MachineFunction.h |
 | llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll |
 | llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h |
 | llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp |
 | llvm/test/DebugInfo/X86/arg-dbg-value-list.ll |
 | llvm/lib/CodeGen/MachineFunction.cpp |
 | llvm/test/DebugInfo/X86/invalidated-dbg-value-is-undef.ll |
 | llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp |
Commit
458eac2573772a2b50e550360d1308b1b0c0f2bc
by paulsson[SystemZ] Support the 'N' code for the odd register in inline-asm.
The odd register of a (128 bit) register pair is accessed with the 'N' code with an inline assembly operand.
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D105502
|
 | llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp |
 | llvm/test/CodeGen/SystemZ/inline-asm-i128.ll |
Commit
74d6ce5d5f169e9cf3fac0eb1042602e286dd2b9
by efriedma[ScalarEvolution] Make getMinusSCEV() fail for unrelated pointers.
As part of making ScalarEvolution's handling of pointers consistent, we want to forbid multiplying a pointer by -1 (or any other value). This means we can't blindly subtract pointers.
There are a few ways we could deal with this: 1. We could completely forbid subtracting pointers in getMinusSCEV() 2. We could forbid subracting pointers with different pointer bases (this patch). 3. We could try to ptrtoint pointer operands.
The option in this patch is more friendly to non-integral pointers: code that works with normal pointers will also work with non-integral pointers. And it seems like there are very few places that actually benefit from the third option.
As a minimal patch, the ScalarEvolution implementation of getMinusSCEV still ends up subtracting pointers if they have the same base. This should eliminate the shared pointer base, but eventually we'll need to rewrite it to avoid negating the pointer base. I plan to do this as a separate step to allow measuring the compile-time impact.
This doesn't cause obvious functional changes in most cases; the one case that is significantly affected is ICmpZero handling in LSR (which is the source of almost all the test changes). The resulting changes seem okay to me, but suggestions welcome. As an alternative, I tried explicitly ptrtoint'ing the operands, but the result doesn't seem obviously better.
I deleted the test lsr-undef-in-binop.ll becuase I couldn't figure out how to repair it to test what it was actually trying to test.
Differential Revision: https://reviews.llvm.org/D104806
|
 | llvm/test/Transforms/LoopStrengthReduce/X86/expander-reused-value-insert-point.ll |
 | llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp |
 | llvm/test/CodeGen/PowerPC/pr42492.ll |
 | llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll |
 | llvm/lib/Transforms/Scalar/LoopRerollPass.cpp |
 | llvm/test/CodeGen/ARM/lsr-undef-in-binop.ll |
 | llvm/test/Transforms/LoopStrengthReduce/X86/eh-insertion-point.ll |
 | llvm/test/Transforms/LoopStrengthReduce/X86/eh-insertion-point-2.ll |
 | llvm/test/Transforms/LoopStrengthReduce/pr27056.ll |
 | llvm/lib/Analysis/ScalarEvolution.cpp |
 | llvm/lib/Analysis/StackSafetyAnalysis.cpp |
 | llvm/test/CodeGen/ARM/test-sharedidx.ll |
 | llvm/lib/Transforms/Scalar/AlignmentFromAssumptions.cpp |
 | llvm/test/Transforms/LoopStrengthReduce/X86/expander-crashes.ll |
 | llvm/include/llvm/Analysis/ScalarEvolution.h |
 | llvm/test/CodeGen/X86/update-terminator-debugloc.ll |
 | llvm/test/Analysis/StackSafetyAnalysis/local.ll |
 | llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll |
 | llvm/test/Transforms/LoopStrengthReduce/funclet.ll |
 | llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp |
Commit
600624a10326ad4be32be409e88b9b8580cef85d
by listmail[LoopVersion] Move an assert [nfc-ish]
|
 | llvm/lib/Transforms/Utils/LoopVersioning.cpp |
Commit
9ffa90d6c27e583bec9656a0aae5062ea5499094
by listmail[LV] Disable epilogue vectorization for non-latch exits
When skimming through old review discussion, I noticed a post commit comment on an earlier patch which had gone unaddressed. Better late (4 months), than never right?
I'm not aware of an active problem with the combination of non-latch exits and epilogue vectorization, but the interaction was not considered and I'm not modivated to make epilogue vectorization work with early exits. If there were a bug in the interaction, it would be pretty hard to hit right now (as we canonicalize towards bottom tested loops), but an upcoming change to allow multiple exit loops will greatly increase the chance for error. Thus, let's play it safe for now.
|
 | llvm/lib/Transforms/Vectorize/LoopVectorize.cpp |
Commit
8517a26d442fa1b3d01e52a83ae76023ba7c9784
by cjdb[libcxx][modularisation] splices `<iterator>` into individual headers
Differential Revision: https://reviews.llvm.org/D105076
|
 | libcxx/include/__iterator/ostream_iterator.h |
 | libcxx/include/__iterator/istream_iterator.h |
 | libcxx/include/__iterator/data.h |
 | libcxx/include/__iterator/reverse_iterator.h |
 | libcxx/include/__iterator/ostreambuf_iterator.h |
 | libcxx/include/__iterator/distance.h |
 | libcxx/include/__iterator/reverse_access.h |
 | libcxx/include/CMakeLists.txt |
 | libcxx/include/__iterator/size.h |
 | libcxx/include/__iterator/front_insert_iterator.h |
 | libcxx/include/__iterator/empty.h |
 | libcxx/include/__iterator/istreambuf_iterator.h |
 | libcxx/include/__iterator/access.h |
 | libcxx/include/__iterator/insert_iterator.h |
 | libcxx/include/__iterator/back_insert_iterator.h |
 | libcxx/include/iterator |
 | libcxx/test/support/test_iterators.h |
 | libcxx/include/__iterator/erase_if_container.h |
 | libcxx/include/module.modulemap |
Commit
35e8cc4979eaa61377c323fc8ff17dd7d09e1f20
by spatel[InstSimplify][test] add tests for poison propagation through FP calls; NFC
|
 | llvm/test/Transforms/InstSimplify/call.ll |
Commit
4ec7c021970d83ce49273ca5623953665720515f
by spatel[InstSimplify] fix bug in poison propagation for FP ops
If any operand of a math op is poison, that takes precedence over general undef/NaN.
This should not be visible with binary ops because it requires 2 constant operands to trigger (and if both operands of a binop are constant, that should get handled first in ConstantFolding).
|
 | llvm/lib/Analysis/InstructionSimplify.cpp |
 | llvm/test/Transforms/InstSimplify/call.ll |
Commit
7b6b15e010664ec444f3c20a9b15ff4324c8971c
by i[profile][test] Improve coverage-linkage.cpp with ld.lld --gc-sections
The __llvm_prf_names section uses SHF_GNU_RETAIN. However, GNU ld before 2015-10 (https://sourceware.org/bugzilla/show_bug.cgi?id=19161) neither supports it nor retains __llvm_prf_names according to __start___llvm_prf_names. So --gc-sections does not work on such old GNU ld.
This is not a problem for gold and sufficiently new lld.
|
 | compiler-rt/test/profile/Linux/coverage-linkage.cpp |
Commit
2ce0df4dfbead9eb0a91861c529910940c87593b
by Louis Dionne[libc++][docs] Overhaul the documentation for building and using libc++
This patch overhauls the documentation around building libc++ for vendors, and using libc++ for end-users. It also:
- Removes mention of the standalone build, which we've been trying to get rid of for a long time. - Removes mention of using a local ABI installation, which we don't do and is documented as "not recommended". - Removes mention of the separate libc++filesystem.a library, which isn't relevant anymore since filesystem support is in the main library. - Adds mention of the GDB pretty printers and how to use them.
|
 | libcxx/docs/index.rst |
 | libcxx/docs/BuildingLibcxx.rst |
 | libcxx/docs/UsingLibcxx.rst |
 | libcxx/utils/ci/run-buildbot |
Commit
045872f42203223450c96a518b6478d255a5d586
by wanyu9511[AIX] Define __TOS_AIX__ predefined macro
%%% Transfer the predefined macro, __TOS_AIX__, from the AIX XL C/C++ compilers.
__TOS_AIX__ indicates that the target operating system is AIX. %%%
Reviewed By: cebowleratibm
Differential Revision: https://reviews.llvm.org/D103587
|
 | clang/test/Preprocessor/init-ppc.c |
 | clang/lib/Basic/Targets/OSTargets.h |
Commit
a6d081b2cbc3348ed7261254ae7a563146b76d23
by efriedmaRevert "[ScalarEvolution] Make getMinusSCEV() fail for unrelated pointers."
This reverts commit 74d6ce5d5f169e9cf3fac0eb1042602e286dd2b9.
Seeing crashes on buildbots in MemoryDepChecker::isDependent.
|
 | llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll |
 | llvm/test/Transforms/LoopStrengthReduce/X86/eh-insertion-point.ll |
 | llvm/include/llvm/Analysis/ScalarEvolution.h |
 | llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp |
 | llvm/test/Transforms/LoopStrengthReduce/X86/expander-crashes.ll |
 | llvm/test/Analysis/StackSafetyAnalysis/local.ll |
 | llvm/test/Transforms/LoopStrengthReduce/pr27056.ll |
 | llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp |
 | llvm/lib/Transforms/Scalar/LoopRerollPass.cpp |
 | llvm/test/CodeGen/X86/update-terminator-debugloc.ll |
 | llvm/test/Transforms/LoopStrengthReduce/funclet.ll |
 | llvm/test/CodeGen/PowerPC/pr42492.ll |
 | llvm/test/Transforms/LoopStrengthReduce/X86/eh-insertion-point-2.ll |
 | llvm/test/CodeGen/ARM/test-sharedidx.ll |
 | llvm/lib/Transforms/Scalar/AlignmentFromAssumptions.cpp |
 | llvm/test/CodeGen/ARM/lsr-undef-in-binop.ll |
 | llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll |
 | llvm/lib/Analysis/StackSafetyAnalysis.cpp |
 | llvm/lib/Analysis/ScalarEvolution.cpp |
 | llvm/test/Transforms/LoopStrengthReduce/X86/expander-reused-value-insert-point.ll |
Commit
7a46d8f50c59e9ca0f180e7dbdd7db7bbe4b272b
by llvmgnsyncbot[gn build] Port 8517a26d442f
|
 | llvm/utils/gn/secondary/libcxx/include/BUILD.gn |
Commit
be0924ad179eb7113fb7539bb2d7fc681ffd9ed9
by david.green[Tests] Update some tests for D104765. NFC
|
 | llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll |
 | llvm/test/CodeGen/ARM/add-like-or.ll |
 | llvm/test/CodeGen/SystemZ/addr-01.ll |
 | llvm/test/CodeGen/SystemZ/addr-02.ll |
Commit
2b0d95fb584e6d6409c57c84bd992f3d62b0eac6
by mgorny[openmp] [test] Add missing <limits> include to capacity_nthreads
Differential Revision: https://reviews.llvm.org/D105474
|
 | openmp/runtime/test/tasking/hidden_helper_task/capacity_nthreads.cpp |
Commit
2d68bb1765f978f0426f1face22e4ff37439a224
by mgorny[compiler-rt] [test] Fix asan symbolize tests on py3.10
Update the asan_symbolize_script for changes in argparse output in Python 3.10. The parser output 'options' instead of 'optional arguments'.
Differential Revision: https://reviews.llvm.org/D105489
|
 | compiler-rt/test/asan/TestCases/Posix/asan_symbolize_script/plugin_no_op_help_output.cpp |
 | compiler-rt/test/asan/TestCases/Posix/asan_symbolize_script/logging_options_in_help.cpp |
Commit
12d51f95fe7fe8d4aec234c2b842478f75154273
by craig.topper[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno
These are fp->int conversions using either RMM or dynamic rounding modes.
The lround and lrint opcodes have a return type of either i32 or i64 depending on sizeof(long) in the frontend which should follow xlen. llround/llrint should always return i64 so we'll need a libcall for those on rv32.
The frontend will only emit the intrinsics if -fno-math-errno is in effect otherwise a libcall will be emitted which will not use these ISD opcodes.
gcc also does this optimization.
Reviewed By: arcbbb
Differential Revision: https://reviews.llvm.org/D105206
|
 | llvm/test/CodeGen/RISCV/float-intrinsics.ll |
 | llvm/test/CodeGen/RISCV/half-intrinsics.ll |
 | llvm/test/CodeGen/RISCV/double-intrinsics.ll |
 | llvm/lib/Target/RISCV/RISCVISelLowering.cpp |
 | llvm/lib/Target/RISCV/RISCVInstrInfoF.td |
 | llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td |
 | llvm/lib/Target/RISCV/RISCVInstrInfoD.td |
Commit
5d2511c38988af69af4b4162ef40f2eb0268a610
by Louis Dionne[libc++] NFC: Sort header lists and remove outdated comments in modulemap
|
 | libcxx/include/CMakeLists.txt |
 | libcxx/include/module.modulemap |
Commit
6e43f3fc141f73a50638aab159de92c1c6d257da
by Louis Dionne[libc++] Do not set CMAKE_BUILD_WITH_INSTALL_NAME_DIR
I'm not sure what that gains us, and it creates a problem when trying to run the tests against libc++ with a custom install name dir (e.g. /usr/lib), since the library that we link against (in the build tree) will advertise itself as /usr/lib/libc++.dylib, so we end up linking against the system dylib at runtime.
Differential Revision: https://reviews.llvm.org/D105499
|
 | libcxx/CMakeLists.txt |
 | libcxx/utils/ci/runtimes/CMakeLists.txt |
Commit
7ac1c7bead90757b5a135747810e41e8ffae5951
by efriedmaRecommit [ScalarEvolution] Make getMinusSCEV() fail for unrelated pointers.
As part of making ScalarEvolution's handling of pointers consistent, we want to forbid multiplying a pointer by -1 (or any other value). This means we can't blindly subtract pointers.
There are a few ways we could deal with this: 1. We could completely forbid subtracting pointers in getMinusSCEV() 2. We could forbid subracting pointers with different pointer bases (this patch). 3. We could try to ptrtoint pointer operands.
The option in this patch is more friendly to non-integral pointers: code that works with normal pointers will also work with non-integral pointers. And it seems like there are very few places that actually benefit from the third option.
As a minimal patch, the ScalarEvolution implementation of getMinusSCEV still ends up subtracting pointers if they have the same base. This should eliminate the shared pointer base, but eventually we'll need to rewrite it to avoid negating the pointer base. I plan to do this as a separate step to allow measuring the compile-time impact.
This doesn't cause obvious functional changes in most cases; the one case that is significantly affected is ICmpZero handling in LSR (which is the source of almost all the test changes). The resulting changes seem okay to me, but suggestions welcome. As an alternative, I tried explicitly ptrtoint'ing the operands, but the result doesn't seem obviously better.
I deleted the test lsr-undef-in-binop.ll becuase I couldn't figure out how to repair it to test what it was actually trying to test.
Recommitting with fix to MemoryDepChecker::isDependent.
Differential Revision: https://reviews.llvm.org/D104806
|
 | llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp |
 | llvm/lib/Analysis/StackSafetyAnalysis.cpp |
 | llvm/test/Analysis/StackSafetyAnalysis/local.ll |
 | llvm/test/Transforms/LoopStrengthReduce/X86/expander-reused-value-insert-point.ll |
 | llvm/test/Transforms/LoopStrengthReduce/pr27056.ll |
 | llvm/test/Transforms/LoopStrengthReduce/X86/eh-insertion-point-2.ll |
 | llvm/test/CodeGen/ARM/test-sharedidx.ll |
 | llvm/include/llvm/Analysis/ScalarEvolution.h |
 | llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp |
 | llvm/test/CodeGen/PowerPC/pr42492.ll |
 | llvm/test/CodeGen/X86/update-terminator-debugloc.ll |
 | llvm/test/Transforms/LoopStrengthReduce/X86/eh-insertion-point.ll |
 | llvm/lib/Transforms/Scalar/AlignmentFromAssumptions.cpp |
 | llvm/test/CodeGen/ARM/lsr-undef-in-binop.ll |
 | llvm/lib/Analysis/LoopAccessAnalysis.cpp |
 | llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll |
 | llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll |
 | llvm/lib/Transforms/Scalar/LoopRerollPass.cpp |
 | llvm/test/Transforms/LoopStrengthReduce/funclet.ll |
 | llvm/test/Transforms/LoopStrengthReduce/X86/expander-crashes.ll |
 | llvm/lib/Analysis/ScalarEvolution.cpp |
Commit
76f734040a54622b847729e5acb4480e667d2c74
by thakis[lld/mac] Give several LTO tests an "lto-" prefix
Differential Revision: https://reviews.llvm.org/D105476
|
 | lld/test/MachO/lto-mattrs.ll |
 | lld/test/MachO/lto-linkonce.ll |
 | lld/test/MachO/lto-codemodel.ll |
 | lld/test/MachO/codemodel.ll |
 | lld/test/MachO/module-asm.ll |
 | lld/test/MachO/internalize.ll |
 | lld/test/MachO/lto-module-asm.ll |
 | lld/test/MachO/lto-internalize.ll |
 | lld/test/MachO/lto-objc-arc-contract.ll |
 | lld/test/MachO/linkonce.ll |
 | lld/test/MachO/objc-arc-contract.ll |
 | lld/test/MachO/bitcode-nodatalayout.ll |
 | lld/test/MachO/lto-cpu-string.ll |
 | lld/test/MachO/mattrs.ll |
 | lld/test/MachO/invalid/lto-bitcode-nodatalayout.ll |
 | lld/test/MachO/cpu-string.ll |
Commit
94e01d579c1954bed2dbd2d82a64ff72baf72223
by kparzysz[Hexagon] Generate trap/undef if misaligned access is detected
This applies to memory accesses to (compile-time) constant addresses (such as memory-mapped registers). Currently when a misaligned access to such an address is detected, a fatal error is reported. This change will emit a remark, and the compilation will continue with a trap, and "undef" (for loads) emitted.
This fixes https://llvm.org/PR50838.
Differential Revision: https://reviews.llvm.org/D50524
|
 | llvm/test/CodeGen/Hexagon/misaligned-const-load.ll |
 | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp |
 | llvm/lib/Target/Hexagon/HexagonISelLowering.h |
 | llvm/test/CodeGen/Hexagon/misaligned-const-store.ll |
Commit
8d69635ed9ecf36fd0ca85906bfde17949671cbe
by Tony.Tye[NFC][AMDGPU] Add link to AMD GPU gfx906 instruction set architecture
Reviewed By: kzhuravl
Differential Revision: https://reviews.llvm.org/D105377
|
 | llvm/docs/AMDGPUUsage.rst |
Commit
aff66b7eef467e2f8d89877b2864daa3888b1c13
by Stanislav.Mekhanoshin[AMDGPU] Fix pass name of AMDGPULowerKernelAttributes. NFC.
This was obviously copy-pasted.
|
 | llvm/lib/Target/AMDGPU/AMDGPULowerKernelAttributes.cpp |
Commit
5915d33874fd0278f72f2c1a8cf2047bdf0ffd31
by Stanislav.Mekhanoshin[AMDGPU] Do not run IR optimizations at -O0
Differential Revision: https://reviews.llvm.org/D105515
|
 | llvm/test/CodeGen/AMDGPU/llc-pipeline.ll |
 | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp |
Commit
a0ab45799b597f5523b14e5910e25256f5b8a489
by Stanislav.Mekhanoshin[AMDGPU] Move atomic expand past infer address spaces
There are cases where infer address spaces pass cannot yet infer an address space in the opt pipeline and then in the llc pipeline it runs too late for atomic expand pass to benefit from a specific address space.
Move atomic expand pass past the infer address spaces.
Fixes: SWDEV-293410
Differential Revision: https://reviews.llvm.org/D105511
|
 | llvm/test/CodeGen/AMDGPU/global-atomics-fp.ll |
 | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp |
 | llvm/test/CodeGen/AMDGPU/llc-pipeline.ll |
Commit
6c9559b67b91966bfeff9e17808a3e84a92e64a0
by dblaikieDebugInfo: Mangle K&R declarations for debug info linkage names
This fixes a gap in the `overloadable` attribute support (K&R declared functions would get mangled symbol names, but that name wouldn't be represented in the debug info linkage name field for the function) and in -funique-internal-linkage-names (this came up in review discussion on D98799) where K&R static declarations would not get the uniqued linkage names.
|
 | clang/test/CodeGen/overloadable-debug.c |
 | clang/lib/AST/ItaniumMangle.cpp |
 | clang/test/CodeGen/unique-internal-linkage-names-dwarf.c |
 | clang/lib/CodeGen/CGDebugInfo.cpp |
Commit
56b3e9edc49314e874c9d52e9d5f5cf08f62c948
by efriedma[AArch64] Sync isDef32 to the current x86 version.
We should probably come up with some better way to do this, but let's make sure to catch known issues for now.
|
 | llvm/lib/Target/AArch64/AArch64ISelLowering.h |
Commit
75eb43ab490fd8e16c231fc40e9ec589c867cee5
by efriedma[AArch64] Add more tests related to vselect with constant condition.
Not a complete set of tests, but a starting point if anyone wants to look at improving this.
|
 | llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll |
Commit
f2d5fce86e81a8b37fbc0829a1c68b6eb48f8365
by mizvekov[clang] fixes named return of variables with dependent alignment
Named return of a variable with aligned attribute would trip an assert in case alignment was dependent.
Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>
Reviewed By: rsmith
Differential Revision: https://reviews.llvm.org/D105380
|
 | clang/test/CXX/class/class.init/class.copy.elision/p3.cpp |
 | clang/lib/Sema/SemaStmt.cpp |
 | clang/test/CodeGen/nrvo-tracking.cpp |
 | clang/lib/Sema/SemaDecl.cpp |
 | clang/lib/AST/Decl.cpp |
 | clang/include/clang/AST/Decl.h |
Commit
3553698de7a1033bd9ca79f9cfee83c85f4e20d4
by nemanja.i.ibm[PowerPC] Re-enable combine for i64 BSWAP on targets without LDBRX
The combine was disabled in 4e22c7265d86 as it caused failures in the ppc64be-multistage (bootstrap) bot. It turns out that the combine did not correctly update the MMO for the high load which caused aliased stores to be reported as unaliased. This patch fixes that problem and re-enables the combine.
|
 | llvm/lib/Target/PowerPC/PPCISelLowering.cpp |
 | llvm/test/CodeGen/PowerPC/bswap-load-store.ll |
 | llvm/test/CodeGen/PowerPC/ld-bswap64-no-ldbrx.ll |
Commit
7f1c077c3014760030cbaebdfccb8f99a4ec41c5
by tstellartests/CodeGen: Use %python lit substitution when invoking python
This will use the python that LLVM was configured to use rather than python from PATH.
Reviewed By: serge-sans-paille
Differential Revision: https://reviews.llvm.org/D105224
|
 | llvm/test/CodeGen/SystemZ/Large/branch-range-11.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-04.py |
 | llvm/test/CodeGen/SystemZ/Large/spill-02.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-08.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-01.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-06.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-03.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-05.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-07.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-09.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-10.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-13.py |
 | llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-12.py |
 | llvm/test/CodeGen/NVPTX/wmma.py |
 | llvm/test/CodeGen/SystemZ/Large/branch-range-02.py |
 | llvm/test/CodeGen/SystemZ/Large/spill-01.py |
Commit
11d88c4acb682d672a216ec1b684ea0b53ce94e7
by uday[MLIR][NFC] Move normalizeAffine methods to Affine utils
The normalizeAffineForOp and normalizedAffineParallel methods were misplaced in the AffineLoopNormalize pass file while their declarations were in affine utils. Move these to affine Utils.cpp. NFC.
Differential Revision: https://reviews.llvm.org/D105468
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 | mlir/lib/Dialect/Affine/Transforms/AffineLoopNormalize.cpp |
 | mlir/lib/Dialect/Affine/Utils/Utils.cpp |
Commit
fc82409b5ce5ddcd038ff0bf192a9a2a03b23020
by johannes[Attributor] Simplify operands inside of simplification AAs first
When we do simplification via AAPotentialValues or AAValueConstantRange we need to simplify the operands of an instruction we deconstruct first. This does not only improve the result, see for example range.ll, but is required as we allow outside AAs to provide simplification rules via callbacks. If we do ignore the simplification rules and base other simplifications on the IR instead we can create an inconsistent state.
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 | llvm/test/Transforms/Attributor/potential.ll |
 | llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll |
 | llvm/test/Transforms/Attributor/cb_range_enabled.ll |
 | llvm/test/Transforms/Attributor/cgscc_bugs.ll |
 | llvm/test/Transforms/Attributor/IPConstantProp/PR16052.ll |
 | llvm/test/Transforms/Attributor/lvi-after-jumpthreading.ll |
 | llvm/test/Transforms/Attributor/depgraph.ll |
 | llvm/test/Transforms/Attributor/range.ll |
 | llvm/test/Transforms/Attributor/callgraph.ll |
 | llvm/test/Transforms/Attributor/liveness.ll |
 | llvm/test/Transforms/Attributor/nonnull.ll |
 | llvm/test/Transforms/Attributor/dereferenceable-1.ll |
 | llvm/test/Transforms/Attributor/value-simplify.ll |
 | llvm/lib/Transforms/IPO/AttributorAttributes.cpp |
 | llvm/test/Transforms/Attributor/willreturn.ll |
 | llvm/test/Transforms/Attributor/ArgumentPromotion/inalloca.ll |
 | llvm/include/llvm/Transforms/IPO/Attributor.h |
 | llvm/test/Transforms/Attributor/internalize.ll |
 | llvm/lib/Transforms/IPO/Attributor.cpp |
Commit
aa3768278d4b1c91e6e55b596fa0d832a25428dc
by johannes[Attributor] Introduce a helper function to deal with undef + none
We often need to deal with the value lattice that contains none and undef as special values. A simple helper makes this much nicer.
Differential Revision: https://reviews.llvm.org/D103857
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 | llvm/test/Transforms/Attributor/nocapture-2.ll |
 | llvm/test/Transforms/Attributor/nonnull.ll |
 | llvm/include/llvm/Transforms/IPO/Attributor.h |
 | llvm/test/Transforms/Attributor/returned.ll |
 | llvm/test/Transforms/Attributor/dereferenceable-1.ll |
 | llvm/test/Transforms/Attributor/range.ll |
 | llvm/test/Transforms/Attributor/lvi-after-jumpthreading.ll |
 | llvm/test/Transforms/Attributor/liveness.ll |
 | llvm/test/Transforms/Attributor/potential.ll |
 | llvm/lib/Transforms/IPO/AttributorAttributes.cpp |
 | llvm/test/Transforms/Attributor/value-simplify.ll |
 | llvm/lib/Transforms/IPO/Attributor.cpp |
Commit
9bd2ee07885cc1ef47dedd0b827908f51fb3565f
by johannes[Attriibutor][NFC] Precommit heap-2-stack test case
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 | llvm/test/Transforms/Attributor/heap_to_stack.ll |
Commit
168a9234d7bbeebec3a5f16c619b68a3eba7b114
by johannes[Attributor][FIX] Replace uses first, then values
Before we replaced value by registering all their uses. However, as we replace a value old uses become stale. We now replace values explicitly and keep track of "new values" when doing so to avoid replacing only uses in stale/old values but not their replacements.
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 | llvm/include/llvm/Transforms/IPO/Attributor.h |
 | llvm/lib/Transforms/IPO/Attributor.cpp |
 | llvm/test/Transforms/Attributor/potential.ll |