Changes

[AMDGPU] isPassEnabled() helper to check cl::opt and OptLevel

We have several checks for both cl::opt and OptLevel over our
pass config, although these checks do not properly work if
default value of a cl::opt will be false. Create a helper to
use instead and properly handle it. NFC for now.

Differential Revision: https://reviews.llvm.org/D105517

[Clang][RISCV] Implement vlseg and vlsegff.

Differential Revision: https://reviews.llvm.org/D103527

[MLIR] Split out GPU ops library from Transforms

Split out GPU ops library from GPU transforms. This allows libraries to
depend on GPU Ops without needing/building its transforms.

Differential Revision: https://reviews.llvm.org/D105472

[llvm-readobj][test] Improve grouped option test

[MLIR] Simplify affine.if having yield values and trivial conditions

When an affine.if operation is returning/yielding results and has a
trivially true or false condition, then its 'then' or 'else' block,
respectively, is promoted to the affine.if's parent block and then, the
affine.if operation is replaced by the correct results/yield values.
Relevant test cases are also added.

Signed-off-by: Srishti Srivastava <srishti.srivastava@polymagelabs.com>

Differential Revision: https://reviews.llvm.org/D105418

[flang] Create HostAssocDetails symbols when needed for mis-parsed ArrayRef

Name resolution is always creating symbols with HostAssocDetails
for host variable names inside internal procedures. This helps lowering
identifying and dealing with such variables inside internal procedures.

However, the case where the variable appears in an ArrayRef mis-parsed
as a FunctionRef goes through a different name resolution path that did
not create such HostAssocDetails when needed. Pointer assignment RHS
are also skipping this path.

Add the logic to create HostAssocDetails for host symbols inisde internal
procedures that appear in mis-parsed ArrayRef or in pointer assignment RHS.

Differential Revision: https://reviews.llvm.org/D105464

[AMDGPU] Simplify tablegen files. NFC.

There is no need to cast records to strings before comparing them.

[mlir][Linalg] Add an InitTensor -> DimOp canonicalization pattern.

Differential Revision: https://reviews.llvm.org/D105537

[mlir] factor out common parts of the converstion to the LLVM dialect

"Standard-to-LLVM" conversion is one of the oldest passes in existence. It has
become quite large due to the size of the Standard dialect itself, which is
being split into multiple smaller dialects. Furthermore, several conversion
features are useful for any dialect that is being converted to the LLVM
dialect, which, without this refactoring, creates a dependency from those
conversions to the "standard-to-llvm" one.

Put several of the reusable utilities from this conversion to a separate
library, namely:
- type converter from builtin to LLVM dialect types;
- utility for building and accessing values of LLVM structure type;
- utility for building and accessing values that represent memref in the LLVM
  dialect;
- lowering options applicable everywhere.

Additionally, remove the type wrapping/unwrapping notion from the type
converter that is no longer relevant since LLVM types has been reimplemented as
first-class MLIR types.

Reviewed By: pifon2a

Differential Revision: https://reviews.llvm.org/D105534

[SVE] Fix cast<FixedVectorType> in truncateToMinimalBitwidths

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D104239

[Clang] Add test dependency on llvm-ar

Following clang driver tests invoke llvm-ar, so ensure that
check-clang rebuilds llvm-ar.

 * test/Driver/clang-offload-bundler.c
 * test/Driver/hip-link-save-temps.hip
 * test/Driver/hip-link-static-library.hip
 * test/Driver/hip-toolchain-rdc-static-lib.hip

Differential Revision: https://reviews.llvm.org/D105285

[DAG] Reassociate Add with Or

We already have reassociation code for Adds and Ors separately in DAG
combiner, this adds it for the combination of the two where Ors act like
Adds. It reassociates (add (or (x, c), y) -> (add (add (x, y), c)) where
we know that the Ors operands have no common bits set, and the Or has
one use.

Differential Revision: https://reviews.llvm.org/D104765

[mlir][CAPI] Export mlirValueEqual in C API

Somehow it is not exported in C API.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D105422

Add Log1pOp to complex dialect.

Also add a lowering pattern from Complex to Standard/Math dialect.

Differential Revision: https://reviews.llvm.org/D105538

[SVE] Fixed cast<FixedVectorType> on scalable vector in SelectionDAGBuilder::getUniformBase

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D105350

[NFC] Remove duplicate function calls

Removed repeated call of L->getHeader(). Now using previously stored return value.

Patch by Dmitry Makogon!

Differential Revision: https://reviews.llvm.org/D105535
Reviewed By: mkazantsev

[libc++] Implement copyable-box from Ranges

Differential Revision: https://reviews.llvm.org/D102135

[gn build] Port 6829db727e9e

[CostModel][X86] Adjust sitofp/uitofp SSE/AVX legalized costs based on llvm-mca reports.

Update (mainly) vXi8/vXi16 -> vXf32/vXf64 sitofp/uitofp costs based on the worst case costs from the script in D103695.

Move to using legalized types wherever possible, which allows us to prune the cost tables.

[mlir][Linalg] Proper handling of ForOp and TiledLoopOp

The `bufferizesToMemoryRead` condition was too optimistics in the case
of operands that map to a block argument.
This is the case for ForOp and TiledLoopOp.
For such ops, forward the call to all uses of the matching BBArg.

Differential Revision: https://reviews.llvm.org/D105540

Refactor GenericPadTensorOpVectorizationPattern

Refactor the original code to rewrite a PadTensorOp into a
sequence of InitTensorOp, FillOp and InsertSliceOp without
vectorization by default. `GenericPadTensorOpVectorizationPattern`
provides a customized OptimizeCopyFn to vectorize the
copying step.

Reviewed By: silvas, nicolasvasilache, springerm

Differential Revision: https://reviews.llvm.org/D105293

[mlir][Linalg] Rewrite PadTensorOp to enable its comprehensive bufferization.

Add the rewrite of PadTensorOp to InitTensor + InsertSlice before the
bufferization analysis starts.

This is exercised via a more advanced integration test.

Since the new behavior triggers folding, 2 tests need to be updated.
One of those seems to exhibit a folding issue with `switch` and is modified.

Differential Revision: https://reviews.llvm.org/D105549

[mlir] Move common reshapeops-related code to ReshapeOpsUtils.h.

This is a first step to move (Tensor)Expand/CollapseShapeOp to tensor/memref
dialects.

Differential Revision: https://reviews.llvm.org/D105547

[OPENMP]Remove const firstprivate allocation as a variable in a constant space.

Current implementation is not compatible with asynchronous target
regions, need to remove it.

Differential Revision: https://reviews.llvm.org/D105375

[CostModel][X86] Adjust sext/zext SSE/AVX legalized costs based on llvm-mca reports.

Update costs based on the worst case costs from the script in D103695.

Move to using legalized types wherever possible, which allows us to prune the cost tables.

[IndVarSimplify][X86] Regenerate loop-invariant-conditions.ll test checks

[AIX] Use VSSRC/VSFRC Register classes for f32/f64 callee arguments on P8 and above

Adding usage of VSSRC and VSFRC when adding the live in registers on AIX.
This matches the behaviour of the rest of PPC Subtargets.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D104396

[coro async] Move code to proper switch

While upstreaming patches this code somehow was applied to the wrong switch statement.

Differential Revision: https://reviews.llvm.org/D105504

[mlir] Use indices instead of affine maps when composing 2 reshape ops.

https://llvm.discourse.group/t/rfc-reshape-ops-restructuring/3310

Differential Revision: https://reviews.llvm.org/D105550

[CostModel] Express cost(urem) as cost(div+mul+sub) when set to Expand.

The Legalizer expands the operations of urem/srem into a div+mul+sub or divrem
when those are legal/custom. This patch changes the cost-model to reflect that
cost.

Since there is no 'divrem' Instruction in LLVM IR, the cost of divrem
is assumed to be the same as div+mul+sub since the three operations will
need to be executed at runtime regardless.

Patch co-authored by David Sherwood (@david-arm)

Reviewed By: RKSimon, paulwalker-arm

Differential Revision: https://reviews.llvm.org/D103799

[libc++] NFC: Fix incorrect comments in CMake

unittests: Fix build with LLVM_LINK_LLVM_DYLIB=ON

The build system was linking the PluginsTests unittest against libLLVM.so
and LLVMAsmParser which was causing the test to fail with this error:

LLVM ERROR: inconsistency in registered CommandLine options

We need to add llvm libraries to LLVM_LINK_COMPONENTS so that
they are dropped from the linker arguments when linking with
LLVM_LINK_LLVM_DYLIB=ON

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D105523

unittests: Fix library dependency name

Corrects the library name of LLVMAsmParser added in
2e4ec3e5d6a3bf7f61bea6898286cba64be7b764.

[Polly][Isl] Use isl::union_set::unite() instead of isl::union_set::add_set(). NFC

This is part of an effort to reduce the differences between the custom C++ bindings used right now by polly in `lib/External/isl/include/isl/isl-noxceptions.h` and the official isl C++ interface.

Changes made:
 - Use `isl::union_set::unite()` instead of `isl::union_set::add_set()`
 - `isl-noexceptions.h` has been generated by this https://github.com/patacca/isl/commit/390c44982b5cee7eb43f8f7a80e185e6d21466b2

Depends on D104994

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D105444

[SVE] Fix ShuffleVector cast<FixedVectorType> in truncateToMinimalBitwidths

Depends on D104239

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D105341

[AArch64][GlobalISel] Lower vector types for min/max

Differential Revision: https://reviews.llvm.org/D105433

[LV] Unconditionally branch from middle to scalar preheader if the scalar loop must execute (try 4)

Resubmit after the following changes:

* Fix a latent bug related to unrolling with required epilogue (see e49d65f). I believe this is the cause of the prior PPC buildbot failure.
* Disable non-latch exits for epilogue vectorization to be safe (9ffa90d)
* Split out assert movement (600624a) to reduce churn if this gets reverted again.

Previous commit message (try 3)

Resubmit after fixing test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll

Previous commit message...

This is a resubmit of 3e5ce4 (which was reverted by 7fe41ac).  The original commit caused a PPC build bot failure we never really got to the bottom of.  I can't reproduce the issue, and the bot owner was non-responsive.  In the meantime, we stumbled across an issue which seems possibly related, and worked around a latent bug in 80e8025.  My best guess is that the original patch exposed that latent issue at higher frequency, but it really is just a guess.

Original commit message follows...

If we know that the scalar epilogue is required to run, modify the CFG to end the middle block with an unconditional branch to scalar preheader. This is instead of a conditional branch to either the preheader or the exit block.

The motivation to do this is to support multiple exit blocks. Specifically, the current structure forces us to identify immediate dominators and *which* exit block to branch from in the middle terminator. For the multiple exit case - where we know require scalar will hold - these questions are ill formed.

This is the last change needed to support multiple exit loops, but since the diffs are already large enough, I'm going to land this, and then enable separately. You can think of this as being NFCIish prep work, but the changes are a bit too involved for me to feel comfortable tagging the review that way.

Differential Revision: https://reviews.llvm.org/D94892

[SystemZ][z/OS][libcxx] mark aligned allocation tests UNSUPPORTED on z/OS

zOS doesn't support aligned allocation, so these tests are failing.
For more details on aligned allocation in zOS, see
https://reviews.llvm.org/D87611 and https://reviews.llvm.org/D90178

Reviewed By: ldionne, #libc

Differential Revision: https://reviews.llvm.org/D102798

[LIBC] Add an optimized memcmp implementation for AArch64

Differential Revision: https://reviews.llvm.org/D105441

[coro async] Cap the alignment of spilled values (vs.  allocas) at the max frame alignment

Before this patch we would normally use the ABI alignment which can be
to high for the context alginment.

For spilled values we don't need ABI alignment, since the frame entry's
address is not escaped.

rdar://79664965

Differential Revision: https://reviews.llvm.org/D105288

[LLDB][GUI] Add initial forms support

This patch adds initial support for forms for the LLDB GUI. The currently
supported form elements are Text fields, Integer fields, Boolean fields, Choices
fields, File fields, Directory fields, and List fields.

A form can be created by subclassing FormDelegate. In the constructor, field
factory methods can be used to add new fields, storing the returned pointer in a
member variable. One or more actions can be added using the AddAction method.
The method takes a function with an interface void(Window &). This function will
be executed whenever the user executes the action.

Example form definition:

```lang=cpp
class TestFormDelegate : public FormDelegate {
public:
  TestFormDelegate() {
    m_text_field = AddTextField("Text", "The big brown fox.");
    m_file_field = AddFileField("File", "/tmp/a");
    m_directory_field = AddDirectoryField("Directory", "/tmp/");
    m_integer_field = AddIntegerField("Number", 5);
    std::vector<std::string> choices;
    choices.push_back(std::string("Choice 1"));
    choices.push_back(std::string("Choice 2"));
    choices.push_back(std::string("Choice 3"));
    choices.push_back(std::string("Choice 4"));
    choices.push_back(std::string("Choice 5"));
    m_choices_field = AddChoicesField("Choices", 3, choices);
    m_bool_field = AddBooleanField("Boolean", true);
    TextFieldDelegate default_field =
        TextFieldDelegate("Text", "The big brown fox.");
    m_text_list_field = AddListField("Text List", default_field);

    AddAction("Submit", [this](Window &window) { Submit(window); });
  }

  void Submit(Window &window) { SetError("An example error."); }

protected:
  TextFieldDelegate *m_text_field;
  FileFieldDelegate *m_file_field;
  DirectoryFieldDelegate *m_directory_field;
  IntegerFieldDelegate *m_integer_field;
  BooleanFieldDelegate *m_bool_field;
  ChoicesFieldDelegate *m_choices_field;
  ListFieldDelegate<TextFieldDelegate> *m_text_list_field;
};
```

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D104395

[Flang][Docs] Update meeting URL

[lld/mac] Tweak reserve() argument in unwind code

addEntriesForFunctionsWithoutUnwindInfo() can add entries to cuVector, so
cuCount can be stale. Use cuVector.size() instead.

No behavior change.

[X86][Atom] Fix vector fp<->int resource/throughputs

Match whats documented in the Intel AOM - almost all the conversion instructions requires BOTH ports (apart from the MMX cvtpi2ps/cvtpi2ps instructions which we already override) - this was being incorrectly modelled as EITHER port.

Now that we can use in-order models in llvm-mca, the atom model is a good "worst case scenario" analysis for x86.

Fix broken libc test

[NFC][lldb-vscode] Fix launch test

Using br for creating breakpoints fails if there are other commands that
start with br.

[lld/mac] Don't crash when dead-stripping removes all unwind info

If the input has compact unwind info but all of it is removed
after dead stripping, we would crash. Now we don't write any
__unwind_info section at all, like ld64.

This is a bit awkward to implement because we only know the final
state of unwind info after UnwindInfoSectionImpl<Ptr>::finalize(),
which is called after sections are added. So add a small amount of
bookkeeping to relocateCompactUnwind() instead (which runs earlier)
so that we can predict what finalize() will do before it runs.

Fixes PR51010.

Differential Revision: https://reviews.llvm.org/D105557

[lld-macho][nfc] Rename test file to be more descriptive (rather than referencing the bug number)

Differential Revision: https://reviews.llvm.org/D105559

[ScalarEvolution] Make sure getMinusSCEV doesn't negate pointers.

Add a function removePointerBase that returns, essentially, S -
getPointerBase(S).  Use it in getMinusSCEV instead of actually
subtracting pointers.

Differential Revision: https://reviews.llvm.org/D105503

[libTooling] Add support for implicit `this` to `buildAddressOf`.

Changes `buildAddressOf` to return `this` when given an implicit `this` expression.

Differential Revision: https://reviews.llvm.org/D105551

[lldb][docs] Force documentation emission of special Python class members

The current LLDB Python docs are missing documentation for all the special
members such as conversion functions (`__int__`) and other special functions
(`__len__`).

The reason for that is that the `automodapi` plugin we're using to generate the
*.rst files simply doesn't emit them. There doesn't seem to be any config option
to enable those in `automodapi` and it's not even clear why they are filtered. I
assume the leading underscore in their names makes them look like private
methods.

This patch just forcibly adds a few selected special members functions to the
list of functions that sphinx should always document.  This will cause sphinx to
warn if a class doesn't have one of those functions but it's better than not
having them documented.

The main motivation here is that since `SBAddress.__int__` is one of the few
functions that is only available in the embedded Python REPL which would be good
to have in the public documentation.

Fixes rdar://64647665

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D105480

[lldb/lua] Add scripted watchpoints for Lua

Add support for Lua scripted watchpoints, with basic tests.

Differential Revision: https://reviews.llvm.org/D105034

Fix a failing assertion with -Wcast-align

When there is unknown type in a struct in code compiled with
-Wcast-align, the compiler crashes due to
clang::ASTContext::getASTRecordLayout() failing an assert.

Added check that the RecordDecl is valid before calling
getASTRecordLayout().

[mlir][vector] Refactor Vector Unrolling and remove Tuple ops

Simplify vector unrolling pattern to be more aligned with rest of the
patterns and be closer to vector distribution.
The new implementation uses ExtractStridedSlice/InsertStridedSlice
instead of the Tuple ops. After this change the ops based on Tuple don't
have any more used so they can be removed.

This allows removing signifcant amount of dead code and will allow
extending the unrolling code going forward.

Differential Revision: https://reviews.llvm.org/D105381

[dfsan][NFC] Add Origin Tracking into doc

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D105378

[mlir] Allow conversion to LLVM for ElementsAttr's with size 0

The code seems to correctly handle the case that this assertion was
guarding.

Differential Revision: https://reviews.llvm.org/D105379

[SLP] rename variable to not be misleading; NFC

The reduction matching was probably only dealing with binops
when it was written, but we have now generalized it to handle
select and intrinsics too, so assert on that too.

[SCEVExpander] Support opaque pointers

This adds support for opaque pointers to expandAddToGEP() by always
generating an i8 GEP for opaque pointers. After looking at some other
cases (constexpr GEP folding, SROA GEP generation), I've come around
to the idea that we should use i8 GEPs for opaque pointers, because
the alternative would be to guess a GEP type from surrounding code,
which will not be reliable. Ultimately, i8 GEPs is where we want to
end up anyway, and opaque pointers just make that the natural choice.

There are a couple of other places in SCEVExpander that check pointer
element types, I plan to update those when I run across usable test
coverage that doesn't assert elsewhere.

Differential Revision: https://reviews.llvm.org/D105398

[PowerPC] Disable permuted SCALAR_TO_VECTOR on LE without direct moves

There are some patterns involving the permuted scalar to vector node
for which we don't have patterns without direct moves on little endian
subtargets. This causes selection errors. While we can of course add
the missing patterns, any additional effort to make this work is not
useful since there is no support for any CPU that can run in
little endian mode and does not support direct moves.

[COFF] [CodeView] Add a few new enum values

These are undocumented, but are visible in the SDK headers since some
versions ago.

Differential Revision: https://reviews.llvm.org/D105513

[LLD] [COFF] Avoid thread exhaustion on 32-bit Windows host

LLD on 32-bit Windows would frequently fail on large projects with
an exception "thread constructor failed: Exec format error".  The stack
trace pointed to this usage of std::async, and looking at the
implementation in libc++ it seems using std::async with
std::launch::async results in the immediate creation of a new thread
for every call.  This could result in a potentially unbounded number
of threads, depending on the number of input files.  This seems to
be hitting some limit in 32-bit Windows host.

I took the easy route, and only use threads on 64-bit Windows, not all
Windows as before.  I was thinking a more proper solution might
involve using a thread pool rather than blindly spawning any number
of new threads, but that may have other unforeseen consequences.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D105506

[CodeView] Add missing cases for new enum values

This fixes warnings while building llvm-pdbutil after
d20b013b490e0603ba21b5ccff966d7e11025775.

[MLIR] Provide lowering of std switch to llvm switch

This patch allows lowering of std switch to llvm switch

Differential Revision: https://reviews.llvm.org/D105580

[SCF] Handle lowering of Execute region to Standard CFG

Lower SCF.executeregionop to llvm by essentially inlining the region and replacing the return

Differential Revision: https://reviews.llvm.org/D105567

[AArch64] Simplify sve-breakdown-scalable-vectortype.ll.

Fix the calling convention so we don't spill every SVE register.

GlobalISel/AArch64: don't optimize away redundant branches at -O0

This patch prevents GlobalISel from optimizing out redundant branch
instructions when compiling without optimizations.

The motivating example is code like the following common pattern in
Swift, where users expect to be able to set a breakpoint on the early
exit:

public func f(b: Bool) {
  guard b else {
    return // I would like to set a breakpoint here.
  }
  ...
}

The patch modifies two places in GlobalISEL: The first one is in
IRTranslator.cpp where the removal of redundant branches is made
conditional on the optimization level. The second one is in
AArch64InstructionSelector.cpp where an -O0 *only* optimization is
being removed.

Disabling these optimizations increases code size at -O0 by
~8%. However, doing so improves debuggability, and debug builds are
the primary reason why developers compile without optimizations. We
thus concluded that this is the right trade-off.

rdar://79515454

Differential Revision: https://reviews.llvm.org/D105238

[IR] Make some pointer element type accesses explicit (NFC)

Explicitly fetch the pointer element type in various deprecated
methods, so we can hopefully remove support from this from the
base GEP constructor.

[llvm-nm] Switch command line parsing from llvm::cl to OptTable

Part of https://lists.llvm.org/pipermail/llvm-dev/2021-July/151622.html
"Binary utilities: switch command line parsing from llvm::cl to OptTable"

Users should generally observe no difference as long as they only use intended
option forms. Behavior changes:

* `-t=d` is removed. Use `-t d` instead.
* `--demangle=0` cannot be used. Omit the option or use `--no-demangle` instead.
* `--help-list` is removed. This is a `cl::` specific option.

Note:

* `-t` diagnostic gets improved.
* This patch avoids cl::opt collision if we decide to support multiplexing for binary utilities
* One-dash long options are still supported.
* The `-s` collision (`-s segment section` for Mach-O) is unfortunate. `-s` means `--print-armap` in GNU nm.
* This patch removes the last `cl::multi_val` use case from the `llvm/lib/Support/CommandLine.cpp` library

`-M` (`--print-armap`), `-U` (`--defined-only`), and `-W` (`--no-weak`)
are now deprecated. They could conflict with future GNU nm options.
(--print-armap has an existing alias -s, so GNU will unlikely add a new one.
--no-weak (not in GNU nm) is rarely used anyway.)

`--just-symbol-name` is now deprecated in favor of
`--format=just-symbols` and `-j`.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D105330

[IR] Simplify Attribute::getAsString() (NFC)

Avoid enumerating all attributes here and instead use
getNameFromAttrKind(), which is based on the tablegen data.

This only leaves us with custom handling for int attributes,
which don't have uniform printing.

[AsmWriter] Simplify type attribute printing (NFC)

Avoid enumerating all supported type attributes, instead fetch
their name from the attribute kind.

[ARM] Add some opaque pointer gather/scatter tests. NFC

They seem to work OK. Some other test cleanups at the same time.

[MCA] [AMDGPU] Adding an implementation to AMDGPUCustomBehaviour for handling s_waitcnt instructions.

This commit also makes some slight changes to the scheduling model for AMDGPU to set the RetireOOO flag for all scheduling classes.

This flag is only used by llvm-mca and allows instructions to retire out of order.

See the differential link below for a deeper explanation of everything.

Differential Revision: https://reviews.llvm.org/D104730

utils: add a revert checker

Chrome OS and Android have found it useful to have an automated revert
checker. It was requested to upstream it, since other folks in the LLVM
community may also find value in it.

The tests depend on having a full (non-shallow) checkout of LLVM. This
seems reasonable to me, since:

- the tests should only be run if the user is developing on this script
- it's kind of hard to develop on this script without local git history
  :)

If people really want, the tests' dependency on LLVM's history can be
removed. It's mostly just effort/complexity that doesn't seem necessary.

Differential Revision: https://reviews.llvm.org/D105578

[OpaquePtr] Remove checking pointee type for byval/preallocated type

These currently always require a type parameter. The bitcode reader
already upgrades old bitcode without the type parameter to use the
pointee type.

In cases where the caller does not have byval but the callee does, we
need to follow CallBase::paramHasAttr() and also look at the callee for
the byval type so that CallBase::isByValArgument() and
CallBase::getParamByValType() are in sync. Do the same for preallocated.

While we're here add a corresponding version for inalloca since we'll
need it soon.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D104663

[PowerPC] Add P7 RUN line for load and splat test

[OpaquePtr] Use ArgListEntry::IndirectType for lowering ABI attributes

Consolidate PreallocatedType and ByValType into IndirectType, and use that for inalloca.

[llvm-nm][test] Fix just-symbols.test

[compiler-rt][hwasan] Setup hwasan thread handling on Fuchsia

This patch splits up hwasan thread creation between `__sanitizer_before_thread_create_hook`,
`__sanitizer_thread_create_hook`, and `__sanitizer_thread_start_hook`.
The linux implementation creates the hwasan thread object inside the
new thread. On Fuchsia, we know the stack bounds before thread creation,
so we can initialize part of the thread object in `__sanitizer_before_thread_create_hook`,
then initialize the stack ring buffer in `__sanitizer_thread_start_hook`
once we enter the thread.

Differential Revision: https://reviews.llvm.org/D104085

[clang] disable P2266 simpler implicit moves under -fms-compatibility

The Microsoft STL currently has some issues with P2266.
We disable it for now in that mode, but we might come back later with a
more targetted approach.

Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D105518

[compiler-rt][Fuchsia] Disable interceptors while enabling new/delete replacements

This disables use of hwasan interceptors which we do not use on Fuchsia. This
explicitly sets the macro for defining the hwasan versions of new/delete.

Differential Revision: https://reviews.llvm.org/D103544

[AMDGPU] Disable garbage collection passes

Differential Revision: https://reviews.llvm.org/D105593

[gn build] (semi-manually) port 966386514bec

[Bazel] Fixes for b5d847b1b95750d0af40cfc8c71a8fec50bb8613 and 6412a13539ab2914eed8e1df83c399b9a16e3408

[gn build] (manually) port ef16c8eaa5cd5679759 (MCACustomBehaviorAMDGPU)

[AIX] Don't pass no-integrated-as by default

D105314 added the abibility choose to use AsmParser for parsing inline
asm. -no-intergrated-as will override this default if specified
explicitly.

If toolchain choose to use MCAsmParser for inline asm, don't pass
the option to disable integrated-as explictly unless set by user.

Reviewed By: #powerpc, shchenz

Differential Revision: https://reviews.llvm.org/D105512

[PowerPC] Fix i64 to vector lowering on big endian

Lowering for scalar to vector would skip if current subtarget is big
endian and the scalar is larger or equal than 64 bits. However there's
some issue in implementation that SToVRHS may refer to SToVLHS's scalar
size if SToVLHS is present, which leads to some crash.o

Reviewed By: nemanjai, shchenz

Differential Revision: https://reviews.llvm.org/D105094

Revert "[MCA] [AMDGPU] Adding an implementation to AMDGPUCustomBehaviour for handling s_waitcnt instructions."

Build failures when building with shared libraries. Reverting until I can fix.

Differential Revision: https://reviews.llvm.org/D104730

[ORC] Fix file comments.

[ORC] Replace MachOJITDylibInitializers::SectionExtent with ExecutorAddressRange

MachOJITDylibInitializers::SectionExtent represented the address range of a
section as an (address, size) pair. The new ExecutorAddressRange type
generalizes this to an address range (for any object, not necessarily a section)
represented as a (start-address, end-address) pair.

The aim is to express more of ORC (and the ORC runtime) in terms of simple types
that can be serialized/deserialized via SPS. This will simplify SPS-based RPC
involving arguments/return-values of these types.