Commit
6611fbc62af59a1d28a9f310d2e95267911d4385
by Jon Roelofs[AArch64] Dump a little more info about unimplemented reg-to-reg copies. NFC
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 | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp |
Commit
f2832c2295c6076b51a35d0d7b304c08e1b41c29
by rob.suderman[mlir][tosa] Added shape propagation for TOSA pool operations.
Pool operations perform the same shape propagation. Included the shape propagation and tests for these avg_pool2d and max_pool2d.
Differential Revision: https://reviews.llvm.org/D105665
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 | mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td |
 | mlir/lib/Dialect/Tosa/IR/TosaOps.cpp |
 | mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir |
Commit
51fc742ce716a09359f4f87ffe3876cb7ff9479d
by i[Driver] Let -fno-integrated-as -gdwarf-5 use -fdwarf-directory-asm
While GNU as only allows the directory form of the .file directive for DWARF v5, the integrated assembler prefers the directory form on all DWARF versions (-fdwarf-directory-asm).
We currently set CC1 -fno-dwarf-directory-asm for -fno-integrated-as -gdwarf-5 which may cause the directory entry 0 and the filename entry 0 to be incorrect (see D105662 and the example below). This patch makes -fno-integrated-as -gdwarf-5 use -fdwarf-directory-asm as well.
``` cd /tmp/c
before % clang -g -gdwarf-5 -fno-integrated-as e/a.c -S -o - | grep '\.file.*0' .file 0 "/tmp/c/e/a.c" md5 0x97e31cee64b4e58a4af8787512d735b6 % clang -g -gdwarf-5 -fno-integrated-as e/a.c -c % llvm-dwarfdump a.o | grep include_directories include_directories[ 0] = "/tmp/c/e"
after % clang -g -gdwarf-5 -fno-integrated-as e/a.c -S -o - | grep '\.file.*0' .file 0 "/tmp/c" "e/a.c" md5 0x97e31cee64b4e58a4af8787512d735b6 % clang -g -gdwarf-5 -fno-integrated-as e/a.c -c % llvm-dwarfdump a.o | grep include_directories include_directories[ 0] = "/tmp/c" ```
Reviewed By: #debug-info, dblaikie, osandov
Differential Revision: https://reviews.llvm.org/D105835
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 | clang/test/Driver/debug-options.c |
 | clang/lib/Driver/ToolChains/Clang.cpp |
Commit
98033fdc50e61273b1d5c77ba5f0f75afe3965c1
by 31459023+hctimsanitizer_common: Fix build for tests
It turns out that COMPILER_RT_TEST_COMPILER_CFLAGS is actually a string that is being appended to and not a list.
Therefore, append the thread-safety flags to the string. Because CMake separates list elements by ';' when turning into a string, also substitute ';' with ' '.
Reviewed By: hctim
Differential Revision: https://reviews.llvm.org/D105829
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 | compiler-rt/CMakeLists.txt |
Commit
189c55251849076e17ddab590c1302f4af0e60f8
by leonardchan[compiler-rt][hwasan] Refactor kAliasRegionStart usage
This moves logic for setting kAliasRegionStart into hwasan_allocator.cpp so other platforms that do not support aliasing mode will not need to define kAliasRegionStart.
Differential Revision: https://reviews.llvm.org/D105725
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 | compiler-rt/lib/hwasan/hwasan_mapping.h |
 | compiler-rt/lib/hwasan/hwasan_allocator.cpp |
 | compiler-rt/lib/hwasan/hwasan_linux.cpp |
Commit
50529affcdc8335f0d71c129f61b717f6f1c782b
by hanchung[mlir][Linalg] Add 3D pooling named ops to Linalg.
Reviewed By: gysit, hanchung
Differential Revision: https://reviews.llvm.org/D105329
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 | mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py |
 | mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml |
 | mlir/test/Dialect/Linalg/named-ops.mlir |
Commit
fada2782cf6f9eab40e1e028b0eca9d85f8800b3
by i[llc] Default MCUseDwarfDirectory to true
For Clang, `MCUseDwarfDirectory` is true by default for the majority cases (-fintegrated-as or -gdwarf-5; most targets use -fintegrated-as by default). Defaulting MCUseDwarfDirectory to true can reduce the differences between clang and llc.
Reviewed By: #debug-info, dblaikie
Differential Revision: https://reviews.llvm.org/D105856
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 | llvm/test/DebugInfo/Generic/lto-comp-dir.ll |
 | llvm/test/DebugInfo/X86/dbg-file-name.ll |
 | llvm/test/DebugInfo/NVPTX/debug-loc-offset.ll |
 | llvm/test/DebugInfo/X86/inline-asm-locs.ll |
 | llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll |
 | llvm/tools/llc/llc.cpp |
 | llvm/test/CodeGen/Generic/dwarf-md5.ll |
 | llvm/test/CodeGen/Generic/dwarf-source.ll |
Commit
45b3cfe8437f78faac2c84b796bb246e16382252
by ajcbik[mlir][sparse] add support for AND and OR operations
Integral AND and OR follow the simple conjunction and disjuction rules for lattice building. This revision also completes some of the Merge refactoring by moving the remainder parts that are merger specific from sparsification into utils files.
Reviewed By: gussmith23
Differential Revision: https://reviews.llvm.org/D105851
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 | mlir/lib/Dialect/SparseTensor/Utils/Merger.cpp |
 | mlir/test/Dialect/SparseTensor/sparse_int_ops.mlir |
 | mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp |
 | mlir/include/mlir/Dialect/SparseTensor/Utils/Merger.h |
Commit
ea91749f0149b77226e2b5ce0329e0ad9513bb4d
by dblaikieDebugInfo: Use debug_rnglists.dwo for ranges in debug_info.dwo when parsing DWARFv5
This call would incorrectly overwrite (with the .debug_rnglists.dwo from the executable, if there was one) the rnglists section instead of the correct value (from the .debug_rnglists.dwo in the .dwo file) that's applied in DWARFUnit::tryExtractDIEsIfNeeded
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 | llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp |
 | llvm/test/tools/llvm-dwarfdump/X86/stats-v5-ranges-dwo.s |
Commit
ac8cedead8859b2e86155e8cc1f0c3cfd822049c
by dblaikieFix test - mistaken hardcoded path from my local machine.
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 | llvm/test/tools/llvm-dwarfdump/X86/stats-v5-ranges-dwo.s |
Commit
0e6424acbdf03c787de7ec0b969d80da97e56c43
by aeubanks[OpaquePointers][ThreadSanitizer] Cleanup calls to PointerType::getElementType()
Reviewed By: #opaque-pointers, dblaikie
Differential Revision: https://reviews.llvm.org/D105710
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 | llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp |
Commit
7987c46273c88a0370f5bfee2e3294a8a4c0f22a
by aeubanks[OpaquePtr][ISel] Use ArgListEntry::IndirectType more
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 | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp |
 | llvm/lib/CodeGen/SelectionDAG/FastISel.cpp |
Commit
cad9b7f708e2b2d19d7890494980c5e427d6d4ea
by rithiksh02[analyzer] Print time taken to analyze each function Summary: This patch is a part of an attempt to obtain more timer data from the analyzer. In this patch, we try to use LLVM::TimeRecord to save time before starting the analysis and to print the time that a specific function takes while getting analyzed.
The timer data is printed along with the -analyzer-display-progress outputs.
ANALYZE (Syntax): test.c functionName : 0.4 ms ANALYZE (Path, Inline_Regular): test.c functionName : 2.6 ms Authored By: RithikSharma Reviewer: NoQ, xazax.hun, teemperor, vsavchenko Reviewed By: NoQ Differential Revision: https://reviews.llvm.org/D105565
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 | clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp |
 | clang/test/Analysis/analyzer-display-progress.cpp |
Commit
b8424b42a58ee4cf8ca423de39993ed97f98f0bc
by Vitaly BukaRevert "[hwasan] More realistic setjmp test."
Breaks https://lab.llvm.org/buildbot/#/builders/sanitizer-x86_64-linux-qemu
This reverts commit 5511bfdb671505c1e7968ab8ef6032414bba3852.
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 | compiler-rt/test/hwasan/TestCases/longjmp.c |
Commit
47d0780f454d3f7c42bdba13c0682bf2a0095bca
by Jessica Paquette[GlobalISel] Handle more types in narrowScalar for eq/ne G_ICMP
Generalize the existing eq/ne case using `extractParts`. The original code only handled narrowings for types of width 2n->n. This generalization allows for any type that can be broken down by `extractParts`.
General overview is:
- Loop over each narrow-sized part and do exactly what the 2-register case did. - Loop over the leftover-sized parts and do the same thing - Widen the leftover-sized XOR results to the desired narrow size - OR that all together and then do the comparison against 0 (just like the old code)
This shows up a lot when building clang for AArch64 using GlobalISel, so it's worth fixing. For the sake of simplicity, this doesn't handle the non-eq/ne case yet.
Also remove the code in this case that notifies the observer; we're just going to delete MI anyway so talking to the observer shouldn't be necessary.
Differential Revision: https://reviews.llvm.org/D105161
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 | llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir |
 | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp |
Commit
606551ee983a70623d397b908d264450aebe099a
by Vitaly BukaRevert "[X86][SSE] X86ISD::FSETCC nodes (cmpss/cmpsd) return a 0/-1 allbits signbits result"
Fails here https://lab.llvm.org/buildbot/#/builders/37/builds/5267
This reverts commit e4aa6ad132164839a4a97dff0d433ea4766f77f1.
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 | llvm/lib/Target/X86/X86ISelLowering.cpp |
 | llvm/test/CodeGen/X86/known-signbits-vector.ll |
Commit
c41e67f3f11b65f77d288c8aa5324a8b71debfb3
by Vitaly Buka[NFC][scudo] Clang format a file
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 | compiler-rt/lib/scudo/scudo_tsd_exclusive.inc |
Commit
20176bc7dd3f431db4c3d59b51a9f53d52190c82
by zeratul976[clang] Refactor AST printing tests to share more infrastructure
Differential Revision: https://reviews.llvm.org/D105457
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 | clang/unittests/AST/ASTPrint.h |
 | clang/unittests/AST/NamedDeclPrinterTest.cpp |
 | clang/unittests/AST/StmtPrinterTest.cpp |
 | clang/unittests/AST/DeclPrinterTest.cpp |
Commit
8a29977429e35d8024fa319a29fb518f15e753af
by czhengsz[PowerPC][NFC] add test case for preparing more loads/stores
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 | llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll |
Commit
d7d9c577ed33ab6b82eceb01bc978f2460f038f4
by gusrb406[NFC] Edit the comment in M68kInstrInfo::ExpandMOVSZX_RM
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 | llvm/lib/Target/M68k/M68kInstrInfo.cpp |
Commit
ca78151001d80d0fd1a2a6db4742f5f673572f7c
by david.green[ARM] Introduce MVEEXT ISel lowering
Similar to D91921 (and D104515) this introduces two MVESEXT and MVEZEXT nodes that larger-than-legal sext and zext are lowered to. These either get optimized away or end up becoming a series of stack loads/store, in order to perform the extending whilst keeping the order of the lanes correct. They are generated from v8i16->v8i32, v16i8->v16i16 and v16i8->v16i32 extends, potentially with a intermediate extend for the larger v16i8->v16i32 extend. A number of combines have been added for obvious cases that come up in tests, notably MVEEXT of shuffles. More may be needed in the future, but this seems to cover most of the cases that come up in the tests.
Differential Revision: https://reviews.llvm.org/D105090
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 | llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll |
 | llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll |
 | llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll |
 | llvm/test/CodeGen/Thumb2/mve-widen-narrow.ll |
 | llvm/test/CodeGen/Thumb2/mve-sext.ll |
 | llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll |
 | llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll |
 | llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll |
 | llvm/lib/Target/ARM/ARMISelLowering.cpp |
 | llvm/lib/Target/ARM/ARMISelLowering.h |
 | llvm/test/CodeGen/Thumb2/mve-shuffleext.ll |
 | llvm/test/CodeGen/Thumb2/mve-gather-increment.ll |
Commit
816f12886bd0781a85d4736d9adc9b0ff7b4775c
by david.green[MIPS] Regenerate test after D105161. NFC
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 | llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir |
Commit
e338d08ae609bf07b1f43ad15a6488e7c302800b
by gusrb406[SimplifyCFG] Fix SimplifyBranchOnICmpChain to be undef/poison safe.
This patch fixes the problem of SimplifyBranchOnICmpChain that occurs when extra values are Undef or poison.
Suppose the %mode is 51 and the %Cond is poison, and let's look at the case below. ``` %A = icmp ne i32 %mode, 0 %B = icmp ne i32 %mode, 51 %C = select i1 %A, i1 %B, i1 false %D = select i1 %C, i1 %Cond, i1 false br i1 %D, label %T, label %F => br i1 %Cond, label %switch.early.test, label %F switch.early.test: switch i32 %mode, label %T [ i32 51, label %F i32 0, label %F ] ``` incorrectness: https://alive2.llvm.org/ce/z/BWScX
Code before transformation will not raise UB because %C and %D is false, and it will not use %Cond. But after transformation, %Cond is being used immediately, and it will raise UB.
This problem can be solved by adding freeze instruction.
correctness: https://alive2.llvm.org/ce/z/x9x4oY
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D104569
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 | llvm/test/Transforms/SimplifyCFG/switch_msan.ll |
 | llvm/test/Transforms/SimplifyCFG/switch_create.ll |
 | llvm/lib/Transforms/Utils/SimplifyCFG.cpp |
 | llvm/test/Transforms/SimplifyCFG/switch_create-custom-dl.ll |
Commit
6fd9c1901f40c1e9beceff67e05570afe2914e65
by qiucofan[PowerPC] Fix typo in vector shuffle combining
a22ecb4 fixed a crash on big endian subtargets. This commit fixes a typo in that commit which may cause miscompile.
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 | llvm/lib/Target/PowerPC/PPCISelLowering.cpp |
Commit
d46d534dbbba484fb17f0f4e1a56c357aad4458f
by Stanislav.Mekhanoshin[AMDGPU] Make some VOP1 instructions rematerializable
This is a pilot change to verify the logic. The rest will be done in a same way, at least the rest of VOP1.
Differential Revision: https://reviews.llvm.org/D105742
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 | llvm/lib/Target/AMDGPU/VOP1Instructions.td |
 | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp |
 | llvm/test/CodeGen/AMDGPU/remat-vop.mir |
Commit
954a15d6398edbb839d4b842534b50e85d4aa8cd
by qiucofan[SelectionDAG] Check use before combining into USUBSAT
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D105789
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 | llvm/test/CodeGen/PowerPC/sat-add.ll |
 | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp |