Changes

Summary

  1. [RegisterCoalescer] Resolve conflict based on liveness of subregister (details)
  2. [NFC][AMDGPU] autogenerate kill-infinite-loop.ll checks (details)
  3. [AMDGPU] Don't handle export done when unify exit nodes (details)
  4. [clangd] Add CMake option to (not) link in clang-tidy checks (details)
  5. [AArch64][SME] Add matrix register definitions and parsing support (details)
  6. [AMDGPU] Precommit flat-scratch-init.ll test (details)
  7. [AMDGPU] Init scratch only if necessary (details)
  8. [RISCV] Fix the neutral element in vector 'fadd' reductions (details)
  9. [mlir][SCF] populateSCFStructuralTypeConversionsAndLegality WhileOp support (details)
  10. [InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183) (details)
  11. [DebugInfo] Correctly update dbg.values with duplicated location ops (details)
  12. [NFC][PowerPC] Added test to check regsiter allocation for ACC registers (details)
  13. [gn build] (manually) merge 462d4de35b0c (details)
  14. Revert rGb803294cf78714303db2d3647291a2308347ef23 : "[InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183)" (details)
  15. [gn build] Port c08dabb0f476 (details)
  16. [X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction. (details)
  17. [lldb][docs] Remove mention of subversion. NFC. (details)
  18. [NFC] [Coroutines] Remove unused CoroFree (details)
  19. [InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183) (REAPPLIED) (details)
  20. [RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs (details)
  21. [lld][MachO] Code cleanup (details)
  22. [Analyzer][solver] Add dump methods for (dis)equality classes. (details)
  23. [SLP] match logical and/or as reduction candidates (details)
  24. ARM: reuse existing libcall global variable if possible. (details)
  25. [docs] Update CMake cross compiling guide link (details)
  26. [mlir][linalg] Fix typo in ExtractSliceOfPadTensorSwapPattern (details)
  27. [AIX] Enable dollar sign as PC in inlineasm (details)
  28. [flang][OpenMP] Fix semantic check of test case in taskloop simd construct (details)
  29. [Lexer] Fix bug in `makeFileCharRange` called on split tokens. (details)
  30. [runtimes] NFCI: Drop intermediate CMake variable TARGET_TRIPLE (details)
  31. [SLP]Workaround for InsertSubVector cost. (details)
  32. [AMDGPU] Check llc-pipeline.ll with -match-full-lines -strict-whitespace (details)
  33. Combine two diagnostics into one and correct grammar (details)
  34. [CostModel][AArch64] Make loads/stores of <vscale x 1 x eltty> invalid. (details)
  35. GlobalISel: Handle lowering non-power-of-2 extloads (details)
  36. [LV] Print remark when loop cannot be vectorized due to invalid costs. (details)
  37. [InstCombine] add tests for icmp with constant offset and no-wrap flags; NFC (details)
  38. [InstCombine] reorder icmp with offset folds for better results (details)
  39. [ARM] Lower v16i8 -> i64 VMLA reductions. (details)
  40. [ELF] --fortran-common: prefer STB_WEAK to COMMON (details)
  41. [WebAssembly] Remove datalayout strings from llc tests (details)
  42. [runtimes] Inherit the TARGET_TRIPLE that may be set by LLVM (details)
  43. [WebAssembly] Codegen for v128.loadX_lane instructions (details)
  44. [SelectionDAG] Add an overload of getStepVector that assumes step 1. (details)
  45. Demangle: correct swift_async demangling for Microsoft scheme (details)
  46. [Verifier] Improve incompatible attribute type check (details)
  47. Remove uses of deprecated target AllPassesAndDialectsNoRegistration in Bazel (NFC) (details)
  48. [scudo] Don't enabled MTE for small alignment (details)
  49. [ARM] Move add(VMLALVA(A, X, Y), B) to VMLALVA(add(A, B), X, Y) (details)
  50. [NFC][PhaseOrdering] Add test for the lack of CSE after SimplifyCFG (PR51092) (details)
  51. [Attributes] Use single method to fetch type from AttributeSet (NFC) (details)
  52. [NFC] Drop redundant check prefixes in newly added test file (details)
  53. [runtimes] Bring back TARGET_TRIPLE (details)
  54. [Bazel] Uniformly export all MLIR td files (details)
  55. [SLP] Fix case of variable name. NFCI. (details)
  56. [docs] Fix :option:`--file-header` reference in llvm-readelf.rst after D105532 (details)
  57. [SLP][NFC]Fix variables names, NFC. (details)
  58. [AMDGPU] Add TII::isIgnorableUse() to allow VOP rematerialization (details)
  59. [tests] Stablize tests for possible change in deref semantics (details)
  60. [libcxx] [test] Remove a LIBCXX-WINDOWS-FIXME in trivial_abi/unique_ptr_ret (details)
  61. Global variables with strong definitions cannot be freed (details)
  62. [mlir] NFC - Add AffineMap::replace variant with dim/symbol inference (details)
  63. [Support] Get correct number of physical cores on Apple Silicon (details)
  64. [lldb] Always call DestroyImpl from Process::Finalize (details)
  65. [lldb] Make TargetList iterable (NFC) (details)
  66. [asan][clang] Add flag to outline instrumentation (details)
  67. [tests] Stablize tests for possible change in deref semantics (details)
  68. [mlir][affine] Add single result affine.min/max -> affine.apply canonicalization. (details)
  69. [AArch64] Fix selection of G_UNMERGE <2 x s16> (details)
  70. [SimpleLoopUnswitch] Don't non-trivially unswitch loops with catchswitch exits (details)
  71. Precommit test for D106017 (details)
  72. [llvm-strip][WebAssembly] Support strip flags (details)
  73. [Polly] Fix misleading debug message. NFC. (details)
  74. [ARM] Fix RELA relocations for 32bit ARM. (details)
  75. [docs][OpaquePtr] Remove finished task (details)
  76. [clang-format] Make BreakAfterReturnType work with K&R C functions (details)
  77. [libomptarget] Keep the Shadow Pointer Map up-to-date (details)
  78. [Support] Turn on SupportTest for Apple Silicon (details)
  79. [GlobalOpt] Fix a miscompile when evaluating struct initializers. (details)
  80. [WebAssembly] Codegen for v128.storeX_lane instructions (details)
  81. [clang] Refactor AST printing tests to share more infrastructure (details)
  82. [libc++] NFCI: Restore code duplication in wrap_iter, with test. (details)
  83. [AMDGPU] Use update_test_checks.py script for annotate kernel features tests. (details)
  84. libclc: Add -cl-no-stdinc to clang flags on clang >=13 (details)
  85. [OpenCL][NFC] opencl-c.h: reorder atomic operations (details)
  86. [OpenCL] opencl-c.h: CL3.0 generic address space (details)
  87. [PowerPC] Generate inlined quadword lock free atomic operations via AtomicExpand (details)
  88. [gn build] Port b9c3941cd61d (details)
  89. [mlir][linalg][NFC] Factor out tile generation in makeTiledShapes (details)
  90. [mlir][linalg] Add optional output operand to PadTensorOp (details)
  91. [mlir][NFC] Move asOpFoldResult helper functions to StaticValueUtils (details)
  92. [mlir][linalg] Tile PadTensorOp (details)
  93. [mlir][linalg] Fix Windows build (details)
  94. [mlir][linalg] Improve codegen of ExtractSliceOfPadTensorSwapPattern (details)
  95. [mlir][linalg] Improve codegen when tiling PadTensor evenly (details)
  96. [PowerPC][NFC] add testcase for update-form preparation with non-const increment (details)
  97. Defend early against operation created without a registered dialect (details)
  98. [Attributor] AACallEdges, Add a way to ask nonasm unknown callees (details)
  99. Revert "Defend early against operation created without a registered dialect" (details)
  100. [MLIR] [Python] Add `owner` to PyValue and fix its parent reference (details)
  101. Defend early against operation created without a registered dialect (details)
Commit 40e3df2a1b229096b899443abf0d95784d7a4bea by ruiling.song
[RegisterCoalescer] Resolve conflict based on liveness of subregister

Currently we are resolving lane/subregister conflict by visiting
instructions sequentially in current block to see whether there is any
use of the tainted lanes. To save compile time, we are not doing further
check in successor blocks. This sounds reasonable without subgregister liveness.

But since we have added subregister liveness tracking capability to
register coalescer, we can easily determine whether we have subregister
liveness conflict by checking subranges. This would help coalescing more
COPYs for target that enables subregister liveness tracking.

Reviewed by: arsenm, qcolombet

Differential Revision: https://reviews.llvm.org/D104509
The file was modifiedllvm/lib/CodeGen/RegisterCoalescer.cpp
The file was addedllvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
Commit 1d9585c8c1ce5c6b9d2e16ba476294b0ee8d9edb by ruiling.song
[NFC][AMDGPU] autogenerate kill-infinite-loop.ll checks

This would help us to track the assembly changes to these tests.

Reviewed by: foad

Differential Revision: https://reviews.llvm.org/D105609
The file was modifiedllvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
Commit d9b9fdd91bb49292cf7c01bb72ece7e9d9f2e9ac by ruiling.song
[AMDGPU] Don't handle export done when unify exit nodes

This patch aims to revert the changes introduced by D70781 D71192 D76364

D70781 was introduced to fix hardware hang where we do not insert exp-
null-done for a kill inside infinit loop. At that time we have not added
exp-null-done for kill early termination, but I believe as for now, we will
always add the exp-null-done for early termination case in LaterBranchLowering.

D71192 was introduced to handle the only_kill case, which is also been
handled by the kill early termination work.

D76364 was used to fix a regression by D71192, where we cleared the done
bit of the export in the existing program and not let the normal return
block branching to the new unified return block.

With this change, we just trust frontends have setup exp-done correctly
which is true for all existing frontends. The backend only inserts
exp-null-done for the kill cases which is handled in SILateBranchLowering.cpp.

Reviewed by: critson

Differential Revision: https://reviews.llvm.org/D105610
The file was modifiedllvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/update-phi.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
Commit 462d4de35b0c9ef7157e49e147fc448a40c829b1 by sam.mccall
[clangd] Add CMake option to (not) link in clang-tidy checks

This reduces the size of the dependency graph and makes incremental
development a little more pleasant (less rebuilding).

This introduces a bit of complexity/fragility as some tests verify
clang-tidy behavior. I attempted to isolate these and build/run as much
of the tests as possible in both configs to prevent rot.

Expectation is that (some) developers will use this locally, but
buildbots etc will keep testing clang-tidy.

Fixes https://github.com/clangd/clangd/issues/233

Differential Revision: https://reviews.llvm.org/D105679
The file was addedclang-tools-extra/clangd/test/diagnostics-tidy.test
The file was modifiedclang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
The file was removedclang-tools-extra/clangd/test/diagnostics.test
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
The file was modifiedclang-tools-extra/clangd/Features.cpp
The file was modifiedclang-tools-extra/clangd/test/lit.site.cfg.py.in
The file was modifiedclang-tools-extra/clangd/unittests/ConfigCompileTests.cpp
The file was modifiedclang-tools-extra/clangd/ParsedAST.cpp
The file was modifiedclang-tools-extra/clangd/Features.inc.in
The file was modifiedclang-tools-extra/clangd/test/lit.cfg.py
Commit c08dabb0f476e7ff3df70d379f3507707acbac4e by cullen.rhodes
[AArch64][SME] Add matrix register definitions and parsing support

SME introduces the ZA array, a new piece of architectural register state
consisting of a matrix of [SVLb x SVLb] bytes, where SVL is the
implementation defined Streaming SVE vector length and SVLb is the
number of 8-bit elements in a vector of SVL bits.

SME instructions consist of three types of matrix operands:

  * Tiles: a ZA tile is a square, two-dimensional sub-array of elements
  within the ZA array. These tiles make up the larger accumulator array
  and the granularity varies based on the element size, i.e.
    - ZAQ0..ZAQ15 (smallest tile granule)
    - ZAD0..ZAD7
    - ZAS0..ZAS3
    - ZAH0..ZAH1
    or ZAB0       (largest tile granule, single tile)
  * Tile vectors: similar to regular tiles, but have an extra 'h' or 'v'
  to tell how the vector at [reg+offset] is layed out in the tile,
  horizontally or vertically. E.g. za1h.h or za15v.q, which corresponds
  to vectors in registers ZAH1 and ZAQ15, respectively.
  * Accumulator matrix: this is the entire accumulator array ZA.

This patch adds the register classes and related operands and parsing
for SME instructions operating on the accumulator array.

The ADDHA and ADDVA instructions which operate on tiles are also added
in this patch to make some use of the code added, later patches will
make use of the other operands introduced here.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Co-authored by: Sander de Smalen (@sdesmalen)

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D105570
The file was addedllvm/test/MC/AArch64/SME/addha-u32.s
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
The file was addedllvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was addedllvm/test/MC/AArch64/SME/addva-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/addva-u32.s
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
The file was addedllvm/test/MC/AArch64/SME/addha-diagnostics.s
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.td
The file was addedllvm/test/MC/AArch64/SME/addva-u64.s
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was addedllvm/test/MC/AArch64/SME/addha-u64.s
The file was modifiedllvm/unittests/Target/AArch64/CMakeLists.txt
The file was addedllvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp
The file was addedllvm/lib/Target/AArch64/SMEInstrFormats.td
Commit a12e551882b68fe36856b0e66a5699fcf124aac5 by sebastian.neubauer
[AMDGPU] Precommit flat-scratch-init.ll test
The file was addedllvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
Commit 4359b870b187dca39573728002ce6bc0ffd4d469 by sebastian.neubauer
[AMDGPU] Init scratch only if necessary

If no scratch or flat instructions are used, we do not need to
initialize the flat scratch hardware register.

Differential Revision: https://reviews.llvm.org/D105920
The file was modifiedllvm/test/CodeGen/AMDGPU/call-constant.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cc-update.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory_clause.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
Commit 03a4702c884a0498db902aff34ebb19c48b4696b by fraser
[RISCV] Fix the neutral element in vector 'fadd' reductions

Using positive zero as the neutral element in 'fadd' reductions, while
it generates better code, is incorrect. The correct neutral element is
negative zero: 0.0 + -0.0 = 0.0, whereas -0.0 + -0.0 = -0.0.

There are perhaps more optimal lowerings of negative zero avoiding
constant-pool loads which could be left as future work.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D105902
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
Commit a36e9ee09d2ea46d752b6eea30168ec1fe73d17f by ivan.butygin
[mlir][SCF] populateSCFStructuralTypeConversionsAndLegality WhileOp support

Differential Revision: https://reviews.llvm.org/D105923
The file was modifiedmlir/test/Dialect/SCF/bufferize.mlir
The file was modifiedmlir/lib/Dialect/SCF/Transforms/StructuralTypeConversions.cpp
Commit b803294cf78714303db2d3647291a2308347ef23 by llvm-dev
[InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183)

As discussed on PR50183, we already fold to prefer 'select-of-idx' vs 'select-of-gep':

define <4 x i32>* @select0a(<4 x i32>* %a0, i64 %a1, i1 %a2, i64 %a3) {
  %gep0 = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a1
  %gep1 = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a3
  %sel = select i1 %a2, <4 x i32>* %gep0, <4 x i32>* %gep1
  ret <4 x i32>* %sel
}
-->
define <4 x i32>* @select1a(<4 x i32>* %a0, i64 %a1, i1 %a2, i64 %a3) {
  %sel = select i1 %a2, i64 %a1, i64 %a3
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %sel
  ret <4 x i32>* %gep
}

This patch adds basic handling for the 'fallthrough' cases where the gep idx == 0 has been folded away to the base address:

define <4 x i32>* @select0(<4 x i32>* %a0, i64 %a1, i1 %a2) {
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a1
  %sel = select i1 %a2, <4 x i32>* %a0, <4 x i32>* %gep
  ret <4 x i32>* %sel
}
-->
define <4 x i32>* @select1(<4 x i32>* %a0, i64 %a1, i1 %a2) {
  %sel = select i1 %a2, i64 0, i64 %a1
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %sel
  ret <4 x i32>* %gep
}

Differential Revision: https://reviews.llvm.org/D105901
The file was modifiedllvm/test/Transforms/InstCombine/select-gep.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Commit 810e4c3c66ed69ba82af687fc2a184bae874ca08 by stephen.tozer
[DebugInfo] Correctly update dbg.values with duplicated location ops

This patch fixes code that incorrectly handled dbg.values with duplicate
location operands, i.e. !DIArgList(i32 %a, i32 %a). The errors in
question were caused by either applying an update to dbg.value multiple
times when the update is only valid once, or by updating the
DIExpression for only the first instance of a value that appears
multiple times.

Differential Revision: https://reviews.llvm.org/D105831
The file was addedllvm/test/DebugInfo/salvage-duplicate-values.ll
The file was modifiedllvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
The file was modifiedllvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
The file was modifiedllvm/test/CodeGen/AArch64/stack-tagging-dbg.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64StackTagging.cpp
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit cf0aa0b66ccec87b0ac14f632998074e507be950 by stefanp
[NFC][PowerPC] Added test to check regsiter allocation for ACC registers

ACC regsiters are a combination of 4 consecutive vector regsiters and therefore
somtimes require special treatment for register allocation. This patch only
adds a test.
The file was addedllvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
Commit aff09545779a5346984e3c0d4f0d887185cb662d by thakis
[gn build] (manually) merge 462d4de35b0c
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/test/BUILD.gn
Commit 0722f3d0fad16d2427acf66a591bf3597fd0e0d8 by llvm-dev
Revert rGb803294cf78714303db2d3647291a2308347ef23 : "[InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183)"

Missed some BPF test changes that need addressing
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/Transforms/InstCombine/select-gep.ll
Commit 90e7f5d25902fe7d7a8eac1b6050f6a3f8c0919e by llvmgnsyncbot
[gn build] Port c08dabb0f476
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
Commit ee71c1bbccb19ed7a30b9aaf112a2c6ac2987193 by llvm-dev
[X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction.

We know that "CVTTPS2SI" returns 0x80000000 for out of range inputs (and for FP_TO_UINT, negative float values are undefined). We can use this to make unsigned conversions from vXf32 to vXi32 more efficient, particularly on targets without blend using the following logic:

small := CVTTPS2SI(x);
fp_to_ui(x) := small | (CVTTPS2SI(x - 2^31) & ARITHMETIC_RIGHT_SHIFT(small, 31))

Even on targets where "PBLENDVPS"/"PBLENDVB" exists, it is often a latency 2, low throughput instruction so this logic is applied there too (in particular for AVX2 also). It furthermore gets rid of one high latency floating point comparison in the previous lowering.

@TomHender checked the correctness of this for all possible floats between -1 and 2^32 (both ends excluded).

Original Patch by @TomHender (Tom Hender)

Differential Revision: https://reviews.llvm.org/D89697
The file was modifiedllvm/test/CodeGen/X86/concat-cast.ll
The file was modifiedllvm/test/CodeGen/X86/scalar-fp-to-i32.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/CodeGen/X86/scalar-fp-to-i64.ll
The file was modifiedllvm/test/CodeGen/X86/ftrunc.ll
The file was modifiedllvm/test/CodeGen/X86/fptoui-sat-scalar.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fptoui.ll
The file was modifiedllvm/test/CodeGen/X86/half.ll
The file was modifiedllvm/test/CodeGen/X86/vec_fp_to_int.ll
The file was modifiedllvm/test/CodeGen/X86/vec_cast3.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
Commit f7d931ac373fc23f5f4493300ecf7f3fe08b9d67 by david.spickett
[lldb][docs] Remove mention of subversion. NFC.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D103744
The file was modifiedlldb/docs/resources/build.rst
Commit 12d04ce9569edec68220888e02aab4fc25e55e01 by yedeng.yd
[NFC] [Coroutines] Remove unused CoroFree
The file was modifiedllvm/lib/Transforms/Coroutines/CoroElide.cpp
Commit d561b6fbdbe6d1da05fd92003a4ac1e37bf4b8bc by llvm-dev
[InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183) (REAPPLIED)

As discussed on PR50183, we already fold to prefer 'select-of-idx' vs 'select-of-gep':

define <4 x i32>* @select0a(<4 x i32>* %a0, i64 %a1, i1 %a2, i64 %a3) {
  %gep0 = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a1
  %gep1 = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a3
  %sel = select i1 %a2, <4 x i32>* %gep0, <4 x i32>* %gep1
  ret <4 x i32>* %sel
}
-->
define <4 x i32>* @select1a(<4 x i32>* %a0, i64 %a1, i1 %a2, i64 %a3) {
  %sel = select i1 %a2, i64 %a1, i64 %a3
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %sel
  ret <4 x i32>* %gep
}

This patch adds basic handling for the 'fallthrough' cases where the gep idx == 0 has been folded away to the base address:

define <4 x i32>* @select0(<4 x i32>* %a0, i64 %a1, i1 %a2) {
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a1
  %sel = select i1 %a2, <4 x i32>* %a0, <4 x i32>* %gep
  ret <4 x i32>* %sel
}
-->
define <4 x i32>* @select1(<4 x i32>* %a0, i64 %a1, i1 %a2) {
  %sel = select i1 %a2, i64 0, i64 %a1
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %sel
  ret <4 x i32>* %gep
}

Reapplied with a fix for the bpf "-bpf-disable-avoid-speculation" tests

Differential Revision: https://reviews.llvm.org/D105901
The file was modifiedllvm/test/Transforms/InstCombine/select-gep.ll
The file was modifiedllvm/test/CodeGen/BPF/adjust-opt-speculative1.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/CodeGen/BPF/adjust-opt-speculative2.ll
Commit df686842bc522b74755e8acbe3de8594e2c36bbd by djtodoro
[RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs

This new MIR pass removes redundant DBG_VALUEs.

After the register allocator is done, more precisely, after
the Virtual Register Rewriter, we end up having duplicated
DBG_VALUEs, since some virtual registers are being rewritten
into the same physical register as some of existing DBG_VALUEs.
Each DBG_VALUE should indicate (at least before the LiveDebugValues)
variables assignment, but it is being clobbered for function
parameters during the SelectionDAG since it generates new DBG_VALUEs
after COPY instructions, even though the parameter has no assignment.
For example, if we had a DBG_VALUE $regX as an entry debug value
representing the parameter, and a COPY and after the COPY,
DBG_VALUE $virt_reg, and after the virtregrewrite the $virt_reg gets
rewritten into $regX, we'd end up having redundant DBG_VALUE.

This breaks the definition of the DBG_VALUE since some analysis passes
might be built on top of that premise..., and this patch tries to fix
the MIR with the respect to that.

This first patch performs bacward scan, by trying to detect a sequence of
consecutive DBG_VALUEs, and to remove all DBG_VALUEs describing one
variable but the last one:

For example:

(1) DBG_VALUE $edi, !"var1", ...
(2) DBG_VALUE $esi, !"var2", ...
(3) DBG_VALUE $edi, !"var1", ...
...

in this case, we can remove (1).

By combining the forward scan that will be introduced in the next patch
(from this stack), by inspecting the statistics, the RemoveRedundantDebugValues
removes 15032 instructions by using gdb-7.11 as a testbed.

Differential Revision: https://reviews.llvm.org/D105279
The file was addedllvm/lib/CodeGen/RemoveRedundantDebugValues.cpp
The file was modifiedllvm/include/llvm/InitializePasses.h
The file was modifiedllvm/test/CodeGen/X86/O0-pipeline.ll
The file was modifiedllvm/test/CodeGen/PowerPC/O3-pipeline.ll
The file was modifiedllvm/include/llvm/CodeGen/MachinePassRegistry.def
The file was modifiedllvm/lib/CodeGen/CMakeLists.txt
The file was modifiedllvm/test/CodeGen/X86/opt-pipeline.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
The file was modifiedllvm/test/CodeGen/AArch64/O0-pipeline.ll
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was addedllvm/test/DebugInfo/MIR/X86/remove-redundant-dbg-vals.mir
The file was modifiedllvm/docs/SourceLevelDebugging.rst
The file was modifiedllvm/include/llvm/CodeGen/Passes.h
The file was modifiedllvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
The file was modifiedllvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
The file was modifiedllvm/include/llvm/CodeGen/CodeGenPassBuilder.h
The file was modifiedllvm/lib/CodeGen/CodeGen.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
The file was modifiedllvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
Commit d21772fa21de6a1c5d0f4792fbd175ff3d18c842 by alexshap
[lld][MachO] Code cleanup

Make use of ArgList::getLastArgValue. NFC.

Test plan: make check-lld-macho

Differential revision: https://reviews.llvm.org/D105452
The file was modifiedlld/MachO/Driver.cpp
Commit bdf31471c76b5ded9e8d5a039250c2a7ba7aead6 by gabor.marton
[Analyzer][solver] Add dump methods for (dis)equality classes.

This proved to be very useful during debugging.

Differential Revision: https://reviews.llvm.org/D103967
The file was addedclang/test/Analysis/expr-inspection-printState-eq-classes.c
The file was modifiedclang/test/Analysis/expr-inspection.c
The file was addedclang/test/Analysis/expr-inspection-printState-diseq-info.c
The file was modifiedclang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
Commit 25ee55c0baff316d3a7b1d7d2830a168af3fc46a by spatel
[SLP] match logical and/or as reduction candidates

This has been a work-in-progress for a long time...we finally have all of
the pieces in place to handle vectorization of compare code as shown in:
https://llvm.org/PR41312

To do this (see PhaseOrdering tests), we converted SimplifyCFG and
InstCombine to the poison-safe (select) forms of the logic ops, so now we
need to have SLP recognize those patterns and insert a freeze op to make
a safe reduction:
https://alive2.llvm.org/ce/z/NH54Ah

We get the minimal patterns with this patch, but the PhaseOrdering tests
show that we still need adjustments to get the ideal IR in some or all of
the motivating cases.

Differential Revision: https://reviews.llvm.org/D105730
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
Commit b18bda67915c67285c2b8d5fb88210f9a7436b8c by Tim Northover
ARM: reuse existing libcall global variable if possible.

If we try to create a new GlobalVariable on each iteration, the Module will
detect the name collision and "helpfully" rename later iterations by appending
".1" etc. But "___udivsi3.1" doesn't exist and we definitely don't want to try
to call it.

So instead check whether there's already a global with the right name in the
module and use that if so.
The file was modifiedllvm/lib/Target/ARM/ARMFastISel.cpp
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-call.ll
Commit 56e6d4742e6909bd7d2db201cc5e0e3e77c6f282 by ty1208chiang
[docs] Update CMake cross compiling guide link

The CMake community Wiki has been moved to the [[ https://gitlab.kitware.com/cmake/community/wikis/home | Kitware GitLab Instance ]].
Also, the original anchor for `Information how to set up various cross compiling toolchains` section might not work as expected. The original content is now being collapsed, so browser won't navigate to the right section directly.

Hence, I think it might be better to provide the section name instead of `this section` with link to help readers find the right section by themselves.

Reviewed By: void

Differential Revision: https://reviews.llvm.org/D104996
The file was modifiedllvm/docs/CMake.rst
Commit b70dde522d50c4aa5471ed7270fb9191c6b35424 by springerm
[mlir][linalg] Fix typo in ExtractSliceOfPadTensorSwapPattern

Differential Revision: https://reviews.llvm.org/D105607
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
The file was modifiedmlir/test/Dialect/Linalg/subtensor-of-padtensor.mlir
Commit fe52296a3433aebc95fadb6f0b187bc3433c9058 by Jinsong Ji
[AIX] Enable dollar sign as PC in inlineasm

$ is used as PC for PowerPC inlineasm, ELF use it,
enable it for AIX XCOFF as well.

Reviewed By: #powerpc, amyk, nemanjai

Differential Revision: https://reviews.llvm.org/D105956
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
The file was addedllvm/test/MC/PowerPC/dollarpc.s
The file was addedllvm/test/CodeGen/PowerPC/inline-asm-dollarpc.ll
Commit 67002b5f20c2c4c9bd5e89f79077ae8d6e165aae by arnamoy.bhattacharyya
[flang][OpenMP] Fix semantic check of test case in taskloop simd construct

The following semantic check is removed in OpenMP Version 5.0:
```
Taskloop simd construct restrictions: No reduction clause can be specified.
```

Also fix several typos.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D105874
The file was modifiedflang/test/Semantics/omp-clause-validity01.f90
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
The file was modifiedflang/test/Semantics/omp-taskloop-simd01.f90
Commit 93dc73b1e0f31c712e5b8bbac14491ce55c414ad by yitzhakm
[Lexer] Fix bug in `makeFileCharRange` called on split tokens.

When the end loc of the specified range is a split token, `makeFileCharRange`
does not process it correctly.  This patch adds proper support for split tokens.

Differential Revision: https://reviews.llvm.org/D105365
The file was modifiedclang/lib/Lex/Lexer.cpp
The file was modifiedclang/unittests/Lex/LexerTest.cpp
Commit 77396bbc981a96e22eae9f0bc79a7d55316501c1 by Louis Dionne
[runtimes] NFCI: Drop intermediate CMake variable TARGET_TRIPLE

We might as well use the various XXX_TARGET_TRIPLE variables directly.
The file was modifiedlibcxx/test/CMakeLists.txt
The file was modifiedlibcxx/lib/abi/CMakeLists.txt
The file was modifiedlibcxxabi/CMakeLists.txt
The file was modifiedlibcxxabi/test/CMakeLists.txt
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibunwind/CMakeLists.txt
The file was modifiedlibunwind/test/CMakeLists.txt
Commit 2eb50baf059648214cb1c624b5269978a62e86a1 by a.bataev
[SLP]Workaround for InsertSubVector cost.

The cost of the InsertSubvector shuffle kind cost is not complete and
may end up with just extracts + inserts costs in many cases. Added
a workaround to represent it as a generic PermuteSingleSrc, which is
still pessimistic but better than InsertSubvector.

Differential Revision: https://reviews.llvm.org/D105827
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/resched.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/cmp_commute.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
Commit 372bb082524de3db9361ff7b5c1992774f081276 by jay.foad
[AMDGPU] Check llc-pipeline.ll with -match-full-lines -strict-whitespace

This prevents breaking the indentation that shows the structure of the
pass managers.

Differential Revision: https://reviews.llvm.org/D105891
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Commit aefd6c615c91a2af89fa3697cf1813aac0f622de by aaron
Combine two diagnostics into one and correct grammar

The anonymous and non-anonymous bit-field diagnostics are easily
combined into one diagnostic. However, the diagnostic was missing a
"the" that is present in the almost-identically worded
warn_bitfield_width_exceeds_type_width diagnostic, hence the changes to
test cases.
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaCXX/ms_wide_bitfield.cpp
The file was modifiedclang/test/SemaObjC/class-bitfield.m
The file was modifiedclang/test/Sema/bitfield.c
The file was modifiedclang/lib/Sema/SemaDecl.cpp
Commit eac167073924e2a27f26a8931b038c1e18cdb08d by sander.desmalen
[CostModel][AArch64] Make loads/stores of <vscale x 1 x eltty> invalid.

At the moment, <vscale x 1 x eltty> are not yet fully handled by the
code-generator, so to avoid vectorizing loops with that VF, we mark the
cost for these types as invalid.
The reason for not adding a new "TTI::getMinimumScalableVF" is because
the type is supposed to be a type that can be legalized. It partially is,
although the support for these types need some more work.

Reviewed By: paulwalker-arm, dmgreen

Differential Revision: https://reviews.llvm.org/D103882
The file was modifiedllvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
The file was modifiedllvm/test/Analysis/CostModel/AArch64/sve-gather.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
The file was modifiedllvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
Commit 47269da5d83e079a565439cbbacd4bb119ed0aff by Matthew.Arsenault
GlobalISel: Handle lowering non-power-of-2 extloads
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
Commit efaf3099c8cec1954831ee28a2f75a72096f50eb by sander.desmalen
[LV] Print remark when loop cannot be vectorized due to invalid costs.

This patch emits remarks for instructions that have invalid costs for
a given set of vectorization factors. Some example output:

  t.c:4:19: remark: Instruction with invalid costs prevented vectorization at VF=(vscale x 1): load
      dst[i] = sinf(src[i]);
                    ^
  t.c:4:14: remark: Instruction with invalid costs prevented vectorization at VF=(vscale x 1, vscale x 2, vscale x 4): call to llvm.sin.f32
      dst[i] = sinf(src[i]);
               ^
  t.c:4:12: remark: Instruction with invalid costs prevented vectorization at VF=(vscale x 1): store
      dst[i] = sinf(src[i]);
             ^

Reviewed By: fhahn, kmclaughlin

Differential Revision: https://reviews.llvm.org/D105806
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit b155c871f2e21beed45d15a25f7c84fb4f0c1d93 by spatel
[InstCombine] add tests for icmp with constant offset and no-wrap flags; NFC
The file was modifiedllvm/test/Transforms/InstCombine/icmp-add.ll
Commit ca6e117d86341682e20025f204294c0ca78c355e by spatel
[InstCombine] reorder icmp with offset folds for better results

This set of folds was added recently with:
c7b658aeb526
0c400e895306
40b752d28d95

...and I noted that this wasn't likely to fire in code derived
from C/C++ source because of nsw in particular. But I didn't
notice that I had placed the code above the no-wrap block
of transforms.

This is likely the cause of regressions noted from the previous
commit because -- as shown in the test diffs -- we may have
transformed into a compare with an arbitrary constant rather
than a simpler signbit test.
The file was modifiedllvm/test/Transforms/InstCombine/icmp-add.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Commit 338314f9c26d4594d49fdd3a7656d71c77255c54 by david.green
[ARM] Lower v16i8 -> i64 VMLA reductions.

MVE does not have a VMLALV instruction that can perform v16i8 -> i64
reductions, like it does for v8i16->i64 and v4i32->i64 reductions. That
means that the pattern to create them will be spilt up by type
legalization, creating a lot of instructions.

This extends the patterns for matching i64 reductions a little to handle
the v16i8->i64 case. We need to turn them into a pair of v8i16->i64
VMLALVs that each perform half of the reduction and are summed together
(so the later is a VMLALVA). The order of the lanes does not matter for
the reduction so we generate a MVEEXT for the extension, that will
either be folded into a extending load or can be optimized to a
VREV/VMOVL. Some of the resulting codegen isn't optimal, but will be
improved in a later patch.

Differential Revision: https://reviews.llvm.org/D105680
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
Commit 7de2173c2a4c45711831cfee3ccf53690c76ff07 by i
[ELF] --fortran-common: prefer STB_WEAK to COMMON

The ELF specification says "The link editor honors the common definition and
ignores the weak ones." GNU ld and our Symbol::compare follow this, but the
--fortran-common code (D86142) made a mistake on the precedence.

Fixes https://bugs.llvm.org/show_bug.cgi?id=51082

Reviewed By: peter.smith, sfertile

Differential Revision: https://reviews.llvm.org/D105945
The file was modifiedlld/ELF/InputFiles.cpp
The file was modifiedlld/test/ELF/common-archive-lookup.s
Commit 122b0220fd45ee71acda912b0b712bb8edb6ba46 by tlively
[WebAssembly] Remove datalayout strings from llc tests

The data layout strings do not have any effect on llc tests and will become
misleadingly out of date as we continue to update the canonical data layout, so
remove them from the tests.

Differential Revision: https://reviews.llvm.org/D105842
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-offset.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/umulo-i64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/inline-asm-roundtrip.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/offset-atomics.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/inline-asm.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/unused-argument.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/bulk-memory64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/mem-intrinsics.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/f64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/implicit-def.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/address-offsets.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-br-i1.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/i64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/return-address-emscripten.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/target-features-tls.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/PR41149.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/unsupported-function-bitcasts.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-ehsjlj-options.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-conversions.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/weak.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-zero-offset.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-scalar-to-vector.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/byval.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/immediates.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/i64-load-store-alignment.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/multivalue.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/select.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-call-indirect64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-build-vector.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-build-pair.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/debugtest-opt.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/eh-lsda.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/debugtrap.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/inline-asm-m.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-global-dtors.ll
The file was modifiedllvm/test/MC/WebAssembly/data-symbol-in-text-section.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/f32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/atomic-mem-consistency.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/function-bitcasts.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/muloti4.ll
The file was modifiedllvm/test/MC/WebAssembly/assembler-binary.ll
The file was modifiedllvm/test/MC/WebAssembly/comdat-sections.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-noreg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/snan_literal.ll
The file was modifiedllvm/test/MC/WebAssembly/array-fill.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/legalize.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/tailcall.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/custom-sections.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel.ll
The file was modifiedllvm/test/MC/WebAssembly/debug-localvar.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-sjlj-sret.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/clear-cache.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/function-bitcasts-varargs.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-ehsjlj-multi-return.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/pr47375.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/function-pointer64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/copysign-casts.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/PR40267.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/dbgvalue.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
The file was modifiedllvm/test/MC/WebAssembly/file-headers.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-extended-extract.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/vtable.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/func.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-unsupported.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/divrem-constant.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/global.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/switch-unreachable-default.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/returned.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/atomic-fence.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/comparisons-f64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/function-info.mir
The file was modifiedllvm/test/CodeGen/WebAssembly/call-indirect.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/unreachable.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/call-pic.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/return-void.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/tls-local-exec.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/import-module.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/cfg-stackify-eh.mir
The file was modifiedllvm/test/CodeGen/WebAssembly/target-features.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/atomic-fence.mir
The file was modifiedllvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/atomic-rmw.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-splat.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/conv-trap.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/null-streamer.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-reductions.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/irreducible-cfg-exceptions.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/PR41841.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/i128.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/stack-insts.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-extending.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/global_dtors.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/offset.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/swiftcc.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/main-three-args.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-i24.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/multivalue-stackify.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/signext-arg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-arith.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/bulk-memory.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/f16.ll
The file was modifiedllvm/test/MC/WebAssembly/function-alias.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/masked-shifts.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/globl.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-select.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/signext-inreg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/memory-addr32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/store.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/call.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/signext-zeroext.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/reference-types.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/dead-vreg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/comparisons-i32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/PR40172.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-pr47040.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/irreducible-cfg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/cfg-stackify.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/i32-load-store-alignment.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/return-address-unknown.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/exception.mir
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-concat.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/irreducible-cfg.mir
The file was modifiedllvm/test/CodeGen/WebAssembly/memory-addr64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/multivalue-stackify.py
The file was modifiedllvm/test/CodeGen/WebAssembly/i32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/ident.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/main-with-args.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/phi.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-i256.ll
The file was modifiedllvm/test/MC/WebAssembly/debug-byval-struct.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/comparisons-i64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-nonconst-sext.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/mutable-globals.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/atomic-pic.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/offset-folding.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/return-int32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-sext-inreg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-bitcasts.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/reg-stackify.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/export-name.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/main-no-args.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/main-declaration.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/multi-return.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/switch-in-loop.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/comparisons-f32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/offset-fastisel.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/negative-base-reg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/exception.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/i128-returned.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-illegal-signext.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/frem.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/load-store-static.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/vector-sdiv.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/libcalls.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-comparisons.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/conv.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/indirect-import.ll
Commit 5099e0156818665ae5381337f64ca68d659e0556 by Louis Dionne
[runtimes] Inherit the TARGET_TRIPLE that may be set by LLVM
The file was modifiedlibcxxabi/CMakeLists.txt
The file was modifiedlibunwind/CMakeLists.txt
The file was modifiedlibcxx/CMakeLists.txt
Commit 970e0900104d6f67a9c15fa9c913cf3eeba5d06a by tlively
[WebAssembly] Codegen for v128.loadX_lane instructions

Replace the experimental clang builtin and LLVM intrinsics for these
instructions with normal codegen patterns. Resolves PR50433.

Differential Revision: https://reviews.llvm.org/D105950
The file was modifiedclang/test/Headers/wasm.c
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
The file was modifiedclang/lib/Headers/wasm_simd128.h
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-build-vector.ll
Commit 1e30bf8621cc123a7afba3246a36187c5ce3c836 by efriedma
[SelectionDAG] Add an overload of getStepVector that assumes step 1.

This is mostly a minor convenience, but the pattern seems frequent
enough to be worthwhile (and we'll probably add more uses in the
future).

Differential Revision: https://reviews.llvm.org/D105850
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAG.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 9c2de2382197109388a25c9486f0e4408896d36e by Saleem Abdulrasool
Demangle: correct swift_async demangling for Microsoft scheme

The emission was corrected for the swift_async calling convention but
the demangling support was not.  This repairs the demangling support as
well.
The file was modifiedllvm/lib/Demangle/MicrosoftDemangle.cpp
The file was modifiedllvm/test/Demangle/ms-mangle.test
Commit 5e4b33fe9218703f0b29e2446159bcf4202d15fa by nikita.ppv
[Verifier] Improve incompatible attribute type check

A couple of attributes had explicit checks for incompatibility
with pointer types. However, this is already handled generically
by the typeIncompatible() check. We can drop these after adding
SwiftError to typeIncompatible().

However, the previous implementation of the check prints out all
attributes that are incompatible with a given type, even though
those attributes aren't actually used. This has the annoying
result that the error message changes every time a new attribute
is added to the list. Improve this by explicitly finding which
attribute isn't compatible and printing just that.
The file was modifiedllvm/lib/IR/Attributes.cpp
The file was modifiedllvm/test/Verifier/swifterror.ll
The file was modifiedllvm/test/Verifier/sret.ll
The file was modifiedllvm/test/Verifier/byval-1.ll
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/test/Verifier/inalloca1.ll
The file was modifiedllvm/test/Verifier/align.ll
The file was modifiedllvm/test/Verifier/byref.ll
The file was modifiedllvm/test/Verifier/preallocated-invalid.ll
The file was modifiedllvm/test/Verifier/noundef.ll
Commit fbab8e6f10dd982281717b5c2b0ce7609ee1ccec by joker.eph
Remove uses of deprecated target AllPassesAndDialectsNoRegistration in Bazel (NFC)

It was an alias for a long time.
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Commit 14362bf1b2589f8a769709be599f24ab7eee6d6e by Vitaly Buka
[scudo] Don't enabled MTE for small alignment

Differential Revision: https://reviews.llvm.org/D105954
The file was modifiedcompiler-rt/lib/scudo/standalone/memtag.h
Commit 31b8f400066c3998edc5650300301c1219468ef2 by david.green
[ARM] Move add(VMLALVA(A, X, Y), B) to VMLALVA(add(A, B), X, Y)

For i64 reductions we currently try and convert add(VMLALV(X, Y), B) to
VMLALVA(B, X, Y), incorporating the addition into the VMLALVA. If we
have an add of an existing VMLALVA, this patch pushes the add up above
the VMLALVA so that it may potentially be simplified further, for
example being folded into another VMLALV.

Differential Revision: https://reviews.llvm.org/D105686
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit a4856c739c570d5115d0b7646a58b918890d37d4 by lebedev.ri
[NFC][PhaseOrdering] Add test for the lack of CSE after SimplifyCFG (PR51092)
The file was addedllvm/test/Transforms/PhaseOrdering/X86/earlycse-after-simplifycfg-two-entry-phi-node-folding.ll
Commit cd88a01cb8e90b5eae9f8bde82ff362b222a61c4 by nikita.ppv
[Attributes] Use single method to fetch type from AttributeSet (NFC)

While it is nice to have separate methods in the public AttributeSet
API, we can fetch the type from the internal AttributeSetNode
using a generic API for all type attribute kinds.
The file was modifiedllvm/lib/IR/AttributeImpl.h
The file was modifiedllvm/lib/IR/Attributes.cpp
Commit dfbfc277b2a45d2cec21763fb1a8be58cd538df8 by lebedev.ri
[NFC] Drop redundant check prefixes in newly added test file
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/earlycse-after-simplifycfg-two-entry-phi-node-folding.ll
Commit 850b57c5fbe7b44d18c9667bb31adfbe307453a6 by Louis Dionne
[runtimes] Bring back TARGET_TRIPLE

This commit reverts 5099e01568 and 77396bbc98, which broke the build
in various ways. I'm reverting until I can investigate, since that
change appears to be way more subtle than it seemed.
The file was modifiedlibcxx/lib/abi/CMakeLists.txt
The file was modifiedlibcxxabi/CMakeLists.txt
The file was modifiedlibunwind/test/CMakeLists.txt
The file was modifiedlibcxxabi/test/CMakeLists.txt
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibunwind/CMakeLists.txt
The file was modifiedlibcxx/test/CMakeLists.txt
Commit 8461995d35a417b4d161112ded0c0980280c5f64 by gcmn
[Bazel] Uniformly export all MLIR td files

CMake would have no restrictions on this and the custom list is a pain
to maintain.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D106003
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Commit 4fd0addb68f603112171a79353bc2a0f1d148183 by llvm-dev
[SLP] Fix case of variable name. NFCI.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 3bda1c4e22cdf54f899f0330a98213337df9b3d4 by i
[docs] Fix :option:`--file-header` reference in llvm-readelf.rst after D105532
The file was modifiedllvm/docs/CommandGuide/llvm-readelf.rst
Commit ba2690b17b9e463b80a1d6c675e3d04fc2974083 by a.bataev
[SLP][NFC]Fix variables names, NFC.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 76b7d3432e38bb7690c3bbd4940786b5cb751b95 by Stanislav.Mekhanoshin
[AMDGPU] Add TII::isIgnorableUse() to allow VOP rematerialization

Any def of EXEC prevents rematerialization of any VOP instruction
because of the physreg use. Create a callback to check if the
physreg use can be ingored to allow rematerialization.

Differential Revision: https://reviews.llvm.org/D105836
The file was modifiedllvm/test/CodeGen/AMDGPU/remat-vop.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/lib/CodeGen/LiveRangeEdit.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/remat-sop.mir
Commit e75a2dfe209d9cc68e4d9813a38441c45d51d8bb by listmail
[tests] Stablize tests for possible change in deref semantics

There's a potential change in dereferenceability attribute semantics in the nearish future.  See llvm-dev thread "RFC: Decomposing deref(N) into deref(N) + nofree" and D99100 for context.

This change simply adds appropriate attributes to tests to keep transform logic exercised under both old and new/proposed semantics.  Note that for many of these cases, O3 would infer exactly these attributes on the test IR.

This change handles the idiomatic pattern of a dereferenceable object being passed to a call which can not free that memory.  There's a couple other tests which need more one-off attention, they'll be handled in another change.
The file was modifiedllvm/test/Transforms/LICM/hoist-deref-load.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll
The file was modifiedllvm/test/Transforms/MemCpyOpt/callslot_deref.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/int64-and-ptr.ll
The file was modifiedllvm/test/CodeGen/X86/memcmp-mergeexpand.ll
The file was modifiedllvm/test/Transforms/GVN/PRE/load-pre-licm.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcmp-memcmp.ll
The file was modifiedllvm/test/Transforms/TailCallElim/reorder_load.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/pair-int32-int32.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/split-block-does-work.ll
The file was modifiedllvm/test/Analysis/ValueTracking/deref-bitcast-of-gep.ll
The file was modifiedllvm/test/CodeGen/X86/load-partial.ll
The file was modifiedllvm/test/Transforms/GVN/loadpre-context.ll
The file was modifiedllvm/test/Transforms/InstCombine/select.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/gep-references-bb.ll
The file was modifiedllvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/alias-merge-blocks.ll
The file was modifiedllvm/test/Transforms/InstCombine/call-guard.ll
The file was modifiedllvm/test/Transforms/JumpThreading/guards.ll
The file was modifiedllvm/test/CodeGen/X86/licm-dominance.ll
The file was modifiedllvm/test/Transforms/InstCombine/masked_intrinsics.ll
The file was modifiedllvm/test/CodeGen/X86/hoist-invariant-load.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/entry-block-shuffled.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/multiple-blocks-does-work.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/X86/SpeculativeExec.ll
The file was modifiedllvm/test/Transforms/GVN/PRE/pre-load.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
Commit d37689e9ababe4badbc0132950425d8f3434a5b8 by martin
[libcxx] [test] Remove a LIBCXX-WINDOWS-FIXME in trivial_abi/unique_ptr_ret

This is the same thing that was clarified in D105906 for weak_ptr_ret.

Differential Revision: https://reviews.llvm.org/D105965
The file was modifiedlibcxx/test/libcxx/memory/trivial_abi/unique_ptr_ret.pass.cpp
Commit b86ddfdb9a80f2343510e07209ceda59d72972e3 by listmail
Global variables with strong definitions cannot be freed

With the current deref semantics, this is redundant - since we assume that anything which is dereferenceable (ever) can't be freed - but it becomes neccessary for the deref-at-point semantics.

Testing wise, this is covered by test/CodeGen/X86/hoist-invariant-load.ll when -use-dereferenceable-at-point-semantics is active.  I didn't bother duplicating the command line since a) it's an in-development mode, and b) the change is pretty obvious.
The file was modifiedllvm/lib/IR/Value.cpp
Commit 7b47de774fd43eb5be7aee86c6f8c15999295b36 by nicolas.vasilache
[mlir] NFC - Add AffineMap::replace variant with dim/symbol inference
The file was modifiedmlir/include/mlir/IR/AffineMap.h
The file was modifiedmlir/lib/IR/AffineMap.cpp
Commit e23dce6c974477d3476bee5256a83a9aaea8eae4 by Steven Wu
[Support] Get correct number of physical cores on Apple Silicon

Fix a bug that `computeHostNumPhysicalCores` is fallback to default
unknown when building for Apple Silicon macs.

rdar://80533675

Reviewed By: arphaman

Differential Revision: https://reviews.llvm.org/D106012
The file was modifiedllvm/lib/Support/Host.cpp
Commit 1e4a417ee639b867b783e52949d22c1965ab25d0 by Jonas Devlieghere
[lldb] Always call DestroyImpl from Process::Finalize

Always destroy the process, regardless of its private state. This will
call the virtual function DoDestroy under the hood, giving our derived
class a chance to do the necessary tear down, including what to do when
the private state is eStateExited.

Differential revision: https://reviews.llvm.org/D106004
The file was modifiedlldb/source/Target/Process.cpp
Commit de448c0a9e5088979526e2e67152fe547ae4ccf0 by Jonas Devlieghere
[lldb] Make TargetList iterable (NFC)

Make it possible to iterate over the TargetList.

Differential revision: https://reviews.llvm.org/D105914
The file was modifiedlldb/source/Core/Debugger.cpp
The file was modifiedlldb/include/lldb/Target/TargetList.h
Commit ac500fd18f0615c45d9d127bfb576ffa1e11425a by Vitaly Buka
[asan][clang] Add flag to outline instrumentation

Summary This option can be used to reduce the size of the
binary. The trade-off in this case would be the run-time
performance.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D105726
The file was addedclang/test/CodeGen/asan-use-callbacks.cpp
The file was modifiedclang/docs/AddressSanitizer.rst
The file was modifiedclang/docs/UsersManual.rst
The file was modifiedclang/include/clang/Driver/SanitizerArgs.h
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/test/Driver/fsanitize.c
The file was modifiedclang/lib/Driver/SanitizerArgs.cpp
Commit 7e496c29e2bc85e5b769e0175ca9637dbff5615a by listmail
[tests] Stablize tests for possible change in deref semantics

This is conceptually part of e75a2dfe.  This file contains both tests whose results don't change (with the right attributes added), and tests which fundementally regress with the current proposal.  Doing the update took some care, thus the seperate change.

Here's the e75a2dfe context repeated:

There's a potential change in dereferenceability attribute semantics in the nearish future.  See llvm-dev thread "RFC: Decomposing deref(N) into deref(N) + nofree" and D99100 for context.

This change simply adds appropriate attributes to tests to keep transform logic exercised under both old and new/proposed semantics.  Note that for many of these cases, O3 would infer exactly these attributes on the test IR.

This change handles the idiomatic pattern of a dereferenceable object being passed to a call which can not free that memory.  There's a couple other tests which need more one-off attention, they'll be handled in another change.
The file was modifiedllvm/test/Analysis/BasicAA/dereferenceable.ll
Commit df538fdaa985e7e64a572dd84b878c562899e5e8 by nicolas.vasilache
[mlir][affine] Add single result affine.min/max -> affine.apply canonicalization.

Differential Revision: https://reviews.llvm.org/D106014
The file was modifiedmlir/test/Dialect/Affine/canonicalize.mlir
The file was modifiedmlir/lib/Dialect/Affine/IR/AffineOps.cpp
Commit 0e49c54a8cbd3e779e5526a5888c683c01cc3c50 by Jon Roelofs
[AArch64] Fix selection of G_UNMERGE <2 x s16>

Differential revision: https://reviews.llvm.org/D106007
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
Commit 5366de7375e653998ff80c3c6cbdfa4f9b9046e3 by aeubanks
[SimpleLoopUnswitch] Don't non-trivially unswitch loops with catchswitch exits

SplitBlock() can't handle catchswitch.

Fixes PR50973.

Reviewed By: aheejin

Differential Revision: https://reviews.llvm.org/D105672
The file was addedllvm/test/Transforms/SimpleLoopUnswitch/catchswitch.ll
The file was modifiedllvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
The file was modifiedllvm/lib/Transforms/Utils/BasicBlockUtils.cpp
Commit d3816ef042d7506e154fb708456147a11264895c by aeubanks
Precommit test for D106017
The file was modifiedllvm/test/Transforms/InstCombine/malloc-free-delete.ll
Commit 7cb25f53875e5490bccaf297accd34b7331cfb8b by dschuff
[llvm-strip][WebAssembly] Support strip flags

Summary:
Add support for the basic section stripping (and keeping) flags for wasm:
strip with no flags, --strip-all, --strip-debug,
--only-section, --keep-section, and --only-keep-debug.

Factor section removal into a function and use a predicate chain like
the ELF implementation.

Reviewers: jhenderson, sbc100

Differential Revision: https://reviews.llvm.org/D73820
The file was modifiedllvm/tools/llvm-objcopy/ConfigManager.cpp
The file was addedllvm/test/tools/llvm-objcopy/wasm/basic-keep.test
The file was addedllvm/test/tools/llvm-objcopy/wasm/strip-all.test
The file was addedllvm/test/tools/llvm-objcopy/wasm/basic-strip.test
The file was addedllvm/test/tools/llvm-objcopy/wasm/only-keep-debug.test
The file was modifiedllvm/tools/llvm-objcopy/wasm/WasmObjcopy.cpp
The file was addedllvm/test/tools/llvm-objcopy/wasm/basic-only-section.test
The file was addedllvm/test/tools/llvm-objcopy/wasm/strip-reloc.test
The file was addedllvm/test/tools/llvm-objcopy/wasm/strip-debug.test
Commit 7e29e57917a9ecb8f1b07aa2d99b0fbea91cda61 by llvm-project
[Polly] Fix misleading debug message. NFC.

The number of parameters can be the reason for aliasing checks not being
generated, but most of the time it for other reasons.
The file was modifiedpolly/lib/Analysis/ScopBuilder.cpp
Commit d1116697be059350a5b04d1af29e2d454afda746 by wolfgang_pieb
[ARM] Fix RELA relocations for 32bit ARM.

RELA relocations for 32 bit ARM ignored the addend. Some tools generate
them instead of REL type relocations. This fixes PR50473.

    Reviewed By: MaskRay, peter.smith

    Differential Revision: https://reviews.llvm.org/D105214
The file was modifiedllvm/lib/Object/RelocationResolver.cpp
The file was addedllvm/test/DebugInfo/ARM/dwarfdump-rela.yaml
Commit 3bf101f34cd466f103af00c764dc1cddb6eb14a6 by aeubanks
[docs][OpaquePtr] Remove finished task
The file was modifiedllvm/docs/OpaquePointers.rst
Commit 58494c856a15f5b0e886c7baf5d505ac6c05dfe5 by owenca
[clang-format] Make BreakAfterReturnType work with K&R C functions

This fixes PR50999.

Differential Revision: https://reviews.llvm.org/D105964
The file was modifiedclang/unittests/Format/FormatTest.cpp
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
Commit 0c7a4870c5b63935b7f0c7cbc380b497341dd203 by georgios.rokos
[libomptarget] Keep the Shadow Pointer Map up-to-date

D105812 introduced a regression where if a PTR_AND_OBJ entry was mapped on the device, then the OBJ was deallocated and then reallocated at a different address, the Shadow Pointer Map would still contain an entry for the PTR but pointing to the old address. This caused test `env/base_ptr_ref_count.c` to fail.

Differential Revision: https://reviews.llvm.org/D105947
The file was modifiedopenmp/libomptarget/src/omptarget.cpp
Commit 483df573135f2287bfd1a6d5c4d7196036f13cbd by Steven Wu
[Support] Turn on SupportTest for Apple Silicon

Follow up for D106012, turn on unittest for Host on Apple Silicon.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D106020
The file was modifiedllvm/unittests/Support/Host.cpp
Commit d14310306827f5c0a4feb6a9ffddddcdfb24fcca by Jon Roelofs
[GlobalOpt] Fix a miscompile when evaluating struct initializers.

The bug was that evaluateBitcastFromPtr attempts a narrowing to a struct's 0th
element of a store that covers other elements. While this is okay on the load
side, applying it to stores causes us to miss the writes to the additionally
covered elements.

rdar://79503568

Differential revision: https://reviews.llvm.org/D105838
The file was addedllvm/test/Transforms/GlobalOpt/store-struct-element.ll
The file was modifiedllvm/lib/Transforms/Utils/Evaluator.cpp
Commit 4a4229f70f815a0a83e8e226ec1718af693faf4d by tlively
[WebAssembly] Codegen for v128.storeX_lane instructions

Replace the experimental clang builtins and LLVM intrinsics for these
instructions with normal codegen patterns. Resolves PR50435.

Differential Revision: https://reviews.llvm.org/D106019
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-build-pair.ll
The file was modifiedclang/test/Headers/wasm.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
The file was modifiedclang/lib/Headers/wasm_simd128.h
Commit 9cfec72ffeec242783b70e792c50bd163dcf9dbb by zeratul976
[clang] Refactor AST printing tests to share more infrastructure

Differential Revision: https://reviews.llvm.org/D105457
The file was modifiedclang/unittests/AST/NamedDeclPrinterTest.cpp
The file was modifiedclang/unittests/AST/ASTPrint.h
The file was modifiedclang/unittests/AST/DeclPrinterTest.cpp
The file was modifiedclang/unittests/AST/StmtPrinterTest.cpp
Commit 4118858b4e4d072ac2ceef6cbc52088438781f39 by arthur.j.odwyer
[libc++] NFCI: Restore code duplication in wrap_iter, with test.

It turns out that D105040 broke `std::rel_ops`; we actually do need
both a one-template-parameter and a two-template-parameter version of
all the comparison operators, because if we have only the heterogeneous
two-parameter version, then `x > x` is ambiguous:

    template<class T, class U> int f(S<T>, S<U>) { return 1; }
    template<class T> int f(T, T) { return 2; }  // rel_ops
    S<int> s; f(s,s);  // ambiguous between #1 and #2

Adding the one-template-parameter version fixes the ambiguity:

    template<class T, class U> int f(S<T>, S<U>) { return 1; }
    template<class T> int f(T, T) { return 2; }  // rel_ops
    template<class T> int f(S<T>, S<T>) { return 3; }
    S<int> s; f(s,s);  // #3 beats both #1 and #2

We have the same problem with `reverse_iterator` as with `__wrap_iter`.
But so do libstdc++ and Microsoft, so we're not going to worry about it.

Differential Revision: https://reviews.llvm.org/D105894
The file was modifiedlibcxx/include/__iterator/wrap_iter.h
The file was addedlibcxx/test/std/containers/iterator.rel_ops.compile.pass.cpp
Commit a7749c3f79a8b0df9ffe8a814a13f9450981b292 by kuterdinel
[AMDGPU] Use update_test_checks.py script for annotate kernel features tests.

This patch makes the annotate kernel features tests use the update_tests_checks.py
script. Which makes it easy to update the tests.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D105864
The file was modifiedllvm/test/CodeGen/AMDGPU/annotate-kernel-features.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
Commit ea469b08b847cef5f4c8187228f1e4bbf881706a by airlied
libclc: Add -cl-no-stdinc to clang flags on clang >=13

cf3ef15a6ec5e5b45c6c54e8fbe3769255e815ce ("[OpenCL] Add builtin
declarations by default.")
switched behaviour to include "opencl-c-base.h". We don't want or need
that for libclc so pass the flag to revert to old behaviour.

Fixes build since cf3ef15a6ec5e5b45c6c54e8fbe3769255e815ce

Reviewed By: tstellar

Differential Revision: https://reviews.llvm.org/D99794
The file was modifiedlibclc/CMakeLists.txt
Commit 090f007e3481863430e4443765769e73f8f40e5f by airlied
[OpenCL][NFC] opencl-c.h: reorder atomic operations

This just reorders the atomics, it doesn't change anything except their layout in the header.

This is a prep patch for adding some conditionals around these for CL3.0 but that patch is much easier to review if all the atomic operations are grouped together like this.

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D105601
The file was modifiedclang/lib/Headers/opencl-c.h
Commit de79ba9f9a2de3d86fa3f44b57e147844b6f2625 by airlied
[OpenCL] opencl-c.h: CL3.0 generic address space

This is one of the easier pieces of adding CL3.0 support.

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D105526
The file was modifiedclang/lib/Headers/opencl-c.h
Commit b9c3941cd61de1e1b9e4f3311ddfa92394475f4b by lkail
[PowerPC] Generate inlined quadword lock free atomic operations via AtomicExpand

This patch uses AtomicExpandPass to implement quadword lock free atomic operations. It adopts the method introduced in https://reviews.llvm.org/D47882, which expand atomic operations post RA to avoid spilling that might prevent LL/SC progress.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D103614
The file was modifiedllvm/lib/CodeGen/AtomicExpandPass.cpp
The file was addedllvm/test/CodeGen/PowerPC/atomics-i128.ll
The file was addedllvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp
The file was modifiedllvm/lib/Target/PowerPC/CMakeLists.txt
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/O3-pipeline.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/lib/Target/PowerPC/PPC.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetMachine.cpp
Commit 8b426bdaf1686ed6fb3460b0f03a7ae6f23bce70 by llvmgnsyncbot
[gn build] Port b9c3941cd61d
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn
Commit 3469a8e03b51bdf3513c533d00206dccb624b102 by springerm
[mlir][linalg][NFC] Factor out tile generation in makeTiledShapes

Factor out the functionality into a new function, so that it can be used for creating PadTensorOp tiles.

Differential Revision: https://reviews.llvm.org/D105458
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
Commit 5da010af9a058a70fc301b9c02d4ff370ab2f9a7 by springerm
[mlir][linalg] Add optional output operand to PadTensorOp

This optional operand will be used for tiling in a subsequent commit.

Differential Revision: https://reviews.llvm.org/D105459
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir
Commit d624c1b50946b206b6274371fcc107f89d04a307 by springerm
[mlir][NFC] Move asOpFoldResult helper functions to StaticValueUtils

Differential Revision: https://reviews.llvm.org/D105602
The file was modifiedmlir/include/mlir/Dialect/Utils/StaticValueUtils.h
The file was modifiedmlir/lib/Dialect/Utils/StaticValueUtils.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
Commit 4064b6a36348a0405a52b690437a1ae3004beec1 by springerm
[mlir][linalg] Tile PadTensorOp

Tiling can be enabled with `linalg-tile-pad-tensor-ops`. Only scf::ForOp can be generated at the moment.

Differential Revision: https://reviews.llvm.org/D105460
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/test/Dialect/Linalg/tile-and-pad-tensors.mlir
The file was addedmlir/test/Dialect/Linalg/tile-pad-tensor-op.mlir
Commit ffb139290d4bf8e46ae88758354bccb647a20f71 by springerm
[mlir][linalg] Fix Windows build

The build failure was introduced by D105458. (Linux builds were not affected.)

Differential Revision: https://reviews.llvm.org/D106029
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
Commit 318ce4ad927d129a2bf96c2c872f4d107c45bdef by springerm
[mlir][linalg] Improve codegen of ExtractSliceOfPadTensorSwapPattern

Generate simpler code in case low/high padding of the PadTensorOp is statically zero.

Differential Revision: https://reviews.llvm.org/D105529
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
The file was modifiedmlir/test/Dialect/Linalg/subtensor-of-padtensor.mlir
Commit a0e02018beb81946397f577f14df09e4b3b675da by springerm
[mlir][linalg] Improve codegen when tiling PadTensor evenly

Produce simpler IR with more static type information and fewer affine expressions.

Differential Revision: https://reviews.llvm.org/D105530
The file was modifiedmlir/test/Dialect/Linalg/tile-pad-tensor-op.mlir
The file was modifiedmlir/test/Dialect/Linalg/tile.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
Commit 70788052ac7ffba3c99b8ce644a3f9bf17eaa4a4 by czhengsz
[PowerPC][NFC] add testcase for update-form preparation with non-const increment
The file was modifiedllvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
Commit 58018858e887320e2432e2e00ace13273b8a1f29 by joker.eph
Defend early against operation created without a registered dialect

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D105961
The file was modifiedmlir/test/CAPI/ir.c
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp
The file was modifiedmlir/lib/IR/Verifier.cpp
The file was modifiedmlir/test/lit.cfg.py
The file was modifiedmlir/test/Dialect/PDL/invalid.mlir
The file was modifiedmlir/test/IR/invalid-module-op.mlir
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
The file was modifiedmlir/lib/Parser/Parser.cpp
The file was modifiedmlir/test/IR/invalid-unregistered.mlir
The file was modifiedmlir/lib/IR/Operation.cpp
The file was modifiedmlir/unittests/Pass/PassManagerTest.cpp
Commit ade190c5eabfb432fa273b354d371f84a312052b by kuterdinel
[Attributor] AACallEdges, Add a way to ask nonasm unknown callees

This patch adds a feature to AACallEdges AbstractAttribute that allows
users to ask if there is a unknown callee that isn't a inline assembly.
This feature is needed by some of it's users.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105992
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
Commit 3e25ea709cf59bdd7f277501ab6737bac5b394f1 by joker.eph
Revert "Defend early against operation created without a registered dialect"

This reverts commit 58018858e887320e2432e2e00ace13273b8a1f29.

The Python bindings test are broken.
The file was modifiedmlir/lib/Parser/Parser.cpp
The file was modifiedmlir/test/lit.cfg.py
The file was modifiedmlir/test/CAPI/ir.c
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp
The file was modifiedmlir/unittests/Pass/PassManagerTest.cpp
The file was modifiedmlir/test/IR/invalid-unregistered.mlir
The file was modifiedmlir/test/IR/invalid-module-op.mlir
The file was modifiedmlir/lib/IR/Verifier.cpp
The file was modifiedmlir/test/Dialect/PDL/invalid.mlir
The file was modifiedmlir/lib/IR/Operation.cpp
Commit 5664c5e24ed42f58175428c5aeb53418b4ff76b0 by john.demme
[MLIR] [Python] Add `owner` to PyValue and fix its parent reference

Adds `owner` python call to `mlir.ir.Value`.

Assuming that `PyValue.parentOperation` is intended to be the value's owner, this fixes the construction of it from `PyOpOperandList`.

Reviewed By: stellaraccident

Differential Revision: https://reviews.llvm.org/D103853
The file was modifiedmlir/lib/Bindings/Python/IRCore.cpp
Commit 0f9e6451a836886f39137818c4f0cfd69ae31e62 by joker.eph
Defend early against operation created without a registered dialect

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D105961
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp
The file was modifiedmlir/test/IR/invalid-unregistered.mlir
The file was modifiedmlir/test/Dialect/PDL/invalid.mlir
The file was modifiedmlir/lib/IR/Verifier.cpp
The file was modifiedmlir/test/CAPI/ir.c
The file was modifiedmlir/test/lit.cfg.py
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
The file was modifiedmlir/unittests/Pass/PassManagerTest.cpp
The file was modifiedmlir/test/IR/invalid-module-op.mlir
The file was modifiedmlir/test/python/dialects/python_test.py
The file was modifiedmlir/lib/IR/Operation.cpp
The file was modifiedmlir/lib/Parser/Parser.cpp