Changes

Summary

  1. [GlobalISel] Add GUnmerge, GMerge, GConcatVectors, GBuildVector abstractions. NFC. (details)
  2. [CMake] Don't LTO optimize targets on Darwin, but only if its not ThinLTO (details)
  3. [CMake] Add LIBXML2_DEFINITIONS when testing for symbol existance (details)
  4. [SimplifyCFG] Add additional if conversion tests (NFC) (details)
  5. Revert D106195 "[dfsan] Add wrappers for v*printf functions" (details)
  6. [InstCombine] Add freezeAllUsesOfArgument to visitFreeze (details)
  7. [llvm] Inline getAssociatedFunction() in LLVM_DEBUG. (details)
  8. [x86] add more tests for add with CMOV of constants; NFC (details)
  9. [DAG] Add initial SelectionDAG::isGuaranteedNotToBeUndefOrPoison framework (PR51129) (details)
  10. [clang][patch] Remove test artifact before running test for consistent results (details)
  11. [mlir] ConversionTarget legality callbacks refactoring (details)
  12. [lld][WebAssembly] Align __heap_base (details)
  13. [AVR] Do not chain stores in call frame setup (details)
  14. [AVR] Set R31R30 as clobbered after ADJCALLSTACKDOWN (details)
  15. [AVR] Improve 8/16 bit atomic operations (details)
  16. [AVR] Expand large shifts early in IR (details)
  17. [AVR] Fix rotate instructions (details)
  18. [AVR] Only support sp, r0 and r1 in llvm.read_register (details)
  19. [gn build] Port 6aa9e746ebde (details)
  20. [CGP] despeculateCountZeros - Don't create is-zero branch if cttz/ctlz source is known non-zero (details)
  21. [SVE][NFC] Cleanup fixed length code gen tests to make them more resilient. (details)
  22. [X86] Add i128 div-mod-pair test coverage (details)
  23. [BasicTTI] Set scalarization cost of scalable vector casts to Invalid. (details)
  24. [mlir] Restore markUnknownOpDynamicallyLegal to call isDynamicallyLegal by default (details)
  25. [X86] Add additional div-mod-pair negative test coverage (details)
  26. [ADT] Remove WrappedPairNodeDataIterator (NFC) (details)
  27. [LICM] Extract debugify test (NFC) (details)
  28. [Tests] Add missing willreturn attributes (NFC) (details)
  29. [Tests] Add additional tests for incorrect willreturn handling (NFC) (details)
  30. [RISCV] Custom lower (i32 (fptoui/fptosi X)). (details)
  31. [mlir] Async: lower SCF operations into CFG inside coroutines (details)
  32. [AArch64][GlobalISel] Widen non-pow-2 types for shifts before clamping. (details)
Commit 5ec0f051c8790653cf4e0f59b8a9048c2dca86e8 by Amara Emerson
[GlobalISel] Add GUnmerge, GMerge, GConcatVectors, GBuildVector abstractions. NFC.

Use these to slightly simplify some code in the artifact combiner.
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
The file was modifiedllvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
Commit 8da3b7d857298a306973ea8f78c35adb5ba89837 by Azharuddin Mohammed
[CMake] Don't LTO optimize targets on Darwin, but only if its not ThinLTO

This is just a workaround. Pass the `-mllvm,-O0` link flags only if its
not ThinLTO. Doing that with ThinLTO currently results in an error:

```
Remaining virtual register operands
UNREACHABLE executed at .../llvm/lib/CodeGen/MachineRegisterInfo.cpp:209!
```
The file was modifiedllvm/cmake/modules/AddLLVM.cmake
Commit ffe32b5c71bfea0009e6d8d1788971d237709672 by markus.boeck02
[CMake] Add LIBXML2_DEFINITIONS when testing for symbol existance

Currently when linking LLVM against Libxml2, a simple check is performed to check whether it can be linked successfully. This check currently adds the include directories and the libraries for libxml2, but not definitions found by the config.

This causes issues on Windows when trying to link against a static libxml2. Libxml2 requires LIBXML_STATIC to be defined in the preprocessor to be able to link statically. This definition is put into LIBXML2_DEFINITIONS in the cmake config, but not properly forwarded to check_symbol_exists leading to it failing as it could not find xmlReadMemory in a DLL.

This patch simply appends the content of LIBXML2_DEFINITIONS to the symbol check definitions, fixing the issue.

Differential Revision: https://reviews.llvm.org/D106740
The file was modifiedllvm/cmake/config-ix.cmake
Commit 9706dd49406b2d318e642b54ae8cab9856b049c5 by nikita.ppv
[SimplifyCFG] Add additional if conversion tests (NFC)

Test a readonly call in between, as well as the combination of
an atomic and simple store.
The file was modifiedllvm/test/Transforms/SimplifyCFG/speculate-store.ll
Commit 228bea6a36cd0eb3b7f80d18bce9f8d5a1a69c95 by gbalats
Revert D106195 "[dfsan] Add wrappers for v*printf functions"

This reverts commit bf281f364757d6af8d9d8456f26d334d1eeaf575.

This commit causes dfsan to segfault.
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt
The file was modifiedcompiler-rt/lib/dfsan/dfsan_custom.cpp
The file was modifiedcompiler-rt/test/dfsan/custom.cpp
Commit aca5aeb7523d7868a4b0706330dcdfc58c0adaed by gusrb406
[InstCombine] Add freezeAllUsesOfArgument to visitFreeze

In D106041, a freeze was added before the branch condition to solve the miscompilation problem of SimpleLoopUnswitch.
However, I found that the added freeze disturbed other optimizations in the following situations.
```
arg.fr = freeze(arg)
use(arg.fr)
...
use(arg)
```
It is a problem that occurred when arg and arg.fr were recognized as different values.
Therefore, changing to use arg.fr instead of arg throughout the function eliminates the above problem.
Thus, I add a function that changes all uses of arg to freeze(arg) to visitFreeze of InstCombine.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D106233
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/test/Transforms/InstCombine/freeze.ll
Commit edb05d555e6a121fc853fbb000b73570af0ea197 by pifon
[llvm] Inline getAssociatedFunction() in LLVM_DEBUG.

Function* F is used only inside LLVM_DEBUG, so that it causes unused
variable warning.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
Commit 937e7c60c8775110dd7e6572b406ef7ce770493e by spatel
[x86] add more tests for add with CMOV of constants; NFC

See D106607 / https://llvm.org/PR51069 for details.
The file was modifiedllvm/test/CodeGen/X86/add-cmov.ll
Commit c261a06b7a98549ab7be858337bb80c9259c2be8 by llvm-dev
[DAG] Add initial SelectionDAG::isGuaranteedNotToBeUndefOrPoison framework (PR51129)

I've setup the basic framework for the isGuaranteedNotToBeUndefOrPoison call and updated DAGCombiner::visitFREEZE to use it, further Opcodes can be handled when we have test coverage.

I'm not aware of any vector test freeze coverage so the DemandedElts (and the Depth) args are not being used yet - but they are in place.

SelectionDAG::isGuaranteedNotToBePoison wrappers have also been added.

Differential Revision: https://reviews.llvm.org/D106668
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAG.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
Commit 05ae3035554aab083ea1ba721284c950cf25d158 by melanie.blower
[clang][patch] Remove test artifact before running test for consistent results

Fix non-deterministic test behavior by removing previously-created
test directory, see comments in D95159
The file was modifiedclang/test/Index/preamble-reparse-changed-module.m
Commit b7a464989955e6374b39b518e317b59b510d4dc5 by ivan.butygin
[mlir] ConversionTarget legality callbacks refactoring

* Get rid of Optional<std::function> as std::function already have a null state
* Add private setLegalityCallback function to set legality callback for unknown ops
* Get rid of unknownOpsDynamicallyLegal flag, use unknownLegalityFn state insted. This causes behavior change when user first calls markUnknownOpDynamicallyLegal with callback and then without but I am not sure is the original behavior was really a 'feature', or just oversignt in the original implementation.

Differential Revision: https://reviews.llvm.org/D105496
The file was modifiedmlir/include/mlir/Transforms/DialectConversion.h
The file was modifiedmlir/lib/Transforms/Utils/DialectConversion.cpp
Commit 13ca0c87edd026813ef7cbf3fbeb0efdb9c8bd3c by aykevanlaethem
[lld][WebAssembly] Align __heap_base

__heap_base was not aligned. In practice, it will often be aligned
simply because it follows the stack, but when the stack is placed at the
beginning (with the --stack-first option), the __heap_base might be
unaligned. It could even be byte-aligned.

At least wasi-libc appears to expect that __heap_base is aligned:
https://github.com/WebAssembly/wasi-libc/blob/659ff414560721b1660a19685110e484a081c3d4/dlmalloc/src/malloc.c#L5224

While WebAssembly itself does not appear to require any alignment for
memory accesses, it is sometimes required when sharing a pointer
externally. For example, WASI might expect alignment up to 8:
https://github.com/WebAssembly/WASI/blob/main/phases/snapshot/docs.md#-timestamp-u64

This issue got introduced with the addition of the --stack-first flag:
https://reviews.llvm.org/D46141
I suspect the lack of alignment wasn't intentional here.

Differential Revision: https://reviews.llvm.org/D106499
The file was addedlld/test/wasm/Inputs/stack-first.s
The file was modifiedlld/test/wasm/stack-first.test
The file was modifiedlld/wasm/Writer.cpp
Commit feda08b70a9bbb55bbdd1b85a83d29f3ed41cf08 by aykevanlaethem
[AVR] Do not chain stores in call frame setup

Previously, AVRTargetLowering::LowerCall attempted to keep stack stores
in order with chains. Perhaps this worked in the past, but it does not
work now: it appears that the SelectionDAG legalization phase removes
these chains. Therefore, I've removed these chains entirely to match
X86 (which, similar to AVR, also prefers to use push instructions over
stack-relative stores to set up a call frame). With this change, all the
stack stores are in a somewhat reasonable order.

Differential Revision: https://reviews.llvm.org/D97853
The file was modifiedllvm/test/CodeGen/AVR/dynalloca.ll
The file was modifiedllvm/lib/Target/AVR/AVRISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AVR/varargs.ll
The file was modifiedllvm/test/CodeGen/AVR/call.ll
Commit 8544ce80f881a33a2c4c8e234709d136b52fa4d8 by aykevanlaethem
[AVR] Set R31R30 as clobbered after ADJCALLSTACKDOWN

In most cases, using R31R30 is fine because the call (which always
precedes ADJCALLSTACKDOWN) will clobber R31R30 anyway. However, in some
rare cases the register allocator might insert an instruction between
the call and the ADJCALLSTACKDOWN instruction and expect the register
pair to be live afterwards. I think this happens as a result of
rematerialization. Therefore, to fix this, the instruction needs to have
Defs set to R31R30.

Setting the Defs field does have the effect of making the instruction
look dead, which it certainly is not. This is fixed by setting
hasSideEffects to true.

Differential Revision: https://reviews.llvm.org/D97745
The file was modifiedllvm/lib/Target/AVR/AVRInstrInfo.td
Commit 431a9414655ba4825a46e6765ef50a0b4ef7e101 by aykevanlaethem
[AVR] Improve 8/16 bit atomic operations

There were some serious issues with atomic operations. This patch should
fix the biggest issues.

For details on the issue take a look at this Compiler Explorer sample:
https://godbolt.org/z/n3ndhn

Code:

    void atomicadd(_Atomic char *val) {
        *val += 5;
    }

Output:

    atomicadd:
        movw    r26, r24
        ldi     r24, 5     ; 'operand' register
        in      r0, 63
        cli
        ld      r24, X     ; load value
        add     r24, r26   ; value += X
        st      X, r24     ; store value back
        out     63, r0
        ret                ; return the wrong value (in r24)

There are various problems with this.

- The value to add (5) is stored in r24. However, the value to add to
   is loaded in the same register: r24.
- The `add` instruction adds half of the pointer to the loaded value,
   instead of (attempting to) add the operand with value 5.
- The output value of the cmpxchg instruction (which is not used in
   this code sample) is the new value with 5 added, not the old value.
   The LangRef specifies that it has to be the old value, before the
   operation.

This patch fixes the first two and leaves the third problem to be fixed
at a later date. I believe atomics were mostly broken before this patch,
with this patch they should become usable as long as you ignore the
output of the atomic operation. In particular it fixes the following
things:

- It sets the earlyclobber flag for the input ('$operand' operand) so
   that the register allocator puts it in a different register than the
   output value.
- It fixes a number of issues with the pseudo op expansion pass, for
   example now it adds the $operand field instead of the pointer. This
   fixes most machine instruction verifier issues (other flagged issues
   are unrelated to atomics).

Differential Revision: https://reviews.llvm.org/D97127
The file was modifiedllvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
The file was modifiedllvm/lib/Target/AVR/AVRInstrInfo.td
Commit 6aa9e746ebde6efd2479fa833d2d816d0a7bb353 by aykevanlaethem
[AVR] Expand large shifts early in IR

This patch makes sure shift instructions such as this one:

    %result = shl i32 %n, %amount

are expanded just before the IR to SelectionDAG conversion to a loop so
that calls to non-existing library functions such as __ashlsi3 are
avoided. The generated code is currently pretty bad but there's a lot of
room for improvement: the shift itself can be done in just four
instructions.

Differential Revision: https://reviews.llvm.org/D96677
The file was modifiedllvm/lib/Target/AVR/CMakeLists.txt
The file was addedllvm/test/CodeGen/AVR/shift-expand.ll
The file was modifiedllvm/lib/Target/AVR/AVR.h
The file was addedllvm/lib/Target/AVR/AVRShiftExpand.cpp
The file was modifiedllvm/lib/Target/AVR/AVRTargetMachine.cpp
Commit 41f905b211fc904d10f819618dcb62f90ba82c45 by aykevanlaethem
[AVR] Fix rotate instructions

This patch fixes some issues with the RORB pseudo instruction.

  - A minor issue in which the instructions were said to use the SREG,
    which is not true.
  - An issue with the BLD instruction, which did not have an output operand.
  - A major issue in which invalid instructions were generated. The fix
    also reduce RORB from 4 to 3 instructions, so it's also a small
    optimization.

These issues were flagged by the machine verifier.

Differential Revision: https://reviews.llvm.org/D96957
The file was modifiedllvm/test/CodeGen/AVR/rot.ll
The file was modifiedllvm/lib/Target/AVR/AVRInstrInfo.td
The file was modifiedllvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
Commit 4d7f5c0a85cde0c144a424059e53079230ec2ea2 by aykevanlaethem
[AVR] Only support sp, r0 and r1 in llvm.read_register

Most other registers are allocatable and therefore cannot be used.

This issue was flagged by the machine verifier, because reading other
registers is considered reading from an undefined register.

Differential Revision: https://reviews.llvm.org/D96969
The file was modifiedllvm/lib/Target/AVR/AVRISelLowering.cpp
The file was addedllvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
The file was removedllvm/test/CodeGen/AVR/intrinsics/read_register.ll
The file was addedllvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
Commit fcb3bb581bdd94e001edfd33eeff2caa609c0f1b by llvmgnsyncbot
[gn build] Port 6aa9e746ebde
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
Commit 478b22d95aee2b818008a7b92b8606175767d0de by llvm-dev
[CGP] despeculateCountZeros - Don't create is-zero branch if cttz/ctlz source is known non-zero

If value tracking can confirm that the cttz/ctlz source is known non-zero then we don't need to create a branch (which DAG will struggle to recover from).

Differential Revision: https://reviews.llvm.org/D106685
The file was modifiedllvm/test/CodeGen/X86/clz.ll
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
Commit e697a542cab39360a578adbf32e0d853a444804c by paul.walker
[SVE][NFC] Cleanup fixed length code gen tests to make them more resilient.

Many of the tests have used NEXT when DAG is more approprite. In
some cases single DAG lines have been used. Note that these are
manual tests because they're to complex for update_llc_test_checks.py
and so it's worth not relying too much on the ordered output.

I've also made the CHECK lines more uniform when it comes to the
ordering of things like LO/HI.
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
Commit 01f20581dd6d59864ca5320b919c9a2e2e20d6c3 by llvm-dev
[X86] Add i128 div-mod-pair test coverage
The file was modifiedllvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
The file was modifiedllvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
Commit c3277a88285e5e40e6d5ee9da7342fae42eaf82e by sander.desmalen
[BasicTTI] Set scalarization cost of scalable vector casts to Invalid.

When BasicTTIImpl::getCastInstrCost can't determine the cost of a
vector cast operation when the types need legalization, it falls
back to calculating scalarization costs. Instead of crashing on
`cast<FixedVectorType>(DstVTy)` when the type is a scalable vector,
return an Invalid cost.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106655
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/test/Analysis/CostModel/AArch64/sve-fptoi.ll
Commit e27c700b9a925b65d19391feee59a50dc39694ea by benny.kra
[mlir] Restore markUnknownOpDynamicallyLegal to call isDynamicallyLegal by default

Looks like an oversight from b7a464989955e6374b39b518e317b59b510d4dc5

This should probably have a test case ...
The file was modifiedmlir/include/mlir/Transforms/DialectConversion.h
Commit f8191ee32b63cfd6499104df7b3bdc2bc3687eec by llvm-dev
[X86] Add additional div-mod-pair negative test coverage

As suggested on D106745
The file was modifiedllvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
The file was modifiedllvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
Commit 4ccfb1076fb7c783ac6fd8d2ae8a6492cdcc42ce by kazu
[ADT] Remove WrappedPairNodeDataIterator (NFC)

The last use was removed on Jul 16, 2020 in commit
f1d4db4f0cdcbfeaee0840bf8a4fb5dc1b9b56fd.
The file was modifiedllvm/include/llvm/ADT/iterator.h
Commit 0339fcc7284d31bb2cb3422a3f300d36d3c2fd05 by nikita.ppv
[LICM] Extract debugify test (NFC)

Only one of the tests in the file wants to check debug info, so
move it into a separate file. This allows update_test_checks to
work.
The file was addedllvm/test/Transforms/LICM/sinking-debugify.ll
The file was modifiedllvm/test/Transforms/LICM/sinking.ll
Commit baa51a0cef57587cfbea4fc437a7968b6daf0290 by nikita.ppv
[Tests] Add missing willreturn attributes (NFC)

To retain the spirit of these tests after an upcoming change
to mayHaveSideEffect(), add willreturn attributes to a number
of functions.
The file was modifiedllvm/test/Transforms/SCCP/calltest.ll
The file was modifiedllvm/test/Transforms/TailCallElim/reorder_load.ll
The file was modifiedllvm/test/Transforms/LICM/sinking.ll
The file was modifiedllvm/test/Transforms/LICM/funclet.ll
The file was modifiedllvm/test/Transforms/SCCP/remove-call-inst.ll
The file was modifiedllvm/test/Transforms/SCCP/musttail-call.ll
Commit c7e69e46c86c3f3785441de45db4b7bc6d26e321 by nikita.ppv
[Tests] Add additional tests for incorrect willreturn handling (NFC)

Highlight a few of the places that don't handle non-willreturn
calls correctly right now.
The file was modifiedllvm/test/Transforms/LICM/sinking.ll
The file was modifiedllvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
The file was modifiedllvm/test/Transforms/SCCP/calltest.ll
Commit c63dbd850182797bc4b76124d08e1c320ab2365d by craig.topper
[RISCV] Custom lower (i32 (fptoui/fptosi X)).

I stumbled onto a case where our (sext_inreg (assertzexti32 (fptoui X)), i32)
isel pattern can cause an fcvt.wu and fcvt.lu to be emitted if
the assertzexti32 has an additional user. If we add a one use check
it would just cause a fcvt.lu followed by a sext.w when only need
a fcvt.wu to satisfy both users.

To mitigate this I've added custom isel and new ISD opcodes for
fcvt.wu. This allows us to keep know it started life as a conversion
to i32 without needing to match multiple nodes. ComputeNumSignBits
has been taught that this new nodes produces 33 sign bits. To
prevent regressions when we need to zero extend the result of an
(i32 (fptoui X)), I've added a DAG combine to convert it to an
(i64 (fptoui X)) before type legalization. In most cases this would
happen in InstCombine, but a zero_extend can be created for function
returns or arguments.

To keep everything consistent I've added new nodes for fptosi as well.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D106346
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rv64d-double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64f-float-convert.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoD.td
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
The file was modifiedllvm/test/CodeGen/RISCV/half-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64f-half-convert.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoF.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
Commit de7a4e53a22b27d47503b9fc513898251319d5c7 by ezhulenev
[mlir] Async: lower SCF operations into CFG inside coroutines

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D106747
The file was modifiedmlir/lib/Dialect/Async/Transforms/CMakeLists.txt
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
The file was modifiedmlir/test/Dialect/Async/async-to-async-runtime.mlir
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
Commit acbc0c5f0ebd8b7ebfa2eb3ae77428eb83c428c5 by Amara Emerson
[AArch64][GlobalISel] Widen non-pow-2 types for shifts before clamping.

For types like s96, we don't want to clamp to s64, we want to first widen to
s128 and then narrow it. Otherwise we end up with impossible to legalize types.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir