Changes

Revert "Remove aarch64-sve-vector-bits-min compile flag from SVE 2 stage bot"

This reverts commit 24c07902d058abcee3bcf908676bacaae1f3d448.

The issue is still present but given that it's not sending out any
new notifications I'm going to leave it as is for now.

It actively building is somewhat useful for those working on
the issue to know what the current status is.

Update config for aosp-O3-polly-before-vectorizer-unprofitable

The bot has moved to a new host with a newer AOSP codebase. Update the
buildbot config to match.

Change-Id: I474f4503078acdf4109ce755228379ae81a39be7

[sanitizer] Run two builds at the time

[NFC][sanitizer] Remove misleading comment

[docs] Update release notes with all LLVM-C API changes

Patch by Mats Larsen. Thanks Mats!

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D106764

[LoopFlatten] Use SCEV and Loop APIs to identify increment and trip count

Replace pattern-matching with existing SCEV and Loop APIs as a more
robust way of identifying the loop increment and trip count. Also
rename 'Limit' as 'TripCount' to be consistent with terminology.

Differential Revision: https://reviews.llvm.org/D106580

[ARM] Implement isLoad/StoreFromStackSlot for MVE stack stores accesses

This implements the isLoadFromStackSlot and isStoreToStackSlot for MVE
MVE_VSTRWU32 and MVE_VLDRWU32 functions. They behave the same as many
other loads/stores, expecting a FI in Op1 and zero offset in Op2. At the
same time this alters VLDR_P0_off and VSTR_P0_off to use the same code
too, as they too should be returning VPR in Op0, take a FI in Op1 and
zero offset in Op2.

Differential Revision: https://reviews.llvm.org/D106797

[RISCV] Add tests showing missed vector saturating add/sub combines

These will be optimized by upcoming patches. The tests are primarily not
being optimized due to the lack of support for saturating vector
arithmetic in the RISC-V backend.

On top of that, however, a large percentage of the scalable-vector tests
are also lacking support in the DAGCombiner: either in
`ISD::matchBinaryPredicate` or due to checks specifically for
`BUILD_VECTOR` and not `SPLAT_VECTOR`.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106649

[AArch64][SME] Add zero instruction

This patch adds the zero instruction for zeroing a list of 64-bit
element ZA tiles. The instruction takes a list of up to eight tiles
ZA0.D-ZA7.D, which must be in order, e.g.

  zero {za0.d,za1.d,za2.d,za3.d,za4.d,za5.d,za6.d,za7.d}
  zero {za1.d,za3.d,za5.d,za7.d}

The assembler also accepts 32-bit, 16-bit and 8-bit element tiles which
are mapped to corresponding 64-bit element tiles in accordance with the
architecturally defined mapping between different element size tiles,
e.g.

  * Zeroing ZA0.B, or the entire array name ZA, is equivalent to zeroing
    all eight 64-bit element tiles ZA0.D to ZA7.D.
  * Zeroing ZA0.S is equivalent to zeroing ZA0.D and ZA4.D.

The preferred disassembly of this instruction uses the shortest list of
tile names that represent the encoded immediate mask, e.g.

  * An immediate which encodes 64-bit element tiles ZA0.D, ZA1.D, ZA4.D and
    ZA5.D is disassembled as {ZA0.S, ZA1.S}.
  * An immediate which encodes 64-bit element tiles ZA0.D, ZA2.D, ZA4.D and
    ZA6.D is disassembled as {ZA0.H}.
  * An all-ones immediate is disassembled as {ZA}.
  * An all-zeros immediate is disassembled as an empty list {}.

This patch adds the MatrixTileList asm operand and related parsing to support
this.

Depends on D105570.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D105575

[clang][tooling] Accept Clang invocations with multiple jobs

When `-fno-integrated-as` is passed to the Clang driver (or set by default by a specific toolchain), it will construct an assembler job in addition to the cc1 job. Similarly, the `-fembed-bitcode` driver  flag will create additional cc1 job that reads LLVM IR file.

The Clang tooling library only cares about the job that reads a source file. Instead of relying on the fact that the client injected `-fsyntax-only` to the driver invocation to get a single `-cc1` invocation that reads the source file, this patch filters out such jobs from `Compilation` automatically and ignores the rest.

This fixes a test failure in `ClangScanDeps/headerwithname.cpp` and `ClangScanDeps/headerwithnamefollowedbyinclude.cpp` on AIX reported here: https://reviews.llvm.org/D103461#2841918 and `clang-scan-deps` failures with `-fembed-bitcode`.

Depends on D106788.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D105695

[clang][tooling] Link clangDriver to ToolingTests

This fixes a build failure introduced in 11ee699b3c812ebe56ce5d3b14ab7ef16c1e8495.

[NFC] Reflow some debug messages.

[RISCV] Add support for vector saturating add/sub operations

This patch adds support for lowering the saturating vector add/sub
intrinsics to RVV instructions, for both fixed-length and
scalable-vector forms alike.

Note that some of the DAG combines are still not triggering for the
scalable-vector tests. These require a bit more work in the DAGCombiner
itself.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106651

[clang-cl] Expose -fmodules and related flags in the driver (PR43391)

I don't know how well this works with clang-cl, but people want to try
it out, and I think we want to make it work, so exposing the flags seems
reasonable.

Differential revision: https://reviews.llvm.org/D106791

Revert "sanitizer_common: split LibIgnore into fast/slow paths"

This reverts commit 1e1f7520279c93a59fa6511028ff40412065985e.

It breaks ignore_noninstrumented_modules=1.
Somehow we did not have any portable tests for this mode before
(only Darwin tests). Add a portable test as well.

Moreover, I think I was too fast uninlining all LibIgnore checks.
For Java, Darwin and OpenMP LibIgnore is always enabled,
so it makes sense to leave it as it was before.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D106855

[clang][tooling] Link LLVMOption to ToolingTests

This fixes a build failure introduced in 11ee699b3c812ebe56ce5d3b14ab7ef16c1e8495.

[SelectionDAG] Support scalable splats in U(ADD|SUB)SAT combines

This patch builds on top of D106575 in which scalable-vector splats were
supported in `ISD::matchBinaryPredicate`. It teaches the DAGCombiner how
to perform a variety of the pre-existing saturating add/sub combines on
scalable-vector types.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106652

[mlir] Fix typo s/applyPermuationMap/applyPermutationMap/

[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder

Differential Revision: https://reviews.llvm.org/D104528

[flang] Fix thinko in CPU_TIME test

We used to test that end > start, but it can well be >= (otherwise the
loop doesn't make sense).

[flang] Fix minor style issues. NFC

[LV] Disable Scalable VFs when tail folding is enabled b/c of low tripcount.

The loop vectorizer may decide to use tail folding when the trip-count
is low. When that happens, scalable VFs are no longer a candidate,
since tail folding/predication is not yet supported for scalable vectors.

This can be re-enabled in a future patch.

Reviewed By: kmclaughlin

Differential Revision: https://reviews.llvm.org/D106657

[lldb][AArch64] Add memory tag writing to lldb-server

This is implemented using the QMemTags packet, as specified
by GDB in:
https://sourceware.org/gdb/current/onlinedocs/gdb/General-Query-Packets.html#General-Query-Packets

(recall that qMemTags was previously added to read tags)

On receipt of a valid packet lldb-server will:
* align the given address and length to granules
  (most of the time lldb will have already done this
  but the specification doesn't guarantee it)
* Repeat the supplied tags as many times as needed to cover
  the range. (if tags > range we just use as many as needed)
* Call ptrace POKEMTETAGS to write the tags.

The ptrace step will loop just like the tag read does,
until all tags are written or we get an error.
Meaning that if ptrace succeeds it could be a partial write.
So we call it again and if we then get an error, return an error to
lldb.

We are not going to attempt to restore tags after a partial
write followed by an error. This matches the behaviour of the
existing memory writes.

The lldb-server tests have been extended to include read and
write in the same test file. With some updated function names
since "qMemTags" vs "QMemTags" isn't very clear when they're
next to each other.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D105180

[X86] Add PR37025 test coverage

[LangRef][NFC] Fix variable name in llvm.maxnum docs

[PowerPC] add more testcases for ld_splat; nfc

[clang/darwin] Pass libclang_rt.profile last on linker command

This reverts the functional change of https://reviews.llvm.org/D35385 because
it sounds like this is no longer necessary
(https://bugs.llvm.org/show_bug.cgi?id=51135#c11) and makes clang's behavior
more uniform across platforms.

Differential Revision: https://reviews.llvm.org/D106733

Convert the error to warning for enabling OMPD in non-Linux platform

OMPD is enabled by default on Linux machines and disabled on others.
However, if explicitly enabled it throws an error and exit while configuring.

It is mentioned in Bug: https://bugs.llvm.org/show_bug.cgi?id=51121

This patch, instead of throwing error, disables OMPD support with a warning message,
so configuration can continue.

Reviewed By: @protze.joachim
Differential Revision: https://reviews.llvm.org/D106682

[lldb] Wait in TestGuiBasicDebug for the interface to open before quitting the welcome screen

Speculative fix for the failing lldb-aarch64-ubuntu bot.

[DebugInfo][LoopStrengthReduction] SCEV-based salvaging for LSR

This patch extends salvaging of debuginfo in the Loop Strength Reduction
(LSR) pass by translating Scalar Evaluations (SCEV) into DIExpressions.
The method is as follows:
- Cache dbg.value intrinsics that are salvageable.
- Obtain a loop Induction Variable (IV) from ScalarExpressionExpander or
  the loop header.
- Translate the IV SCEV into an expression that recovers the current
  loop iteration count. Combine this with the dbg.value's location
  op SCEV to create a DIExpression that salvages the value.

Review by: jmorse

Differential Revision: https://reviews.llvm.org/D105207

[clangd] Use function pointer instead of function_ref to avoid GCC 5 bug

With GCC <6 constructing a function_ref from a free function reference
leads to it referencing a temporary function pointer. If the lifetime of
that temporary is insufficient it can crash.

Fixes https://github.com/clangd/clangd/issues/800

[flang][driver] Make `flang` ignore `-Mfree/-Mfixed`

`-Mfixed` is not supported by the new driver and hence
`flang`, the bash wrapper script, forwards it to the host compiler.
The forwarded options are used by the host compiler when compiling the
unparsed files. As the unparsed source files are always in the free
form, forwarding `-Mfixed` is problematic.

With this patch, `-Mfixed` (and `-Mfree` for consistency) will be
ignored altogether. The user will only see a warning. This is not a
particularly sound approach, but `flang` is only a temporary solution
for us and this workaround is a fair compromise.

Differential Revision: https://reviews.llvm.org/D106428

[clangd] Add platform triple (host & target) to version info

Useful in logs to understand issues around some platforms we don't have much
experience with (e.g. m1, mingw)

Differential Revision: https://reviews.llvm.org/D105681

[DebugInfo][LoopStrengthReduction] SCEV-based salvaging for LSR

This reverts commit 76f3ffb2b285998f02639db8fd42fb0de8a540d0 because
of a failure on sanitixer-X86-64-linux-autoconf.

[DebugInfo][InstrRef] Handle llvm.frameaddress intrinsics gracefully

When working out which instruction defines a value, the
instruction-referencing variable location code has a few special cases for
physical registers:
 * Arguments are never defined by instructions,
 * Constant physical registers always read the same value, are never def'd

This patch adds a third case for the llvm.frameaddress intrinsics: you can
read the framepointer in any block if you so choose, and use it as a
variable location, as shown in the added test.

This rather violates one of the assumptions behind instruction referencing,
that LLVM-ir shouldn't be able to read from an arbitrary register at some
arbitrary point in the program. The solution for now is to just emit a
DBG_PHI that reads the register value: this works, but if we wanted to do
something clever with DBG_PHIs in the future then this would probably get
in the way. As it stands, this patch avoids a crash.

Differential Revision: https://reviews.llvm.org/D106659

[clang][Driver] Expose driver mode detection logic

Also use it in other places that performed it on their own.

Differential Revision: https://reviews.llvm.org/D106789

Revert "Revert "[clangd] Canonicalize compile flags before applying edits""

Set driver mode before parsing arglist.

Depends on D106789.

Differential Revision: https://reviews.llvm.org/D106794

Revert "Revert "[clangd] Adjust compile flags to contain only the requested file as input""

This reverts commit 04e21fbc44c145d5599ef8db9aaf66b159107f33.

[DebugInfo][LoopStrengthReduction] SCEV-based salvaging for LSR

This reapplies commit 76f3ffb2b285998f02639db8fd42fb0de8a540d0 that was
reverted due to buildbot failures.

- Update lit tests with REQUIRES condition.
- Abandon salvage attempt if SCEVUnknown::getValue() returns nullptr.

Differential Revision: https://reviews.llvm.org/D105207

[IVDescriptors] Fix bug in checkOrderedReduction

The Exit instruction passed in for checking if it's an ordered reduction need not be
an FPAdd operation. We need to bail out at that point instead of
assuming it is an FPAdd (and hence has two operands). See added testcase.
It crashes without the patch because the Exit instruction is a phi with
exactly one operand.
This latent bug was exposed by 95346ba which added support for
multi-exit loops for vectorization.

Reviewed-By: kmclaughlin
Differential Revision: https://reviews.llvm.org/D106843

Handle unused variable when assertions are disabled

[libc++] NFC: Try to trigger Docker image rebuild on CI nodes

[clang-repl] Build and install clang-repl by default.

We have the basic infrastructure in place. We can recover from simple errors
(recovering from errors in template instantiations is not yet supported). It
looks like we are in a reasonably functional state for llvm13.

Differential revision: https://reviews.llvm.org/D106813

[DebugInfo][InstrRef] Correctly update DBG_PHIs during instr scheduling

Avoid several crashes when DBG_INSTR_REF and DBG_PHI instructions are fed
to the instruction scheduler. DBG_INSTR_REFs should be treated like
DBG_LABELs, and just ignored for the purpose of scheduling [0].

DBG_PHIs however behave much more like DBG_VALUEs: they refer to register
operands, and if some register defs get shuffled around during instruction
scheduling, there's a risk that the debug instr will refer to the wrong
value. There's already a facility for updating DBG_VALUEs to reflect this;
add DBG_PHI to the list of instructions that it will update.

[0] Suboptimal, but it's what instr scheduling does right now.

Differential Revision: https://reviews.llvm.org/D106663

[lldb][AArch64] Add memory tag writing to lldb

This adds memory tag writing to Process and the
GDB remote code. Supporting work for the
"memory tag write" command. (to follow)

Process WriteMemoryTags is similair to ReadMemoryTags.
It will pack the tags then call DoWriteMemoryTags.
That function will send the QMemTags packet to the gdb-remote.

The QMemTags packet follows the GDB specification in:
https://sourceware.org/gdb/current/onlinedocs/gdb/General-Query-Packets.html#General-Query-Packets

Note that lldb-server will be treating partial writes as
complete failures. So lldb doesn't need to handle the partial
write case in any special way.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D105181

[libc++] [c++2b] [P2166] Prohibit string and string_view construction from nullptr.

* https://wg21.link/P2166

Reviewed By: ldionne, #libc

Differential Revision: https://reviews.llvm.org/D106801

Revert "[X86][AVX] Add getBROADCAST_LOAD helper function. NFCI."

This reverts commit 1cfecf4fc4278afb0005923f6dff595cd372da5c.

This commit broke LLVM code generated through XLA by removing a
conditional on Ld->getExtensionType() == ISD::NON_EXTLOAD

Revert "Revert "[X86][AVX] Add getBROADCAST_LOAD helper function. NFCI.""

This reverts commit d7bbb1230a94cb239aa4a8cb896c45571444675d.

There were follow up uses of a deleted method and I didn't run the
tests. Undo the revert, so I can do it properly.

Revert "[X86][AVX] Add getBROADCAST_LOAD helper function. NFCI."

This reverts commit 1cfecf4fc4278afb0005923f6dff595cd372da5c.

This commit broke LLVM code generated through XLA by removing a
conditional on Ld->getExtensionType() == ISD::NON_EXTLOAD

This is not a perfect revert. The new function is left as other uses of
it exist now.

Strip undef implying attributes when moving calls

When hoisting/moving calls to locations, we strip unknown metadata. Such calls are usually marked `speculatable`, i.e. they are guaranteed to not cause undefined behaviour when run anywhere. So, we should strip attributes that can cause immediate undefined behaviour if those attributes are not valid in the context where the call is moved to.

This patch introduces such an API and uses it in relevant passes. See
updated tests.

Fix for PR50744.

Reviewed By: nikic, jdoerfert, lebedev.ri

Differential Revision: https://reviews.llvm.org/D104641

[SystemZ][z/OS] Initial code to generate assembly files on z/OS

- This patch consists of the bare basic code needed in order to generate some assembly for the z/OS target.
- Only the .text and the .bss sections are added for now.
- The relevant MCSectionGOFF/Symbol interfaces have been added. This enables us to print out the GOFF machine code sections.
- This patch enables us to add simple lit tests wherever possible, and contribute to the testing coverage for the z/OS target
- Further improvements and additions will be made in future patches.

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D106380

Revert "[clang][pp] adds '#pragma include_instead'"

> `#pragma clang include_instead(<header>)` is a pragma that can be used
> by system headers (and only system headers) to indicate to a tool that
> the file containing said pragma is an implementation-detail header and
> should not be directly included by user code.
>
> The library alternative is very messy code that can be seen in the first
> diff of D106124, and we'd rather avoid that with something more
> universal.
>
> This patch takes the first step by warning a user when they include a
> detail header in their code, and suggests alternative headers that the
> user should include instead. Future work will involve adding a fixit to
> automate the process, as well as cleaning up modules diagnostics to not
> suggest said detail headers. Other tools, such as clangd can also take
> advantage of this pragma to add the correct user headers.
>
> Differential Revision: https://reviews.llvm.org/D106394

This caused compiler crashes in Chromium builds involving PCH and an include
directive with macro expansion, when Token::getLiteralData() returned null. See
the code review for details.

This reverts commit e8a64e5491260714c79dab65d1aa73245931d314.

[OpenCL] NULL redefined as nullptr in C++ mode.

Redefines NULL as nullptr instead of ((void*)0)
in C++ for OpenCL.

Such internal representation of NULL provides
compatibility with C++11 and later language
standards.

Patch by Topotuna (Justas Janickas)!

Differential Revision: https://reviews.llvm.org/D105987

Update isl to isl-0.24-69-g54aac5ac

This is needed for having the functions isl_{set,map}_n_basic_{set,map}
exported to the C++ interface.
Some tests have been modified to reflect the isl changes.

[WebAssembly] Codegen for extmul SIMD instructions

Replace the clang builtins and LLVM intrinsics for the SIMD extmul instructions
with normal codegen patterns.

Differential Revision: https://reviews.llvm.org/D106724

AMDGPU: Treat IMPLICIT_DEF like a constant lanemask source

This is partially a workaround. SILowerI1Copies does not understand
unstructured loops. This would result in inserting instructions to
merge a mask register in the same block where it was defined in an
unstructured loop.

[mlir][sparse] fixed bug in verification

The order of testing in two sparse tensor ops was incorrect,
which could cause an invalid cast (crashing the compiler instead
of reporting the error). This revision fixes that bug.

Reviewed By: gussmith23

Differential Revision: https://reviews.llvm.org/D106841

Re-engineer MLIR python build support.

* Implements all of the discussed features:
  - Links against common CAPI libraries that are self contained.
  - Stops using the 'python/' directory at the root for everything, opening the namespace up for multiple projects to embed the MLIR python API.
  - Separates declaration of sources (py and C++) needed to build the extension from building, allowing external projects to build custom assemblies from core parts of the API.
  - Makes the core python API relocatable (i.e. it could be embedded as something like 'npcomp.ir', 'npcomp.dialects', etc). Still a bit more to do to make it truly isolated but the main structural reset is done.
  - When building statically, installed python packages are completely self contained, suitable for direct setup and upload to PyPi, et al.
  - Lets external projects assemble their own CAPI common runtime library that all extensions use. No more possibilities for TypeID issues.
  - Begins modularizing the API so that external projects that just include a piece pay only for what they use.
* I also rolled in a re-organization of the native libraries that matches how I was packaging these out of tree and is a better layering (i.e. all libraries go into a nested _mlir_libs package). There is some further cleanup that I resisted since it would have required source changes that I'd rather do in a followup once everything stabilizes.
* Note that I made a somewhat odd choice in choosing to recompile all extensions for each project they are included into (as opposed to compiling once and just linking). While not leveraged yet, this will let us set definitions controlling the namespacing of the extensions so that they can be made to not conflict across projects (with preprocessor definitions).
* This will be a relatively substantial breaking change for downstreams. I will handle the npcomp migration and will coordinate with the circt folks before landing. We should stage this and make sure it isn't causing problems before landing.
* Fixed a couple of absolute imports that were causing issues.

Differential Revision: https://reviews.llvm.org/D106520

AMDGPU: Update tests for lower i1 change

I forgot to squash the test updates for b32d3d9e81cdd9275d19cd2a396c461edc9e7189

[mlir] Math: add algebraic simplification patterns to math transforms

Reviewed By: bkramer

Differential Revision: https://reviews.llvm.org/D106822

Update reduction test. Remove standalone test file

Based on post commit review comments at 68ffed12b.

[LoopVectorize] Don't interleave scalar ordered reductions for inner loops

Consider the following loop:

  void foo(float *dst, float *src, int N) {
    for (int i = 0; i < N; i++) {
      dst[i] = 0.0;
      for (int j = 0; j < N; j++) {
        dst[i] += src[(i * N) + j];
      }
    }
  }

When we are not building with -Ofast we may attempt to vectorise the
inner loop using ordered reductions instead. In addition we also try
to select an appropriate interleave count for the inner loop. However,
when choosing a VF=1 the inner loop will be scalar and there is existing
code in selectInterleaveCount that limits the interleave count to 2
for reductions due to concerns about increasing the critical path.
For ordered reductions this problem is even worse due to the additional
data dependency, and so I've added code to simply disable interleaving
for scalar ordered reductions for now.

Test added here:

  Transforms/LoopVectorize/AArch64/strict-fadd-vf1.ll

Differential Revision: https://reviews.llvm.org/D106646

Enabling the copy-constant-to-alloca optimization in more instances

Patch by Mohammad Fawaz

This patch allows lifetime calls to be ignored (and later erased) if we
know that the copy-constant-to-alloca optimization is going to happen.
The case that is missed is when the global variable is in a different address
space than the alloca (as shown in the example added to the lit test.)

This used to work before https://github.com/llvm/llvm-project/commit/6da31fa4a61d68af21dfa1e144e726ed6d77903e

Differential Revision: https://reviews.llvm.org/D106573

[AArch64] Update and expand min-max cost model test. NFC

This expands the cost model test for min/max to many more types,
including floating point minnum/maxnum and minimum/maximum, and FP16
with and without fullfp16.  The old llc run lines are removed, as those
are better tested by CodeGen tests.

[clang][fpenv][patch] Change clang option -ffp-model=precise to select ffp-contract=on

Change the ffp-model=precise to enables -ffp-contract=on (previously
-ffp-model=precise enabled -ffp-contract=fast). This is a follow-up
to Andy Kaylor's comments in the llvm-dev discussion "Floating Point
semantic modes". From the same email thread, I put Andy's distillation
of floating point options and floating point modes into UsersManual.rst
Also fixes bugs.llvm.org/show_bug.cgi?id=50222

I had to revert this a few times because of failures on the x86-64
buildbot but I think we finally have that fixed by LNT/79f2b03c51.

Reviewed By: rjmccall, andrew.kaylor

Differential Revision: https://reviews.llvm.org/D74436

[RISCV] Select vector shl by 1 to a vector add.

A vector add may be faster than a vector shift.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D106689

[libc++] CI: Run -std=c++03 on Clang ToT

Differential Revision: https://reviews.llvm.org/D106104

[runtimes] Always build libc++, libc++abi and libunwind with -fPIC

Building the libraries with -fPIC ensures that we can link an executable
against the static libraries with -fPIE. Furthermore, there is apparently
basically no downside to building the libraries with position independent
code, since modern toolchains are sufficiently clever.

This commit enforces that we always build the runtime libraries with -fPIC.
This is another take on D104327, which instead makes the decision of whether
to build with -fPIC or not to the build script that drives the runtimes'
build.

Fixes http://llvm.org/PR43604.

Differential Revision: https://reviews.llvm.org/D104328

[lld/mac] When loading reexports, look for basename in -F / -L first

Matches ld64 (cf Options::findIndirectDylib()), and fixes PR51218.

Differential Revision: https://reviews.llvm.org/D106842

Add jump-threading optimization for deterministic finite automata

The current JumpThreading pass does not jump thread loops since it can
result in irreducible control flow that harms other optimizations. This
prevents switch statements inside a loop from being optimized to use
unconditional branches.

This code pattern occurs in the core_state_transition function of
Coremark. The state machine can be implemented manually with goto
statements resulting in a large runtime improvement, and this transform
makes the switch implementation match the goto version in performance.

This patch specifically targets switch statements inside a loop that
have the opportunity to be threaded. Once it identifies an opportunity,
it creates new paths that branch directly to the correct code block.
For example, the left CFG could be transformed to the right CFG:

```
          sw.bb                        sw.bb
        /   |   \                    /   |   \
   case1  case2  case3          case1  case2  case3
        \   |   /                /       |       \
        latch.bb             latch.2  latch.3  latch.1
         br sw.bb              /         |         \
                           sw.bb.2     sw.bb.3     sw.bb.1
                            br case2    br case3    br case1
```

Co-author: Justin Kreiner @jkreiner
Co-author: Ehsan Amiri @amehsan

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D99205

[Matrix] RAUW should only replace an instruction in ShapeMap if supportsShapeInfo

As an instruction is replaced in optimizeTransposes RAUW will replace it in
the ShapeMap (ShapeMap is ValueMap so that uses are updated).  In
finalizeLowering however we skip updating uses if they are in the ShapeMap
since they will be lowered separately at which point we pick up the lowered
operands.

In the testcase what happened was that since we replaced the doubled-transpose
with the shuffle, it ended up in the ShapeMap.  As we lowered the
columnwise-load the use in the shuffle was not updated.  Then as we removed
the original columnwise-load we changed that to an undef.  I.e. we ended up
with:

```
%shuf = shufflevector <8 x double> undef, <8 x double> poison, <6 x i32>
                                   ^^^^^
                                  <i32 0, i32 1, i32 2, i32 4, i32 5, i32 6>
```

Besides the fix itself, I have fortified this last bit.  As we change uses to
undef when removing instruction we track the undefed instruction to make sure
we eventually remove those too.  This would have caught the issue at compile
time.

Differential Revision: https://reviews.llvm.org/D106714

[Matrix] Fix shape for factored transpose

The shape of the input is C x R.

Differential Revision: https://reviews.llvm.org/D106722

[lld/mac] Fix application-extension.s failure after 8e8701abca3d4

The test accidentally tested something else that makes lld fail
with a different (correct-looking) error that wasn't the one the
test tries to test for. (The test case before this change makes
ld64 hang in an infinite loop.)

[gn build] Port 02077da7e7a8

[dfsan][NFC] Update API interfaces

Reviewed By: gbalats

Differential Revision: https://reviews.llvm.org/D106895

[ASAN] NFC: Remove redundant variable

`StackAlignment` has only one use: `StackAlignment = std::max(StackAlignment, AI.getAlignment());` So it is redundant.

Reviewed By: vitalybuka, MTC

Differential Revision: https://reviews.llvm.org/D106741

[AArch64][GlobalISel] Fix constraining LDXPX intrinsic selection.

Causes a fallback because of lack of regclasses on vregs, unless its without
asserts, where we end up crashing later in codegen.

Add test update for a11d9a1f480f which disables fallbacks.

Remove unused include that's also a layering violation. NFC.

[SystemZ][z/OS][libcxx]: Disable align_val_t test cases on z/OS

align_val_t is not supported on z/OS, it causes failure on z/OS. similar to https://reviews.llvm.org/rGd0fe294729a2ac45625ed45a5619c8405a14db49 , we will need to disable those test cases on z/OS platform.

Differential Revision: https://reviews.llvm.org/D106810

[lld/mac] Fix sub-library.s on Windows after 8e8701abca3d4f0

The endswith() check for the framework name fails when joining
with the native path separator. Always use the posix separator as fix.

[z/OS] Make MinGlobalAlign consistent with SystemZ

Remove overriding MinGlobalAlign to 0 for z/OS target to be consistent with SystemZ.

Reviewed By: abhina.sreeskantharajan

Differential Revision: https://reviews.llvm.org/D106890

[hwasan] Fix stack safety test for old PM.

With the old PM, the stub for __hwasan_generate_tag is still generated
in the IR, but never called.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D106858

AMDGPU/GlobalISel: Add a few tests for unaligned truncating stores

AMDGPU/GlobalISel: Fix wrong addrspace in test MMOs

AMDGPU/GlobalISel: Fix selecting G_SEXTLOAD/G_ZEXTLOAD pre-gfx9

The patterns for the m0 glue patterns were failing to import.

[flang] Disallow BOZ literal constants as output list items

According to C7109, "A boz-literal-constant shall appear only as a
data-stmt-constant in a DATA statement, or where explicitly allowed in
16.9 as an actual argument of an intrinsic procedure."  This change
enforces that constraint for output list items.

I also added a general interface to determine if an expression is a BOZ
literal constant and changed all of the places I could find where it
could be used.

I also added a test.

This change stemmed from the following issue --
  https://gitlab-master.nvidia.com/fortran/f18-stage/issues/108

Differential Revision: https://reviews.llvm.org/D106893

[libclang] Check LLVM_HAVE_LINK_VERSION_SCRIPT

There are some platform that might not have version script support,
don't try to use version script on those.

Reviewed By: MaskRay, hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D106914

[mlir][bzl] Fix typo

[libc++] Disable incomplete library features.

Adds a new CMake option to disable the usage of incomplete headers.
These incomplete headers are not guaranteed to be ABI stable. This
option is intended to be used by vendors so they can avoid their users
from code that's not ready for production usage.

The option is enabled by default.

Differential Revision: https://reviews.llvm.org/D106763

Fix "break delete --disabled" with no arguments.

The code that figured out which breakpoints to delete was supposed
to set the result status if it found breakpoints, and then the code
that actually deleted them checked that the result's status was set.

The code for "break delete --disabled" failed to set the status if
no "protected" breakpoints were provided.  This was a confusing way
to implement this, so I reworked it with early returns so it was less
error prone, and added a test case for the no arguments case.

Differential Revision: https://reviews.llvm.org/D106623

When calculating the "currently selected thread" in
Process::HandleStateChangedEvent, we check whether a thread stopped
for eStopReasonSignal is stopped for a signal that's currently set to
"no-stop". If it is, then we don't set that thread as the currently
selected thread.

But that only happens in the part of the algorithm that's handling the
case where the previously selected thread has no stop reason. Since we
want to keep on a thread as long as it is doing something interesting,
we always prefer the current thread. That's almost right, but we
forgot to check whether the previously selected thread stopped with an
eStopReasonSignal for a "no-stop" signal. If it did, then we shouldn't
select it.

This patch adds that check. I can't figure out a good way to test
this. This is the sort of thing that Ismail's scripted process plugin
will make easy once it is a real boy. But figuring out how to do this
in a real process is not trivial.

Differential Revision: https://reviews.llvm.org/D106712

Add a test for top-level expressions using "expr --top-level".

This was broken for a while even though the Python version
continued to work.  This adds a test so it doesn't regress.

[libc] Enable MPFR library for math functions test

Included more math functions to Windows's entrypoints
and made a cmake option (-DLLVM_LIBC_MPFR_INSTALL_PATH)
where the user can specify the install path where the MPFR
library was built so it can be linked. The try_compile was
moved to LLVMLibCCheckMPFR.cmake, so the variable that is
set after this process can retain its value in other files
of the same parent file. A direct reason for this is for
LIBC_TESTS_CAN_USE_MPFR to be true when the user specifies
MPFR's path and retain its value even after leaving the file.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D106894

[PDL] Remove RewriteEndOp and mark RewriteOp as NoTerminator

RewriteEndOp was a fake terminator operation that is no longer needed now that blocks are not required to have terminators.

Differential Revision: https://reviews.llvm.org/D106911

[mlir] Add a FailureOr copy constructor from a FailureOr of a convertible type.

[x86] add more tests for cmov and lea; NFC

[x86] update stale code comment; NFC

The transform was generalized with:
1ce05ad619a5

[PowerPC] Turn deprecated altivec prefetch instrs to nops on AIX

The dst/dstt/dstst/dststt instructions are nop's on all PowerPC
cores that AIX supports. The AIX assembler also does not accept
these mnemonics. Turn them into nop's on AIX (similar to dstall).

[libc] Fix x86_64 fenv implementation for windows

All fenv functions are also enabled for windows. Since two tests,
enabled_exceptions_test and feholdexcept_test are still failing on
windows, they have been disabled.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D106808

[dfsan][NFC] Describe how origin trace tracking works

Reviewed By: gbalats

Differential Revision: https://reviews.llvm.org/D106903

[OpenMP] Creating the `omp_target_num_teams` and `omp_target_thread_limit` attributes to outlined functions

The device runtime contains several calls to __kmpc_get_hardware_num_threads_in_block
and __kmpc_get_hardware_num_blocks. If the thread_limit and the num_teams are constant,
these calls can be folded to the constant value.

In commit D106033 we have the optimization phase. This commit adds the attributes to
the outlined function for the grid size. the two attributes are `omp_target_num_teams` and
`omp_target_thread_limit`. These values are added as long as they are constant.

Two functions are created `getNumThreadsExprForTargetDirective` and
`getNumTeamsExprForTargetDirective`. The original functions `emitNumTeamsForTargetDirective`
 and `emitNumThreadsForTargetDirective` identify the expresion and emit the code.
However, for the Device version of the outlined function, we cannot emit anything.
Therefore, this is a first attempt to separate emision of code from deduction of the
values.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106298

[lldb][NFC] Fix incorrect log and comment

Likely copy & paste issue that was overlooked years ago

[libc] Fix strtok_r crash when src and *saveptr are both nullptr

While working and testing my refactoring of multiple string functions in libc, I came across a bug that needs to be addressed in a patch on its own: src is checked for nullptr and assigned to *saveptr if it is nullptr. However, saveptr is initially nullptr when it comes to reentry. This could cause a problem if both saveptr and src are null; we need to do the check first and return nullptr if both are nullptr.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D106885

[OpenMP] Fix deadlock for detachable task with child tasks

This patch fixes https://bugs.llvm.org/show_bug.cgi?id=49066.

For detachable tasks, the assumption breaks that the proxy task cannot have
remaining child tasks when the proxy completes.
In stead of increment/decrement the incomplete task count, a high-order bit
is flipped to mark and wait for the incomplete proxy task.

Differential Revision: https://reviews.llvm.org/D101082

[NFC][MLGO] Debug messages for what inline advisor is selected

We already have an indication (error) if the desired inline advisor
cannot be enabled, but we don't have a positive indication. Added
LLVM_DEBUG messages for the latter.

[OpenMP][Tests] Fix test compatibility

gcc and clang disagree in how the event handle needs to be handled.
According to OpenMP LC, gcc is right. Will open clang bug report

[MLGO] fix silly LLVM_DEBUG misuse

[AIX] Update fetch_and_add type

It turns out that the AIX kernel is defining int instead of unsigned int for fetch_and_add.

Legacy XL also defines this to be signed.

https://www.ibm.com/docs/en/aix/7.2?topic=f-fetch-add-kernel-services

So update the type for compat.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D106920

[Libomptarget] Revert new variable sharing to use the old method

The new method of sharing variables introduces a `__kmpc_alloc_shared` call
that cannot be removed in the middle end because of its non-constant argument
and unconnected free. This patch reverts this to the old method that used a
static amount of shared memory for sharing variables.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106905

[gn build] manually port 71909de37495

[lld][ELF] remove empty SyntheticSections from inputSections

Change removeUnusedSyntheticSections() to actually remove empty
SyntheticSections in inputSections.

In addition to doing what removeUnusedSyntheticSections() was meant
to do, this will also make the shuffle-sections tests, which shuffles
inputSections, less sensitive to empty Synthetic Sections that
will not appear in the final image.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D106427

Change-Id: I589eaf596472161a4395fb658aea0fad73318088

Fix test/Transforms/LoopVectorize/AArch64/strict-fadd-vf1.ll.

It was writing to the source directory (which may not be writeable),
rather than using %t.

Fixes: a5dd6c6cf935 ("[LoopVectorize] Don't interleave scalar ordered reductions for inner loops")

[compiler-rt][hwasan][Fuchsia] Do not emit FindDynamicShadowStart for Fuchsia

This function is unused because fuchsia does not support a dynamic shadow.

Differential Revision: https://reviews.llvm.org/D105735

[libcxx][nfc] Delete `cpp20_input_iterator`'s default constructor.

This will make it conform only to the minimum requirements for an `input_iterator`.

[libcxx][ranges] Add `counted_iterator`.

Differential Revision: https://reviews.llvm.org/D106205

[Attributor] Disable simplification AAs if a callback is present

AAValueSimplify, AAValueConstantRange, and AAPotentialValues all look at
the IR by default. If queried for a IR position which has a
simplification callback we should either look at the callback return, or
give up. We do the latter for now.

[OpenMP] Improve alignment handling in the new device runtime

[Attributor] Verify `checkForAllUses` return value properly

Also do not emit more than one remark after Heap2Stack failed.

Revert "[Attributor] Disable simplification AAs if a callback is present"

This reverts commit cbb709e25124dc38ee593882051fc88c987fe591 as it
breaks the tests, which was not supposed to happen. Investigating now.

[gn build] Port 8a48e6dda9f7

Revert "[ELF] --gc-sections: allow GC on reserved sections in a group"

clang may place dynamic initializations for explicitly specialized class
template static data members in comdat.
Such in-comdat SHT_INIT_ARRAY was an abuse but we have to work around it for a while.

[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs

This fixes https://llvm.org/PR51229.

Create synthetic symbol names on demand to improve memory consumption and startup times.

This is a resubmission of https://reviews.llvm.org/D105160 after fixing testing issues.

This fix was created after profiling the target creation of a large C/C++/ObjC application that contained almost 4,000,000 redacted symbol names. The symbol table parsing code was creating names for each of these synthetic symbols and adding them to the name indexes. The code was also adding the object file basename to the end of the symbol name which doesn't allow symbols from different shared libraries to share the names in the constant string pool.

Prior to this fix this was creating 180MB of "___lldb_unnamed_symbol" symbol names and was taking a long time to generate each name, add them to the string pool and then add each of these names to the name index.

This patch fixes the issue by:

not adding a name to synthetic symbols at creation time, and allows name to be dynamically generated when accessed
doesn't add synthetic symbol names to the name indexes, but catches this special case as name lookup time. Users won't typically set breakpoints or lookup these synthetic names, but support was added to do the lookup in case it does happen
removes the object file baseanme from the generated names to allow the names to be shared in the constant string pool
Prior to this fix the startup times for a large application was:
12.5 seconds (cold file caches)
8.5 seconds (warm file caches)

After this fix:
9.7 seconds (cold file caches)
5.7 seconds (warm file caches)

The names of the symbols are auto generated by appending the symbol's UserID to the end of the "___lldb_unnamed_symbol" string and is only done when the name is requested from a synthetic symbol if it has no name.

Differential Revision: https://reviews.llvm.org/D106837

[PDL] Fix the builders for OperationOp and PatternOp

[PDL] Mark PatternOp as SingleBlock

This provides access to the SingleBlock accessor methods, e.g. getBody().

[X86] Fix lowering to illegal type in LowerINSERT_VECTOR_ELT

[libc++] Fix a few warnings in system headers with GCC

This isn't fixing all of them, but at least it's making some progress.

Differential Revision: https://reviews.llvm.org/D106283

Add llvm::equal convenient wrapper for ranges around std::equal

Differential Revision: https://reviews.llvm.org/D106913

Revert "[X86] Fix lowering to illegal type in LowerINSERT_VECTOR_ELT"

This reverts commit 6ff73efea94621e74642e4d7a15cc86a5fb6d411.

Reapply "[Attributor] Disable simplification AAs if a callback is present""

This reapplies commit cbb709e25124dc38ee593882051fc88c987fe591 and
includes the use of the lookup method instead of operator[] to avoid
accidentally setting (empty) simplification callbacks.

This reverts commit aa27430a625b2fd059707a87f8ba2df8f480ff11.

[X86] Fix lowering to illegal type in LowerINSERT_VECTOR_ELT

Differential Revision: https://reviews.llvm.org/D106780

Precommit test files for D105344 (NFC)

[DAGCombiner] Fold SETCC(FREEZE(x),const) to FREEZE(SETCC(x,const)) if SETCC is used by BRCOND

This patch adds a peephole optimization `SETCC(FREEZE(x),const)` => `FREEZE(SETCC(x,const))`
if the SETCC is only used by BRCOND.

Combined with `BRCOND(FREEZE(X)) => BRCOND(X)`, this leads to a nice improvement in the generated assembly when x is a masked loaded value.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D105344

llvm/utils: guarantee revert_checker's revert ordering

At the moment, the revert ordering from this tool is unspecified (though
it happens to be in `git log` order, so newest reverts come first).

From the standpoint of tooling and users, this seems to be the opposite
of what we want by default: tools and users will generally try to apply
these reverts as cherry-picks. If two reverts in the list are close
enough to each other, if the reverts get applied out of order, we'll get
a merge conflict.

Rather than having `reverse`s for all tools (and mental reverses for
manual users), just guarantee an oldest-first output ordering for this
function.

Differential Revision: https://reviews.llvm.org/D106838

[clang] NFC: change uses of `Expr->getValueKind` into `is?Value`

Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>

Reviewed By: rsmith

Differential Revision: https://reviews.llvm.org/D100733

[OpenMP] Folding threadLimit and numThreads when single value in kernels

The device runtime contains several calls to `__kmpc_get_hardware_num_threads_in_block`
and `__kmpc_get_hardware_num_blocks`. If the thread_limit and the num_teams are constant,
these calls can be folded to the constant value.

In this patch we use the already introduced `AAFoldRuntimeCall` and the `NumTeams` and
`NumThreads` kernel attributes (to be introduced in a different patch) to fold these functions.
The code checks all the kernels, and if their attributes match, the functions are folded.

In the future we will explore specializing for multiple values of NumThreads and NumTeams.

Depends on D106390

Reviewed By: jdoerfert, JonChesterfield

Differential Revision: https://reviews.llvm.org/D106033

[OpenMP][Libomptarget] Adding `print_device_info` to RTL and `omptarget`

This patch introduces a function in the device's plugin to print the
device information. This patch relates to another patch that introduces
a CLI tool to obtain the device information from the omplibrary directly.
It is inspired by PGI's pgaccelinfo.

The modifications are as follows:
1. Introduce the optional `void __tgt_rtl_print_device_info(RTLdevID)` function into the RTL.
2. Introduce the `bool __tgt_print_device_info(devID)` function into `omptarget` interface. Returns false if the RTL is not implemented
3. Added `bool printDeviceInfo(RTLDevID)` to the `DeviceTy`
4. Implement the `__tgt_rtl_print_device_info` for CUDA. Added additional CUDA Runtime calls.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106751

[lld] Replace LLVM_ATTRIBUTE_NORETURN with [[noreturn]]

[[noreturn]] can be used since 2016 when the minimum compiler requirement was bumped to GCC 4.8/MSVC 2015.

[mlir] Replace LLVM_ATTRIBUTE_NORETURN with C++11 [[noreturn]]

[[noreturn]] can be used since 2016 when the minimum compiler requirement was bumped to GCC 4.8/MSVC 2015.

Fix a thinko in the parsing of substitutions in CommandObjectRegexCommand.

The old code incorrectly calculated the start position for the search
for the third (and subsequent) instance of a particular substitution
pattern (e.g. %1).

I also added a few test cases for this parsing covering this failure.

[mlir][openacc] Initial translation for DataOp to LLVM IR

Add basic translation of acc.data to LLVM IR with runtime calls.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D104301

[OpenMP][Tool] Introducing the `llvm-omp-device-info` tool

This patch introduces the `llvm-omp-device-info` tool, which uses the
omptarget library and interface to query the device info from all the
available devices as seen by OpenMP. This is inspired by PGI's `pgaccelinfo`

Since omptarget usually requires a description structure with executable
kernels, I split the initialization of the RTLs and Devices to be able to
initialize all possible devices and query each of them.

This revision relies on the patch that introduces the print device info.

A limitation is that the order in which the devices are initialized, and the
corresponding device ID is not necesarily the one seen by OpenMP.

The changes are as follows:
1. Separate the RTL initialization that was performed in `RegisterLib` to its own `initRTLonce` function
2. Create an `initAllRTLs` method that initializes all available RTLs at runtime
3. Created the `llvm-deviceinfo.cpp` tool that uses `omptarget` to query each device and prints its information.

Example Output:
```
Device (0):
    print_device_info not implemented

Device (1):
    print_device_info not implemented

Device (2):
    print_device_info not implemented

Device (3):
    print_device_info not implemented

Device (4):
    CUDA Driver Version:                11000
    CUDA Device Number:                 0
    Device Name:                        Quadro P1000
    Global Memory Size:                 4236312576 bytes
    Number of Multiprocessors:          5
    Concurrent Copy and Execution:      Yes
    Total Constant Memory:              65536 bytes
    Max Shared Memory per Block:        49152 bytes
    Registers per Block:                65536
    Warp Size:                          32 Threads
    Maximum Threads per Block:          1024
    Maximum Block Dimensions:           1024, 1024, 64
    Maximum Grid Dimensions:            2147483647 x 65535 x 65535
    Maximum Memory Pitch:               2147483647 bytes
    Texture Alignment:                  512 bytes
    Clock Rate:                         1480500 kHz
    Execution Timeout:                  Yes
    Integrated Device:                  No
    Can Map Host Memory:                Yes
    Compute Mode:                       DEFAULT
    Concurrent Kernels:                 Yes
    ECC Enabled:                        No
    Memory Clock Rate:                  2505000 kHz
    Memory Bus Width:                   128 bits
    L2 Cache Size:                      1048576 bytes
    Max Threads Per SMP:                2048
    Async Engines:                      Yes (2)
    Unified Addressing:                 Yes
    Managed Memory:                     Yes
    Concurrent Managed Memory:          Yes
    Preemption Supported:               Yes
    Cooperative Launch:                 Yes
    Multi-Device Boars:                 No
    Compute Capabilities:               61
```

Reviewed By: tianshilei1992

Differential Revision: https://reviews.llvm.org/D106752

[OpenMP] Fixing missing variables when CUDA SDK not in system

This patch fixes the error reported in D106751. When there is no CUDA SDK
installed in the system, the build fails due to missing `CU_DEVICE_ATTRIBUTE`
variables.

Using @zsrkmyn sugested fix

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106933

Revert "Remove aarch64-sve-vector-bits-min compile flag from SVE 2 stage bot"

This reverts commit 24c07902d058abcee3bcf908676bacaae1f3d448.

The issue is still present but given that it's not sending out any
new notifications I'm going to leave it as is for now.

It actively building is somewhat useful for those working on
the issue to know what the current status is.

Update config for aosp-O3-polly-before-vectorizer-unprofitable

The bot has moved to a new host with a newer AOSP codebase. Update the
buildbot config to match.

Change-Id: I474f4503078acdf4109ce755228379ae81a39be7

[sanitizer] Run two builds at the time

[NFC][sanitizer] Remove misleading comment