Started 3 mo 20 days ago
Took 1 hr 34 min

Build #1994 (Oct 3, 2021 10:01:34 PM)

Changes
  1. Add more MLIR builders and refactor slightly the config (details / githubweb)
  2. Disable LLD for the clang-5 build: it suffers from http://llvm.org/pr49915 (details / githubweb)
Changes
  1. Fix last leaky MLIR integration test (NFC) (details)
  2. Exclude MLIR python binding tests from Sanitizer tests for now (details)
  3. Fix ASAN execution for the MLIR Python tests (details)
  4. [mlir] [test] Include mlir_tools_dir in PATH to fix mlir-reduce (details)
  5. [NFC][RISCV] Update test cases through update_cc_test_checks.py. (details)
  6. [LSV] Change the default value of InstertElement to poison (details)
  7. [Clang] Extend -Wbool-operation to warn about bitwise and of bools with side effects (details)
  8. Revert "[Clang] Extend -Wbool-operation to warn about bitwise and of bools with side effects" (details)
  9. Fixed warnings in LLVM produced by -Wbitwise-instead-of-logical (details)
  10. Reland "[Clang] Extend -Wbool-operation to warn about bitwise and of bools with side effects" (details)
  11. [clang-format] allow clang-format to be passed a file of filenames so we can add a regression suite of "clean clang-formatted files" from LLVM (details)
  12. Unbreak hexagon-check-builtins.c due to rGb1fcca388441 (details)
  13. [X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests (details)
  14. [NFC][X86][LV] Add costmodel test coverage for interleaved i8 load/store stride=6 (details)
  15. [NFC][X86][Codegen] Add test coverage for interleaved i8 load/store stride=6 (details)
  16. Fixed more warnings in LLVM produced by -Wbitwise-instead-of-logical (details)
  17. Fixed warnings in target/parser codes produced by -Wbitwise-instead-of-logicala (details)
  18. [NFC][X86][LV] Add costmodel test coverage for interleaved i32/f32 load/store stride=3 (details)
  19. [NFC][X86][Codegen] Add test coverage for interleaved i32 load/store stride=3 (details)
  20. [InstSimplify] Add additional load from constant test (NFC) (details)
  21. [InstCombine] add test for shl + demanded bits; NFC (details)
  22. [InstCombine] fold cast of right-shift if high bits are not demanded (3rd try) (details)
  23. [NFC][X86][LV] Add costmodel test coverage for interleaved i64/f64 load/store stride=3 (details)
  24. [NFC][X86][Codegen] Add test coverage for interleaved i64 load/store stride=3 (details)
  25. [Analysis, CodeGen] Migrate from arg_operands to args (NFC) (details)
  26. [ARM] Tests for constant hoisting -1 immediates (details)
  27. [CostModel][X86] X86TTIImpl::getCmpSelInstrCost - try to use Predicate argument directly first (PR48337) (details)
  28. [X86] Split Cannonlake + Icelake Tuning. NFC (details)
  29. [ARM] Mark <= -1 immediate constant as cheap (details)
  30. [mlir] [test] Add missing tool substitutions (details)
  31. [Clang][NFC] Fix the comment for Sema::DiagIfReachable (details)
  32. [X86][Costmodel] Load/store i8 Stride=6 VF=2 interleaving costs (details)
  33. [X86][Costmodel] Load/store i8 Stride=6 VF=4 interleaving costs (details)
  34. [X86][Costmodel] Load/store i8 Stride=6 VF=8 interleaving costs (details)
  35. [X86][Costmodel] Load/store i8 Stride=6 VF=16 interleaving costs (details)
  36. [X86][Costmodel] Load/store i8 Stride=6 VF=32 interleaving costs (details)
  37. [X86][Costmodel] Load/store i16 Stride=3 VF=2 interleaving costs (details)
  38. [X86][Costmodel] Load/store i16 Stride=3 VF=4 interleaving costs (details)
  39. [X86][Costmodel] Load/store i16 Stride=3 VF=8 interleaving costs (details)
  40. [X86][Costmodel] Load/store i16 Stride=3 VF=16 interleaving costs (details)
  41. [X86][Costmodel] Load/store i16 Stride=3 VF=32 interleaving costs (details)
  42. [openmp] Fix a typo in a test REQUIRES line (details)
  43. [AttrBuilder] Make handling of int attribtues more generifc (NFC) (details)
  44. [SCEV] Correctly propagate nowrap flags across scopes when folding invariant add through addrec (details)
  45. [SCEV] Use full logic when infering flags on add and gep (details)
  46. [SCEV] Use trivial bound on defining scope of all SCEVs when computing flags (details)
  47. [SCEV] Cap the number of instructions scanned when infering flags (details)
Changes
  1. Add more MLIR builders and refactor slightly the config (details)
  2. Disable LLD for the clang-5 build: it suffers from http://llvm.org/pr49915 (details)

Started by timer

This run spent:

  • 7 ms waiting;
  • 1 hr 34 min build duration;
  • 1 hr 34 min total from scheduled to completion.
Revision: fd469b915c51bb30fc0ce212c0afa882df229810
Repository: https://github.com/llvm/llvm-zorg.git
  • refs/remotes/origin/main
Revision: 5f7a5353301b776ffb0e5fb048992898507bf7ee
Repository: http://labmaster3.local/git/llvm-project.git
  • refs/remotes/origin/main
Revision: fd469b915c51bb30fc0ce212c0afa882df229810
Repository: http://labmaster3.local/git/llvm-zorg.git
  • refs/remotes/origin/main
Test Result (no failures)