Changes

[llvm-profgen] Skip duplication factor outside of body sample computation

We incorrectly use duplication factor for total samples even though we already accumulate samples instead of taking MAX. It causes profile to have bloated total samples for functions with loop unrolled or vectorized. The change fix the issue for total sample, head sample and call target samples.

Differential Revision: https://reviews.llvm.org/D112042

[NARY-REASSOCIATE] Fix infinite recursion optimizing min\max

To guarantee convergence of the algorithm each optimization step should decrease number of instructions when IR is modified. This property is not held in this test case. The problem is that SCEV Expander may do "unexpected" reassociation what results in creation of new min/max chains and introduction of extra instructions. As a result on each step we indefinitely optimize back and forth.

The solution is to restrict SCEV Expander to perform uncontrolled reassociations by means of "Unknown" expressions.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D112060

[CSKY] Complete to add basic integer instruction set

Complete the basic integer instruction set and add related predictor in CSKY.td.
And it includes the instruction definition and asm parser support.

Differential Revision: https://reviews.llvm.org/D111701

[Flang][flang-omp-report] Switch from std::string to StringRef (where possible)

This patch makes the following changes to flang-omp-report:
 - Update 'normalize_clause_name' parameter to use llvm::StringRef instead of
   std::sting.
 - Change usages of std::tolower to llvm::toLower from
   "ADT/StringExtras.h".
This is a one of several patches focusing on switching containers from STL to LLVM's ADT library.

Reviewed By: Leporacanthicus, clementval

Differential Revision: https://reviews.llvm.org/D111980

[flang] flang-omp-report replace std::map with llvm::DenseMap

This patch replaces the uses of std::map with llvm::DenseMap in the
flang-omp-report plugin. It also removed the 'constructClauseCount' map
due to no longer being needed after the plugin was stripped down.
This is a one of several patches focusing on switching containers from STL to LLVM's ADT library.

Reviewed By: kiranchandramohan, clementval

Differential Revision: https://reviews.llvm.org/D111977

[clang-format] git-clang-format throws an assertion when removing files as part of the commit

Following a change {D111273} to allow git-clang-format to see single lines being removed,
we introduced a regression such that if you are removing a whole file it will
assert in clang-format as its given the -lines=0:0  (lines are 1 based)

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D112056

[clang-format] [PR52015] clang-format should put __attribute__((foo)) on its own line before @interface / @implementation / @protocol

https://bugs.llvm.org/show_bug.cgi?id=52015

A newline should be place between attribute and @ for objectivec

Reviewed By: benhamilton, HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D111975

[WebAssembly] Implementation of table.get/set for reftypes in LLVM IR

This change implements new DAG nodes TABLE_GET/TABLE_SET, and lowering
methods for load and stores of reference types from IR arrays. These
global LLVM IR arrays represent tables at the Wasm level.

Differential Revision: https://reviews.llvm.org/D111154

[AArch64] Improve div and rem costmodel tests. NFC

Copied from the X86 tests, these give a better test coveraged than the
existing tests.

[SPARC] Recognize the prefetch instruction

Reviewed By: LemonBoy

Differential Revision: https://reviews.llvm.org/D96311

[AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions.

autiasp, autibsp instructions are the counterpart of paciasp/pacibsp instructions
therefore let's emit .cfi_negate_ra_state for these too.
In case of Armv8.3 instruction set the retaa/retbb will do the return and authentication
in one step here we can't emit the . cfi_negate_ra_state because that would be point after
the ret* instruction.

Reviewed By: nickdesaulniers, MaskRay

Differential Revision: https://reviews.llvm.org/D111780

[lldb/DWARF] Ignore debug info pointing to the low addresses

specifically, ignore addresses that point before the first code section.

This resurrects D87172 with several notable changes:
- it fixes a bug where the early exits in InitializeObject left
  m_first_code_address "initialized" to LLDB_INVALID_ADDRESS (0xfff..f),
  which caused _everything_ to be ignored.
- it extends the line table fix to function parsing as well, where it
  replaces a similar check which was checking the executable permissions
  of the section. This was insufficient because some
  position-independent elf executables can have an executable segment
  mapped at file address zero. (What makes this fix different is that it
  checks for the executable-ness of the sections contained within that
  segment, and those will not be at address zero.)
- It uses a different test case, with an elf file with near-zero
  addresses, and checks for both line table and function parsing.

Differential Revision: https://reviews.llvm.org/D112058

[docs] Fix hyperlink

[lldb/test] Remove quote/unquote steps from the make invocations

None of the commands we run really rely on shell features. Running them
with shell=False, simplifies the code as there is no need for elaborate
quoting.

Differential Revision: https://reviews.llvm.org/D111990

[lldb] Improve assert message in TestCPPAccelerator

`log` is just some IO object that gets printed as `<_io.TextIOWrapper = filename`
but the intention here was to print the actual found log contents.

[X86] Remove X86ProcFamilyEnum::IntelSLM

Replace X86ProcFamilyEnum::IntelSLM enum with a TuningUseSLMArithCosts flag instead, matching what we already do for Goldmont.

This just leaves X86ProcFamilyEnum::IntelAtom to replace with general Tuning/Feature flags and we can finally get rid of the old X86ProcFamilyEnum enum.

Differential Revision: https://reviews.llvm.org/D112079

[lldb] [Process/Utility] Define qN regs on ARM via helper macro

Add a FPU_QREG macro to define qN registers.  This is a piece-wise
attempt of reconstructing D112066 with the goal of figuring out which
part of the larger change breaks the buildbot.

Differential Revision: https://reviews.llvm.org/D112066

consteval if does not form a discarded statement

When we added support for if consteval, we accidentally formed a discarded
statement evaluation context for the branch-not-taken. However, a discarded
statement is a property of an if constexpr statement, not an if consteval
statement (https://eel.is/c++draft/stmt.if#2.sentence-2). This turned out to
cause issues when deducing the return type from a function with a consteval if
statement -- we wouldn't consider the branch-not-taken when deducing the return
type.

This fixes PR52206.

Note, there is additional work left to be done. We need to track discarded
statement and immediate evaluation contexts separately rather than as being
mutually exclusive.

[CostModel][X86] Add costs for multiply-by-pow2 constants

These are folded to left shifts in the backend.

We should be able to extend this for multiply-by-negpow2 after D111968 has landed to resolve PR51436

[SLP][X86] Improve SLP tests for division/multiplication by +/- pow2

Add PR51436 test as well as some basic multiply tests, and include SSE2 division coverage

[libunwind] Use the from-scratch testing configuration by default

This commit switches libunwind from using the complicated logic in
libc++'s testing configuration to a from-scratch configuration.
I tried to make sure that all cases that were handled in the old
config were handled by this one too, so hopefully this shouldn't
break anyone. However, if you encounter issues with this change,
please let me know and feel free to revert if I don't reply quickly.

This change was engineered to be easily revertable.

Differential Revision: https://reviews.llvm.org/D112082

[SelectionDAG] Fix getVectorSubVecPointer for scalable subvectors.

When inserting a scalable subvector into a scalable vector through
the stack, the index to store to needs to be scaled by vscale.
Before this patch, that didn't yet happen, so it would generate the
wrong offset, thus storing a subvector to the incorrect address
and overwriting the wrong lanes.

For some insert:
  nxv8f16 insert_subvector(nxv8f16 %vec, nxv2f16 %subvec, i64 2)

The offset was not scaled by vscale:
  orr     x8, x8, #0x4
  st1h    { z0.h }, p0, [sp]
  st1h    { z1.d }, p1, [x8]
  ld1h    { z0.h }, p0/z, [sp]

And is changed to:
  mov x8, sp
  st1h { z0.h }, p0, [sp]
  st1h { z1.d }, p1, [x8, #1, mul vl]
  ld1h { z0.h }, p0/z, [sp]

Differential Revision: https://reviews.llvm.org/D111633

[lldb] [Process/Linux] Support arbitrarily-sized FPR writes on ARM

Support arbitrarily-sized FPR writes on ARM in order to fix writing qN
registers directly.  Currently, writing them works only by accident
due to value_regs splitting them into smaller writes via dN and sN
registers.

Differential Revision: https://reviews.llvm.org/D112131

[lldb] [Process/Utility] Fix value_regs/invalidate_regs for ARM

Fix incorrect values for value_regs, and incomplete values for
invalidate_regs in RegisterInfos_arm.  The value_regs entry needs
to list only one base (i.e. larger) register that needs to be read
to get the value for this register, while invalidate_regs needs to list
all other registers (including pseudo-register) whose values would
change when this register is written to.

7a8ba4ffbeecb5070926b80bb839a4d80539f1ac fixed a similar problem
for ARM64.

Differential Revision: https://reviews.llvm.org/D112066

[lldb] [ABI/X86] Support combining xmm* and ymm*h regs into ymm*

gdbserver does not expose combined ymm* registers but rather XSAVE-style
split xmm* and ymm*h portions.  Extend value_regs to support combining
multiple registers and use it to create user-friendly ymm* registers
that are combined from split xmm* and ymm*h portions.

Differential Revision: https://reviews.llvm.org/D108937

[NewPM][test] Avoid using -enable-new-pm=1 since -passes implies new PM

[NewPM][test] Use -passes syntax in SpeculativeExecution lit tests

The legacy PM is deprecated, so use the new PM syntax in lit tests
running the speculative-execution pass.

[NewPM][test] Use -passes syntax in BoundsChecking lit tests

The legacy PM is deprecated, so use the new PM syntax in lit tests
running the bounds-checking pass.

[NewPM][test] Use -passes syntax in VectorCombine lit tests

The legacy PM is deprecated, so use the new PM syntax in lit tests
running the vector-combine pass.

[NewPM][test] Only use -passes syntax in Scalarizer lit tests

With legacy PM being deprecated it should be enough to verify the
scalarizer pass using the new-PM syntax when invoking opt.

[libc++] Move LIBCXX-DEBUG-FIXME to params.py

This temporary FIXME really belongs to the testing config, not to the
specific CMake cache that enables that configuration.

Differential Revision: https://reviews.llvm.org/D112031

[libFuzzer] Update InputInfo.TimeOfUnit when replacing it in the corpus.

Previously, when the fuzzing loop replaced an input in the corpus, it didn't update the execution time of the input. Therefore, some schedulers (e.g. Entropic) would adjust weights based on the incorrect execution time.

This patch updates the execution time of the input when replacing it.

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D111479

[mlir][Linalg] Add a first vectorization pattern for conv1d in NWCxWCF format.

This revision uses the newly refactored StructuredGenerator to create a simple vectorization for conv1d_nwc_wcf.

Note that the pattern is not specific to the op and is technically not even specific to the ConvolutionOpInterface (modulo minor details related to dilations and strides).

The overall design follows the same ideas as the lowering of vector::ContractionOp -> vector::OuterProduct: it seeks to be minimally complex, composable and extensible while avoiding inference analysis. Instead, we metaprogram the maps/indexings we expect and we match against them.

This is just a first stab and still needs to be evaluated for performance.
Other tradeoffs are possible that should be explored.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D111894

[DebugInfo][InstrRef] Track a single variable at a time

Here's another performance patch for InstrRefBasedLDV: rather than
processing all variable values in a scope at a time, instead, process one
variable at a time. The benefits are twofold:
 * It's easier to reason about one variable at a time in your mind,
 * It improves performance, apparently from increased locality.

The downside is that the value-propagation code gets indented one level
further, plus there's some churn in the unit tests.

Differential Revision: https://reviews.llvm.org/D111799

[mlir] Expand prefixing to OpFormatGen

Follow up to also use the prefixed emitters in OpFormatGen (moved
getGetterName(s) and getSetterName(s) to Operator as that is most
convenient usage wise even though it just depends on Dialect). Prefix
accessors in Test dialect and follow up on missed changes in
OpDefinitionsGen.

Differential Revision: https://reviews.llvm.org/D112118

[x86] make helper for useVPTERNLOG; NFC

See D112085 for another use case.

[clangd] Only publish preamble after rebuilds

Don't invoke parsing callback for preamble if clangd is using a
previously built one.

Differential Revision: https://reviews.llvm.org/D112137

[clangd] Fix use-after-free in HeaderIncluderCache

Includer cache could get into a bad state when a main file went bad and
added back afterwards. This patch adds a check to invalidate to prevent
that.

Differential Revision: https://reviews.llvm.org/D112130

[RISCV][WebAssembly][TargetLowering] Allow expandCTLZ/expandCTTZ to rely on CTPOP expansion for vectors.

Our fallback expansion for CTLZ/CTTZ relies on CTPOP. If CTPOP
isn't legal or custom for a vector type we would scalarize the
CTLZ/CTTZ. This is different than CTPOP itself which would use a
vector expansion.

This patch teaches expandCTLZ/CTTZ to rely on the vector CTPOP
expansion instead of scalarizing. To do this I had to add additional
checks to make sure the operations used by CTPOP expansions are all
supported. Some of the operations were already needed for the CTLZ/CTTZ
expansion.

This is a huge improvement to the RISCV which doesn't have a scalar
ctlz or cttz in the base ISA.

For WebAssembly, I've added Custom lowering to keep the scalarizing
behavior. I've also extended the scalarizing to CTPOP.

Differential Revision: https://reviews.llvm.org/D111919

[Sema, StaticAnalyzer] Use StringRef::contains (NFC)

[NewPM][test] Use -passes syntax in Mem2Reg lit tests

The legacy PM is deprecated, so use the new PM syntax in lit tests
verifying the mem2reg pass.

[NewPM][test] Strickly use -passes in some more lit tests

Removed/replaced RUN lines using legacy PM syntax in favor of using
-passes in lit tests for Float2Int, MetaRenamer, StripDeadPrototypes
and StripSymbols.

[lld-macho] Fix dangling string reference when adding frameworks

In Driver.cpp, addFramework used std::string instance to represent the path of a framework, which will be freed after the function returns. However, this string is stored in loadedArchive, which will be used later to compare with path of newly added frameworks. This caused https://bugs.llvm.org/show_bug.cgi?id=52133. A test is included in this commit to reproduce this bug.

Now resolveDylibPath returns a StringRef instance, and it uses StringSaver to save its data, then returns it to functions on the top. This ensures the resolved framework path is still valid after LC_LINKER_OPTION is parsed.

Reviewed By: int3, #lld-macho, oontvoo

Differential Revision: https://reviews.llvm.org/D111706

[analyzer][NFC] Refactor llvm::isa<> usages in the StaticAnalyzer

It turns out llvm::isa<> is variadic, and we could have used this at a
lot of places.

The following patterns:
  x && isa<T1>(x) || isa<T2>(x) ...
Will be replaced by:
  isa_and_non_null<T1, T2, ...>(x)

Sometimes it caused further simplifications, when it would cause even
more code smell.

Aside from this, keep in mind that within `assert()` or any macro
functions, we need to wrap the isa<> expression within a parenthesis,
due to the parsing of the comma.

Reviewed By: martong

Differential Revision: https://reviews.llvm.org/D111982

[RISCV] Use clang_builtin_alias for all RISCV vector intrinsics.

Previously we used builtin_alias for overloaded intrinsics, but
macros for the non-overloaded version. This patch changes the
non-overloaded versions to also use builtin_alias, but without
the overloadable attribute.

Reviewed By: khchen, HsiangKai

Differential Revision: https://reviews.llvm.org/D112020

[CodeGenPrepare] Avoid a scalable-vector crash in ctlz/cttz

This patch fixes a crash when despeculating ctlz/cttz intrinsics with
scalable-vector types. It is not safe to speculatively get the size of
the vector type in bits in case the vector type is not a fixed-length type. As
it happens this isn't required as vector types are skipped anyway.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D112141

[clang] Add plugin ActionType to run command line plugin before main action

Currently we have a way to run a plugin if specified on the command line
after the main action, and ways to unconditionally run the plugin before
or after the main action, but no way to run a plugin if specified on the
command line before the main action.

This introduces the missing option.

This is helpful because -clear-ast-before-backend clears the AST before
codegen, while some plugins may want access to the AST.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D112096

[MLIR][OpenMP] Shifted hint from CriticalOp to CriticalDeclareOp

According to the OpenMP 5.0 standard, names and hints of critical operation are
closely related. The following are the restrictions on them:
 - Unless the effect is as if `hint(omp_sync_hint_none)` was specified, the
   critical construct must specify a name.
 - If the hint clause is specified, each of the critical constructs with the
   same name must have a hint clause for which the hint-expression evaluates to
   the same value.

These restrictions will be enforced by design if the hint expression is a part
of the `omp.critical.declare` operation.
 - Any operation with no "name" will be considered to have
   `hint(omp_sync_hint_none)`.
 - All the operations with the same "name" will have the same hint value.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D112134

[InstCombine] add tests for casted insertelement; NFC

[OpenMP] Add GOMP allocator functions

This patch adds GOMP_alloc and GOMP_free functions of LIBGOMP.

Differential revision: https://reviews.llvm.org/D111673

[WebAssembly] Add prototype relaxed float min max instructions

Add relaxed. f32x4.min, f32x4.max, f64x2.min, f64x2.max. These are only
exposed as builtins, and require user opt-in.

Differential Revision: https://reviews.llvm.org/D112146

Fix unused variable warning.

[mlir] fix region property generation in python bindings

InvalidPtrChecker - don't dereference a dyn_cast<> - use cast<> instead.

Avoid dereferencing a nullptr returned by dyn_cast<>, by using cast<> instead which asserts that the cast is valid.

[IR] Refactor GlobalIFunc to inherit from GlobalObject, Remove GlobalIndirectSymbol

As discussed in:
* https://reviews.llvm.org/D94166
* https://lists.llvm.org/pipermail/llvm-dev/2020-September/145031.html

The GlobalIndirectSymbol class lost most of its meaning in
https://reviews.llvm.org/D109792, which disambiguated getBaseObject
(now getAliaseeObject) between GlobalIFunc and everything else.
In addition, as long as GlobalIFunc is not a GlobalObject and
getAliaseeObject returns GlobalObjects, a GlobalAlias whose aliasee
is a GlobalIFunc cannot currently be modeled properly. Creating
aliases for GlobalIFuncs does happen in the wild (e.g. glibc). In addition,
calling getAliaseeObject on a GlobalIFunc will currently return nullptr,
which is undesirable because it should return the object itself for
non-aliases.

This patch refactors the GlobalIFunc class to inherit directly from
GlobalObject, and removes GlobalIndirectSymbol (while inlining the
relevant parts into GlobalAlias and GlobalIFunc). This allows for
calling getAliaseeObject() on a GlobalIFunc to return the GlobalIFunc
itself, making getAliaseeObject() more consistent and enabling
alias-to-ifunc to be properly modeled in the IR.

I exercised some judgement in the API clients of GlobalIndirectSymbol:
some were 'monomorphized' for GlobalAlias and GlobalIFunc, and
some remained shared (with the type adapted to become GlobalValue).

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D108872

[Clang][AST] Resolve FIXME: Remove ObjCObjectPointer from
isSpecifierType

There is no reason to have this here, (since all tests pass) and it
isn't even a specifier anyway. We can just treat it as a pointer
instead.

Differential Revision: https://reviews.llvm.org/D110068

[NFC] De-template LazyCallGraph::visitReferences() and move into .cpp file

This makes changing it and recompiling it much faster.

Raise compile error when using unimplemented functions

The path functions in this patch are unimplemented (as per the TODO comment from upstream). To avoid running into a linker error (missing symbol), this patch raises a compile error by commenting out the functions, which is more user friendly.

Differential Revision: https://reviews.llvm.org/D111892

Precommit InstCombine/and-xor-or.ll test. NFC.

[clang] Disallow mixing SEH and Objective-C exceptions

We already disallow mixing SEH and C++ exceptions, and
mixing SEH and Objective-C exceptions seems to not work (see PR52233).
Emitting an error is friendlier than crashing.

Differential Revision: https://reviews.llvm.org/D112157

[ORC-RT] Configure the ORC runtime for more architectures and platforms

Enable building the ORC runtime for 64-bit and 32-bit ARM architectures,
and for all Darwin embedded platforms (iOS, tvOS, and watchOS). This
covers building the cross-platform code, but does not add TLV runtime
support for the new architectures, which can be added independently.

Incidentally, stop building the Mach-O TLS support file unnecessarily on
other platforms.

Differential Revision: https://reviews.llvm.org/D112111

[InstCombine] fold fake vector insert to bit-logic

bitcast (inselt (bitcast X), Y, 0) --> or (and X, MaskC), (zext Y)

https://alive2.llvm.org/ce/z/Ux-662

Similar to D111082 / db231ebdb07f :
We want to avoid relatively opaque vector ops on types that are
likely supported by the backend as scalar integers. The bitwise
logic ops are more likely to allow further combining.

We probably want to generalize this to allow a shift too, but
that would oppose instcombine's general rule of not creating
extra instructions, so that's left as a potential follow-up.
Alternatively, we could do that transform in VectorCombine
with the help of the TTI cost model.

This is part of solving:
https://llvm.org/PR52057

[lld/mac] Remove else-after-return in ICF code

No behavior change.

[MC] Recursively calculate symbol offset

This is speculative since I'm not sure if there's some implicit contract that a
variable symbol must not have another variable symbol in its evaluation tree.

Downstream bug: https://bugs.chromium.org/p/chromium/issues/detail?id=471146#c23.

Test is based on alias.s (removed checks since we just need to know it didn't
crash).

Differential Revision: https://reviews.llvm.org/D109109

[AMDGPU] Allow rematerialization of SOP with virtual registers

D106408 was doing this for all targets although it was
reverted due to couple performance regressions on some targets.
The difference for AMDGPU is the ability to rematerialize SOP
instructions with virtual register uses like we already do for VOP.

Differential Revision: https://reviews.llvm.org/D110743

[AMDGPU] MachineLICM cannot hoist VALU

MachineLoop::isLoopInvariant() returns false for all VALU
because of the exec use. Check TII::isIgnorableUse() to
allow hoisting.

That unfortunately results in higher register consumption
since MachineLICM does not adequately estimate pressure.
Therefor I think it shall only be enabled after D107677 even
though it does not depend on it.

Differential Revision: https://reviews.llvm.org/D107859

[lldb] Remove variable "any" which is set but not used

[AArch64][GlobalISel] combine (and (or x, c1), c2) => (and x, c2) iff c1 & c2 == 0

https://godbolt.org/z/h8ejrG4hb

rdar://83597585

Differential Revision: https://reviews.llvm.org/D111856

Drop transfer_read inner most unit dimensions

Add a pattern to take a rank-reducing subview and drop inner most
contiguous unit dim.
This is useful when lowering vector to backends with 1d vector types.

Reviewed By: ThomasRaoux

Differential Revision: https://reviews.llvm.org/D111561

Update ext-int test to have x86 linux/windows before ABI Impl

Writing a quick test to make sure we are aware of the change to the
_ExtInt/_BitInt ABI on x86 (32bit) OSes.

[fir] Add Character helper

This patch is extracted from D111337. It introduce the
CharacterExprHelper that helps dealing with character in FIR.

Reviewed By: schweitz, awarzynski

Differential Revision: https://reviews.llvm.org/D112140

Co-authored-by: Jean Perier <jperier@nvidia.com>
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Co-authored-by: V Donaldson <vdonaldson@nvidia.com>

Make dr177x.cpp test work with Windows-32 bit platfroms with 'thiscall'.

My downstream noticed that the test failed on windows-32 bit machines
since the types have __attribute__((thiscall)) on them in a few places.
This patch just adds a wildcard to handle that, since it isn't
particularly important to the test.

[mlir][sparse] make index type explicit in public API of support library

The current implementation used explicit index->int64_t casts for some, but
not all instances of passing values of type "index" in and from the sparse
support library. This revision makes the situation more consistent by
using new "index_t" type at all such places  (which allows for less trivial
casting in the generated MLIR code).  Note that the current revision still
assumes that "index" is 64-bit wide. If we want to support targets with
alternative "index" bit widths, we need to build the support library different.
But the current revision is a step forward by making this requirement explicit
and more visible.

Reviewed By: wrengr

Differential Revision: https://reviews.llvm.org/D112122

[IndVars] Invalidate SCEV when IR is changed in rewriteLoopExitValue.

At the moment, rewriteLoopExitValue forgets the current phi node in the
loop that collects phis to rewrite. A few lines after the value is
forgotten, SCEV is used again to analyze incoming values and
potentially expand SCEV expression. This means that another SCEV is
created for PN, before the IR is actually updated in the next loop.

This leads to accessing invalid cached expression in combination with
D71539.

PN should only be changed once the actual incoming exit value is set in
the next loop. Moving invalidation there should ensure that PN is
invalidated in all relevant cases.

Reviewed By: mkazantsev

Differential Revision: https://reviews.llvm.org/D111495

Precommit updated InstCombine/and-xor-or.ll test. NFC.

Remove include of 'type_info' from ext-int test.

Originally I thought that I needed to do a #include to trick the
compiler into letting me use typeid I believe, but Aaron explained that
it was just looking for the type_info type.  I had to give it some
public/private members to make it emit the same as before, but this
ought to be a 'perfect' replacement.

[InstCombine] Fold `(a & ~b) & ~c` to `a & ~(b | c)`

  %not1 = xor i32 %b, -1
  %not2 = xor i32 %c, -1
  %and1 = and i32 %a, %not1
  %and2 = and i32 %and1, %not2
=>
  %i1 = or i32 %b, %c
  %i2 = xor i32 %1, -1
  %and2 = and i32 %i2, %a

Differential Revision: https://reviews.llvm.org/D112108

[libc++] Fix incorrect main() signatures in the tests

Those creep up from time to time. We need to use `int main(int, char**)`
because in freestanding mode, `main` doesn't get special treatment and
special mangling, so we setup a symbol alias from the mangled version of
`main(int, char**)` to `extern "C" main`. That only works if all the tests
are consistent about how they define their main function.

[x86] add special-case lowering for usubsat for AVX512

This is a small extension of D112095 to avoid another regression
seen with D112085.
In this case, we allow the same conversion from usubsat to ALU
ops if the target supports vpternlog.

That pattern will get converted later in X86DAGToDAGISel::tryVPTERNLOG().
This seems better than putting a magic immediate constant directly in
this code to create the exact vpternlog that we need. It's possible that
there are other special-cases along these lines, so we should try to
keep all of the vpternlog magic in one place.

Differential Revision: https://reviews.llvm.org/D112138

Revert "[fir] Add Character helper"

This reverts commit 02d7089c239075a5c2e148087d2824d253fc3d5f.

[Tests] Add tests for non-speculatable ephemeral values

The loads in these examples are currently not considered ephemeral
because they are not speculatable.

[libc++abi] Guard include of <unistd.h> behind __has_include

This doesn't change anything on platforms that have <unistd.h>, but
it will allow this file to compile on platforms that do not.

[libunwind] Revert "Use the from-scratch testing configuration by default"

This reverts commit 5a8ad80b6fa5cbad58b78384f534b78fca863e7f, which broke
the Bootstrapping build. I'm reverting until we've fixed the issue.

Differential Revision: https://reviews.llvm.org/D112082

[runtimes] Rename CI job from "Runtimes build" to "Bootstrapping build"

Revert "[ORC-RT] Configure the ORC runtime for more architectures and platforms"

Broke on aarch64-linux. Reverting while I investigate.

This reverts commit 5692ed0cce8c9506eef40ffe6ca2d9629956c51c.

[ARM] Fix inline assembly referencing floating point registers on soft-float targets

Fixes PR: https://bugs.llvm.org/show_bug.cgi?id=52230

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D112135

OS Laboratory, Huawei Russian Research Institute, Saint-Petersburg

[SelectionDAG] Bail out of mergeTruncStores when not optimizing

With unoptimized code, we may see lots of stores and spend too much time in mergeTruncStores.

Fixes PR51827.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D111596

[lld-macho] Temporarily disable lc-linker-option.ll on Windows

It's currently using a symlink, which is not supported on Windows.

[msan] Add stat-family interceptors on Linux

Add following interceptors on Linux: stat, lstat, fstat, fstatat.

This fixes use-of-uninitialized value on platforms with GLIBC 2.33+.
In particular: Arch Linux, Ubuntu hirsute/impish.

The tests should have also been failing during the release on the mentioned platforms, but I cannot find any related discussion.

Most likely, the regression was introduced by glibc commit [[ https://github.com/bminor/glibc/commit/8ed005daf0ab03e142500324a34087ce179ae78e | 8ed005daf0ab03e14250032 ]]:
all stat-family functions are now exported as shared functions.

Before, some of them (namely stat, lstat, fstat, fstatat) were provided as a part of libc_noshared.a and called their __xstat dopplegangers. This is still true for Debian Sid and earlier Ubuntu's. stat interceptors may be safely provided for them, no problem with that.

Closes https://github.com/google/sanitizers/issues/1452.
See also https://jira.mariadb.org/browse/MDEV-24841

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D111984

[ARM] Use correct name of floating point ceil intrinsic in test.

The intrinsic is called llvm.ceil not llvm.fceil. The checks weren't
strong enough to notice that a call to llvm.fceil was emitted in
the final assembly.

[Driver][OpenBSD] Some improvements to the external assembler handling

- Pass CPU variant for ARM
- Pass MIPS CPU in addition to the ABI

[MLIR][OpenMP] Add support for ordered construct

This patch supports the ordered construct in OpenMP dialect following
Section 2.19.9 of the OpenMP 5.1 standard. Also lowering to LLVM IR
using OpenMP IRBduiler. Lowering to LLVM IR for ordered simd directive
is not supported yet since LLVM optimization passes do not support it
for now.

Reviewed By: kiranchandramohan, clementval, ftynse, shraiysh

Differential Revision: https://reviews.llvm.org/D110015

[modules] While merging ObjCInterfaceDecl definitions, merge them as decl contexts too.

While working on https://reviews.llvm.org/D110280 I've tried to merge
decl contexts as it seems to be correct and matching our handling of
decl contexts from different modules. It's not required for the fix in
https://reviews.llvm.org/D110280 but it revealed a missing diagnostic,
so separating this change into a separate commit.

Renamed some variables to distinguish diagnostic like "declaration of
'x' does not match" for different cases.

Differential Revision: https://reviews.llvm.org/D110287

[Codegen] Set ARITH_FENCE as meta-instruction

ARITH_FENCE, which was added by https://reviews.llvm.org/D99675,
should be a meta-instruction b/c it only emits comments "ARITH_FENCE".

Reviewed By: pengfei, LuoYuanke

Differential Revision: https://reviews.llvm.org/D112127

[lld-macho][nfc] Added some notes on deliberate differences btw LD64 vs LLD-MACHO

For future references and to help with debugging crashes, this could be useful.

Differential Revision: https://reviews.llvm.org/D110464

[NFC][msan] Break the loop when done

We have nothing to do after the Argument
is found.

[NFC][msan] Rerun update_test_checks.py for a test

[NFC][msan] Add NormalArgAfterNoUndef testcase

[ELF] Avoid adding an orphan section to a less suitable segment

If segments are defined in a linker script, placing an orphan section
before the found closest-rank section can result in adding it in a
previous segment and changing flags of that segment. This happens if
the orphan section has a lower sort rank than the found section. To
avoid that, the patch forces orphan sections to be moved after the
found section if segments are explicitly defined.

Differential Revision: https://reviews.llvm.org/D111717

Revert "[MLIR][OpenMP] Add support for ordered construct"

This reverts commit dc2be87ecf10f2f1cf05f638a72256387c78f1c1.

Seems like this broke all the CI bots.