Changes

Summary

  1. Fix clone_constant_impl to correctly deal with null pointers (details)
  2. [analyzer] Fixup scan-build tests for non-Darwin platforms. (details)
  3. [analyzer] Require darwin for scan-build tests (details)
  4. [X86] Teach X86MCInstLower to swap operands of commutable instructions (details)
  5. [BPF] fix a use after free bug (details)
  6. [IR] Add Freeze instruction (details)
  7. [X86] Lower the cost of avx512 horizontal bool and/or reductions to (details)
  8. [IR] Remove switch's default block that causes clang 8 raise error (details)
Commit 31be9f3f7dee80c586d3beac9a65663d5628cf96 by aqjune
Fix clone_constant_impl to correctly deal with null pointers
Summary: This patch resolves llvm-c-test's following error
``` LLVM ERROR: LLVMGetValueKind returned incorrect type
```
which arises when the input bitcode contains a null pointer.
Reviewers: jdoerfert, CodaFi, deadalnix
Reviewed By: jdoerfert
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68928
The file was modifiedllvm/test/Bindings/llvm-c/echo.ll
The file was modifiedllvm/tools/llvm-c-test/echo.cpp
Commit 48223d92a98e2eb7da6844d56471953f83da191e by Devin Coughlin
[analyzer] Fixup scan-build tests for non-Darwin platforms.
This is a fix to 0aba69eb1a01c44185009f50cc633e3c648e9950 to address
failing bots.
The file was modifiedclang/test/Analysis/scan-build/html_output.test
The file was modifiedclang/test/Analysis/scan-build/exclude_directories.test
The file was modifiedclang/test/Analysis/scan-build/plist_html_output.test
The file was modifiedclang/test/Analysis/scan-build/plist_output.test
The file was modifiedclang/test/Analysis/scan-build/help.test
Commit abc04ff4012c62c98aa9f0d840114b2f56855dc8 by Devin Coughlin
[analyzer] Require darwin for scan-build tests
Let's at least get some coverage from these tests. We can generalize to
other platforms later.
The file was modifiedclang/test/Analysis/scan-build/plist_output.test
The file was modifiedclang/test/Analysis/scan-build/html_output.test
The file was modifiedclang/test/Analysis/scan-build/plist_html_output.test
The file was modifiedclang/test/Analysis/scan-build/help.test
The file was modifiedclang/test/Analysis/scan-build/exclude_directories.test
Commit f65493a83e3bdb402fb1dfa92bcc25707e961147 by craig.topper
[X86] Teach X86MCInstLower to swap operands of commutable instructions
to enable 2-byte VEX encoding.
Summary: The 2 source operands commutable instructions are encoded in
the VEX.VVVV field and the r/m field of the MODRM byte plus the VEX.B
field.
The VEX.B field is missing from the 2-byte VEX encoding. If the VEX.VVVV
source is 0-7 and the other register is 8-15 we can swap them to avoid
needing the VEX.B field. This works as long as the VEX.W, VEX.mmmmm, and
VEX.X fields are also not needed.
Fixes PR36706.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68550
The file was modifiedllvm/test/CodeGen/X86/midpoint-int-vec-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-rotate-256.ll
The file was modifiedllvm/test/CodeGen/X86/masked_compressstore.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-packus.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-512.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-256.ll
The file was modifiedllvm/test/CodeGen/X86/uadd_sat_vec.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-256.ll
The file was modifiedllvm/test/CodeGen/X86/vec_umulo.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-by-select-loop.ll
The file was modifiedllvm/test/CodeGen/X86/sad.ll
The file was modifiedllvm/test/CodeGen/X86/pr29112.ll
The file was modifiedllvm/test/CodeGen/X86/masked_expandload.ll
The file was modifiedllvm/test/CodeGen/X86/vector-rotate-512.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-mask-op.ll
The file was modifiedllvm/test/CodeGen/X86/madd.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-math.ll
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-256.ll
The file was modifiedllvm/test/CodeGen/X86/avx-intel-ocl.ll
The file was modifiedllvm/test/CodeGen/X86/avx512-vselect.ll
The file was modifiedllvm/lib/Target/X86/X86MCInstLower.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
Commit 9f34447f3ff525029ec889bf3a82b04678a9d7c0 by yhs
[BPF] fix a use after free bug
Commit fff2721286e1 ("[BPF] Fix CO-RE bugs with bitfields") fixed CO-RE
handling bitfield issues. But the implementation introduced a use after
free bug. The "Base" of the intrinsic might be freed so later on
accessing the Type of "Base" might access the freed memory. The failed
test case,
CodeGen/BPF/CORE/offset-reloc-middle-chain.ll is exactly used to test
such a case.
Similarly to previous attempt to remember Metadata etc, remember "Base"
pointee Alignment in advance to avoid such use after free bug.
The file was modifiedllvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
Commit 58acbce3def63a207b8f5a69318a99666a4aac53 by aqjune
[IR] Add Freeze instruction
Summary:
- Define Instruction::Freeze, let it be UnaryOperator
- Add support for freeze to LLLexer/LLParser/BitcodeReader/BitcodeWriter
The format is `%x = freeze <ty> %v`
- Add support for freeze instruction to llvm-c interface.
- Add m_Freeze in PatternMatch.
- Erase freeze when lowering IR to SelDag.
Reviewers: deadalnix, hfinkel, efriedma, lebedev.ri, nlopes, jdoerfert,
regehr, filcab, delcypher, whitequark
Reviewed By: lebedev.ri, jdoerfert
Subscribers: jfb, kristof.beyls, hiraditya, lebedev.ri, steven_wu,
dexonsmith, xbolva00, delcypher, spatel, regehr, trentxintong, vsk,
filcab, nlopes, mehdi_amini, deadalnix, llvm-commits
Differential Revision: https://reviews.llvm.org/D29011
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/include/llvm-c/Core.h
The file was modifiedllvm/lib/AsmParser/LLLexer.cpp
The file was modifiedllvm/test/Bindings/OCaml/core.ml
The file was modifiedllvm/include/llvm/IR/PatternMatch.h
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
The file was modifiedllvm/lib/IR/Instruction.cpp
The file was modifiedllvm/test/Bitcode/compatibility.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/include/llvm/IR/IRBuilder.h
The file was modifiedllvm/include/llvm/IR/Operator.h
The file was modifiedllvm/lib/IR/ConstantFold.cpp
The file was modifiedllvm/tools/llvm-c-test/echo.cpp
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was modifiedllvm/include/llvm/IR/Instruction.def
The file was modifiedllvm/test/Transforms/MergeFunc/inline-asm.ll
The file was modifiedllvm/lib/IR/Instructions.cpp
The file was modifiedllvm/lib/AsmParser/LLToken.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
The file was modifiedllvm/include/llvm/Bitcode/LLVMBitCodes.h
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
The file was addedllvm/test/Bindings/llvm-c/freeze.ll
The file was modifiedllvm/lib/IR/Core.cpp
Commit 103968d147b135ebfcee69d6d7a1428163e66aaa by craig.topper
[X86] Lower the cost of avx512 horizontal bool and/or reductions to
2*log2(bitwidth)+1 for legal types.
This better represents the kshift+binop we'd get for each stage before
the final extract. Its likely we'll do even better by doing a kmov and a
cmp with a GPR, but this is a good start.
The default handling was costing a worst case single source permute
shuffle of the vector before the binop. This worst case assumes the
shuffle might have to be emulated with extracts and inserts. But since
we know we're doing a reduction we can assume we'll get kshift lowering.
There's still some room for improvement here, but this is much better
than it was.
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-or.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-and.ll
Commit 92ef101da91d39525043034694b3088d0a08f43f by aqjune
[IR] Remove switch's default block that causes clang 8 raise error
The file was modifiedllvm/lib/IR/ConstantFold.cpp