Changes

[lldb][NFC] Give some parameters in CommandInterpreter more descriptive
names

[AArch64] Update test checks on merge-store-dependency.ll. NFC

Recommit "[HardwareLoops] Optimisation remarks"
With a few things fixed:
- initialisaiton of the optimisation remark pass (this was causing the
buildbot
 failures on PPC),
- a test case.
Differential Revision: https://reviews.llvm.org/D69660

[mips] Fix `__mips_isa_rev` macros value for Octeon CPU

[mips] Set __OCTEON__ macros

DWARFDebugLoclists: Make it possible to read relocated addresses
Summary: Handling relocations was not needed when the loclists section
was a DWO-only thing. But since DWARF5, it is possible to use it in
regular objects too, and the standard permits embedding addresses into
the section directly. These addresses need to be relocated in unlinked 
files.
Reviewers: JDevlieghere, dblaikie, probinson
Subscribers: aprantl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68271

[RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook
Summary: Introduces the `InstrInfo::areMemAccessesTriviallyDisjoint` 
hook. The test could check for instruction reorderings, but to avoid 
being brittle it just checks instruction dependencies.
Reviewers: asb, lenary Reviewed By: lenary Tags: #llvm Differential
Revision: https://reviews.llvm.org/D67046

[InstCombine] dropRedundantMaskingOfLeftShiftInput(): truncation
(PR42563)
Summary: That fold keeps growing and growing :( I think this may be one
of the last pieces for it.
Since D67677/D67725, the fold knowns the general form of the pattern -
where some masking is needed: https://rise4fun.com/Alive/F5R 
https://rise4fun.com/Alive/gslRa
But there is one more huge piece missing - if you are extracting some
bits, it is not impossible that the origin is wider than the extraction, 
i.e. there may be a truncation. And we don't deal with that yet.
But we can, and the generalization remains fully identical: 
https://rise4fun.com/Alive/Uar https://rise4fun.com/Alive/5SW
After a preparatory cleanup i think the diff looks rather clean.
One missing piece is that in some patterns (especially pat. b),
`-1` only needs to be `-1` in final type, but that is for later..
https://bugs.llvm.org/show_bug.cgi?id=42563
Reviewers: spatel, nikic
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69125

[LoopUnroll] peel-loop-conditions.ll: add some 'is even/odd' peeling
tests

MemoryRegion: Print "don't know" permission values as such
Summary: The permissions in a memory region have ternary states (yes,
no, don't know), but the memory region command only prints in binary,
treating
"don't know" as "yes", which is particularly confusing as for instance 
the unwinder will treat an unknown value as "no".
This patch makes is so that we distinguish all three states when 
printing the values, using "?" to indicate the lack of information. It 
is implemented via a special argument to the format provider for the 
OptionalBool enumeration.
Reviewers: clayborg, jingham
Subscribers: lldb-commits
Differential Revision: https://reviews.llvm.org/D69106

lldb/minidump: Add support for the alternate ARM64 constant

[OpenCL] Add builtin function attribute handling
Add handling for the "pure", "const" and "convergent" function 
attributes for OpenCL builtin functions.
Patch by Pierre Gondois and Sven van Haastregt.
Differential Revision: https://reviews.llvm.org/D64319

[OpenCL] Group builtin functions by prototype
The TableGen-generated file containing the function definitions can be 
reorganized to save some memory in the Clang binary.  Functions having 
the same prototype(s) will point to a shared list of prototype(s).
Patch by Pierre Gondois and Sven van Haastregt.
Differential Revision: https://reviews.llvm.org/D63557

Revert and patch "[Python] Remove readline module"
Fix https://bugs.llvm.org/show_bug.cgi?id=43830 while avoiding polluting
the global Python namespace.
This both reverts r357277 to rebundle a version of Python's readline
module based on libedit.
However, this patch also provides two improvements over the previous 
implementation:
1. use PyMem_RawMalloc instead of PyMem_Malloc, as expected by
PyOS_Readline
  (prevents to segfault upon exit of interactive session) 2. patch the
readline module upon embedded interpreter loading, instead of
  patching it globally, which should prevent any side effect on other
  modules/packages 3. only activate the patched module if libedit is
actually linked in lldb
Differential Revision: https://reviews.llvm.org/D69793

lldb/breakpad: add suppport for the "x86_64h" architecture

[Scheduling][ARM] Consistently enable PostRA Machine scheduling
In the ARM backend, for historical reasons we have only some targets 
using Machine Scheduling. The rest use the old list scheduler as they 
are using itinaries and the list scheduler seems to produce better code
(and not crash running out of register on v6m codes). So whether to use 
the MIScheduler or not is checked at runtime from the subtarget 
features.
This is fine, except for post-ra scheduling. Whether to use the old 
post-ra list scheduler or the post-ra machine schedule is decided as the 
pass manager is set up, in arms case from a newly constructed subtarget. 
Under some situations, like LTO, this won't include the correct cpu so 
can pick the wrong option. This can have a surprising effect on 
performance.
To fix that, this patch overrides targetSchedulesPostRAScheduling and 
addPreSched2 in the ARM backend, adding _both_ post-ra schedulers and 
picking at runtime which to execute. To pick between the two I've had to 
add a enablePostRAMachineScheduler() method that normally returns 
enableMachineScheduler() && enablePostRAScheduler(), which can be 
overridden to enable just one of PostRAMachineScheduler vs 
PostRAScheduler.
Thanks to David Penry for the identifying this problem.
Differential Revision: https://reviews.llvm.org/D69775

[ARM] Always enable UseAA in the arm backend
This feature controls whether AA is used into the backend, and was 
previously turned on for certain subtargets to help create less 
constrained scheduling graphs. This patch turns it on for all 
subtargets, so that they can all make use of the extra information to 
produce better code.
Differential Revision: https://reviews.llvm.org/D69796

Fix PR40644: miscompile indexed FP constant store
Summary: Functions replaceStoreOfFPConstant() and OptimizeFloatStore()
both replace store of float by a store of an integer unconditionally.
However this generates wrong code when the store that is replaced is an
indexed or truncating store. This commit solves this issue by adding an
early return in these functions when the store being considered is not a 
normal store.
Bug was only observed on out of tree targets, hence the lack of testcase 
in this commit.
Reviewers: efriedma
Subscribers: hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68420

[Clang FE]  Recognize -mnop-mcount CL option (SystemZ only).
Recognize -mnop-mcount from the command line and add a function
attribute
"mnop-mcount"="true" when passed.
When this option is used, a nop is added instead of a call to fentry.
This is used when building the Linux Kernel.
If this option is passed for any other target than SystemZ, an error is 
generated.
Review: Ulrich Weigand https://reviews.llvm.org/D67763