Commit
a9018fddf9ba17e53a35674bf0a93e78382c4c23
by dave[X86] Add more add/sub carry tests Preparation for: https://reviews.llvm.org/D70079 https://reviews.llvm.org/D70077
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 | llvm/test/CodeGen/SystemZ/int-uadd-03.ll |
 | llvm/test/CodeGen/X86/subcarry.ll |
 | llvm/test/CodeGen/SystemZ/int-usub-03.ll |
 | llvm/test/CodeGen/X86/addcarry.ll |
Commit
ebe2f56030458e7a4c2375c6d92a48f0ed01eb5b
by pavelDWARFDebugLoclists: add location list "interpretation" logic Summary: This patch extracts the logic for computing the "absolute" locations, which was partially present in the debug_loclists dumper, completes it, and moves it into a separate function. This makes it possible to later reuse the same logic for uses other than dumping. The dumper is changed to reuse the location list interpreter, and its format is changed somewhat. In "verbose" mode it prints the "raw" value of a location list, the interpreted location (if available) and the expression itself. In non-verbose mode it prints only one of the location forms: it prefers the interpreted form, but falls back to the "raw" format if interpretation is not possible (for instance, because we were not given a base address, or the resolution of indirect addresses failed). This patch also undos some of the changes made in D69672, namely the part about making all functions static. The main reason for this is that I learned that the original approach (dumping only fully resolved locations) meant that it was impossible to rewrite one of the existing tests. To make that possible (and make the "inline location" dump work in more cases), I now reuse the same dumping mechanism as is used for section-based dumping. As this required having more objects know about the various location lists classes, it seemed like a good idea to create an interface abstracting the difference between them. Therefore, I now create a DWARFLocationTable class, which will serve as a base class for the location list classes. DWARFDebugLoclists is made to inherit from that. DWARFDebugLoc will follow. Another positive effect of this change is that section-based dumping code will not need to use templates (as originally) envisioned, and that the argument lists of the dumping functions become shorter. Reviewers: dblaikie, probinson, JDevlieghere, aprantl, SouraVX Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70081
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 | llvm/include/llvm/DebugInfo/DWARF/DWARFLocationExpression.h |
 | llvm/test/tools/llvm-dwarfdump/X86/debug_loclists_startx_length.s |
 | llvm/test/CodeGen/X86/debug-loclists.ll |
 | llvm/test/DebugInfo/X86/fission-ranges.ll |
 | llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp |
 | llvm/lib/DebugInfo/DWARF/DWARFDie.cpp |
 | llvm/test/tools/llvm-dwarfdump/X86/debug_loclists.s |
 | llvm/lib/DebugInfo/DWARF/DWARFContext.cpp |
 | llvm/test/tools/llvm-dwarfdump/X86/debug_loc_dwo.s |
 | llvm/test/DebugInfo/X86/loclists-dwp.ll |
 | llvm/include/llvm/DebugInfo/DWARF/DWARFDebugLoc.h |
Commit
ec4c96d68566debcc4588c4189b4ef8a5f78729a
by Raphael Isemann[lldb][NFC] Simplify a return in ThreadPlanStepInRange::DefaultShouldStopHereCallback We know should_stop_here is false here, so we might as well return false directly.
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 | lldb/source/Target/ThreadPlanStepInRange.cpp |
Commit
1ee93240c02b0fd505a539691d58565376f8acdf
by flo[LoopInterchange] Only skip PHIs with incoming values from the inner loop. Currently we have limited support for outer loops with multiple basic blocks after the inner loop exit. But the current checks for creating PHIs for loop exit values only assumes the header and latches of the outer loop. It is better to just skip incoming values defined in the original inner loops. Those are handled earlier. Reviewers: efriedma, mcrosier Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D70059
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 | llvm/test/Transforms/LoopInterchange/pr43797-lcssa-for-multiple-outer-loop-blocks.ll |
 | llvm/lib/Transforms/Scalar/LoopInterchange.cpp |
Commit
3130a88137ddc6ee277c4e896f235cf93d883dfa
by Tatyana Krasnukha[lldb][test] Macros in expressions require DWARF 5
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 | lldb/packages/Python/lldbsuite/test/commands/expression/macros/TestMacros.py |
 | lldb/packages/Python/lldbsuite/test/commands/expression/macros/Makefile |
Commit
002625113ba815d1d08463411e67875be6e19a3f
by llvm-dev[X86] Add PR39464 addcarry/subborrow test cases Additional coverage for D70079
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 | llvm/test/CodeGen/X86/addcarry.ll |
 | llvm/test/CodeGen/X86/subcarry.ll |
Commit
6da34a8b847f2c858f421278a38dd343d2e8507b
by llvm-devFileCheckPattern::FindRegexVarEnd - make helper function static. NFC Fixes cppcheck warning.
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 | llvm/lib/Support/FileCheckImpl.h |
Commit
8794f6787685655223be8a029bf51a1565f7a231
by llvm-dev[X86] Cleanup prefixes + regenerate for fp-intrinsics-fma.ll
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 | llvm/test/CodeGen/X86/fp-intrinsics-fma.ll |
Commit
7f1dcc8952e6a1a4ba918159ab86bd787d584930
by diana.picus[InstCombine] Skip scalable vectors in combineLoadToOperationType Don't try to canonicalize loads to scalable vector types to loads of integers. This removes one assertion when trying to use a TypeSize as a parameter to DataLayout::isLegalInteger. It does not handle the second part of the function (which looks at bitcasts). This patch also contains a NFC fix for Load Analysis, where a variable initialization that would cause the same assertion is moved closer to its use. This allows us to run the new test for InstCombine without having to teach LocationSize to play nicely with scalable vectors. Differential Revision: https://reviews.llvm.org/D70075
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 | llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp |
 | llvm/test/Transforms/InstCombine/load.ll |
 | llvm/lib/Analysis/Loads.cpp |
Commit
636412bf31fc4285d63faeea67e4d71e44e3799c
by flo[AArch64ExpandPseudos] Preserve renamable state when expanding MOVi64 & co. If the MOVi operand was renamable, the operands of the expanded instructions are also renamable. Reviewers: thegameg, samparker, zatrazz Reviewed By: thegameg Differential Revision: https://reviews.llvm.org/D70061
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 | llvm/test/CodeGen/AArch64/expand-movi-renamable.mir |
 | llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp |
Commit
77cc246412ca40082c0902f1300f53d29dd98c02
by mgorny[lldb] [Process/NetBSD] Use PT_STOP to stop the process [NFCI] Differential Revision: https://reviews.llvm.org/D70060
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 | lldb/source/Plugins/Process/NetBSD/NativeProcessNetBSD.h |
 | lldb/source/Plugins/Process/NetBSD/NativeProcessNetBSD.cpp |
Commit
44e5879f0fb7c28b90e8042fde81bba30b4090a3
by Tim NorthoverAArch64: add arm64_32 support to Clang.
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 | clang/lib/Sema/SemaChecking.cpp |
 | clang/lib/Basic/Targets/AArch64.cpp |
 | clang/test/Driver/aarch64-cpus.c |
 | clang/test/Preprocessor/init-v7k-compat.c |
 | clang/lib/CodeGen/CGBuiltin.cpp |
 | clang/test/CodeGen/target-data.c |
 | clang/lib/Driver/ToolChains/CommonArgs.cpp |
 | clang/lib/Sema/SemaType.cpp |
 | clang/test/Preprocessor/stdint.c |
 | clang/test/Driver/arm64_32-link.c |
 | clang/lib/Basic/Targets/AArch64.h |
 | clang/lib/Driver/ToolChain.cpp |
 | clang/test/CodeGen/arm64_32-vaarg.c |
 | clang/test/Preprocessor/aarch64-target-features.c |
 | clang/lib/Driver/ToolChains/Darwin.cpp |
 | clang/test/CodeGen/builtins-arm64.c |
 | clang/test/CodeGenCXX/armv7k.cpp |
 | clang/lib/Driver/ToolChains/Clang.cpp |
 | clang/test/Preprocessor/arm64_32.c |
 | clang/test/Sema/aarch64-neon-vector-types.c |
 | clang/lib/Basic/Targets.cpp |
 | clang/test/CodeGen/arm64_32.c |
 | clang/lib/CodeGen/TargetInfo.cpp |
 | clang/test/Sema/types.c |
Commit
5022a5fcaef9e8e5a739d5794954d67bc6f291a2
by alexMark llvm::ConstantExpr::getAsInstruction as const Summary: getAsInstruction is the only non-const member method. It is impossible to enforce const-correctness because of it. Reviewers: jmolloy, majnemer Reviewed By: jmolloy Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70113
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 | llvm/lib/IR/Constants.cpp |
 | llvm/include/llvm/IR/Constants.h |
Commit
1dfb1a85e7cbc37bf6fff9bb046c6e8be0c26b8e
by pavel[lldb] Fix some warnings in the python plugin
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 | lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp |
 | lldb/source/Plugins/ScriptInterpreter/Python/PythonDataObjects.h |
Commit
6aa60b0514865751ea9dd208236db60eb69aaf1e
by pavel[lldb] Fix more -Wdeprecated-copy warnings This warning triggers when a class defines a copy constructor but not a copy-assignment operator (which then gets auto-generated by the compiler). Fix the warning by deleting the other operator too, as the default implementation works just fine.
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 | lldb/include/lldb/Host/SocketAddress.h |
 | lldb/source/Host/common/TCPSocket.cpp |
 | lldb/include/lldb/Utility/StringExtractorGDBRemote.h |
 | lldb/source/Host/common/SocketAddress.cpp |
 | lldb/include/lldb/Core/SearchFilter.h |
 | lldb/source/Core/SearchFilter.cpp |
Commit
a6c40f56aed1556a80867209b6846f7eedc4dc78
by omair.javaidRevert "Fix lookup of symbols at the same address with no size vs. size" This reverts commit 3f594ed1686b44138bee245c708773e526643aaf. This change has cause LLDB expression evaluation to fail on Arm Linux. Differential Revision: https://reviews.llvm.org/D63540
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 | lldb/source/Symbol/Symtab.cpp |
 | lldb/test/Shell/SymbolFile/sizeless-symbol.test |
 | lldb/test/Shell/SymbolFile/Inputs/sizeless-symbol.s |
Commit
7d0b1d77b3d4d47df477519fd1bf099b3df6f899
by flo[Examples] Add IRTransformations directory to examples. This patch adds a new IRTransformations directory to llvm/examples/. This is intended to serve as a new home for example transformations/analysis code used by various tutorials. If LLVM_BUILD_EXAMPLES is enabled, the ExamplesIRTransforms library is linked into the opt binary and the example passes become available. To start off with, it contains the CFG simplifications used in the IR part of the 'Getting Started With LLVM: Basics' tutorial at the US LLVM Developers Meeting 2019. Reviewers: paquette, jfb, meikeb, lhames, kbarton Reviewed By: paquette Differential Revision: https://reviews.llvm.org/D69416
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 | llvm/examples/IRTransforms/SimplifyCFG.h |
 | llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg3-phis.ll |
 | llvm/examples/IRTransforms/InitializePasses.h |
 | llvm/CMakeLists.txt |
 | llvm/examples/CMakeLists.txt |
 | llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg5-del-phis-for-dead-block.ll |
 | llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg1.ll |
 | llvm/examples/IRTransforms/SimplifyCFG.cpp |
 | llvm/examples/IRTransforms/CMakeLists.txt |
 | llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg-blockaddress.ll |
 | llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg4-multiple-duplicate-cfg-updates.ll |
 | llvm/examples/IRTransforms/InitializePasses.cpp |
 | llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg2-dead-block-order.ll |
 | llvm/tools/opt/CMakeLists.txt |
 | llvm/test/Examples/IRTransforms/SimplifyCFG/tut-simplify-cfg6-dead-self-loop.ll |
 | llvm/tools/opt/opt.cpp |
Commit
4cc0c2998d64156c9f848a8c2b2aed375ebd58b6
by Jinsong Ji[PowerPC][NFC]Fix typo in desc for enable-ppc-prefetching
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 | llvm/lib/Target/PowerPC/PPCTargetMachine.cpp |
Commit
41c3f76dcd0daeec60eddfcb56008a31ad6e8738
by Tom.Weaver[DBG][OPT] Attempt to salvage or undef debug info when removing trivially deletable instructions in the Reassociate Expression pass. Reviewed By: aprantl, vsk Differential revision: https://reviews.llvm.org/D69943
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 | llvm/test/Transforms/Reassociate/undef_intrinsics_when_deleting_instructions.ll |
 | llvm/lib/Transforms/Scalar/Reassociate.cpp |
 | llvm/test/Transforms/Reassociate/reassociate_salvages_debug_info.ll |
Commit
228dd96c6fddad6d070c29a6830c7bd161982e3a
by Jinsong Ji[PowerPC] Remove allow-deprecated-dag-overlap and fix broken tests Summary: This is found during review of https://reviews.llvm.org/D67088. CHECK-DAG is non-overlapping after https://reviews.llvm.org/D47106. -allow-deprecated-dag-overlap was introduced to temporary accept old behavior. But it actually hide some broken tests, eg: `test/CodeGen/PowerPC/swaps-le-1.ll` The codegen has changed, but the CHECK-DAG still PASS due to allowing `overlap`. This patch remove the deprecated options, and fix the broken tests. Reviewers: #powerpc, hfinkel, nemanjai, steven.zhang, shchenz Reviewed By: shchenz Subscribers: shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69733
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 | llvm/test/CodeGen/PowerPC/build-vector-tests.ll |
 | llvm/test/CodeGen/PowerPC/swaps-le-1.ll |
 | llvm/test/CodeGen/PowerPC/memcpy-vec.ll |
 | llvm/test/CodeGen/PowerPC/machine-combiner.ll |
 | llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll |
Commit
0a58ef5eb5e1a243756f649f82834281ac3dd7ff
by kparzysz[Hexagon] Require PS_aligna whenever variable-sized objects are present
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 | llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp |
Commit
67294c97fbfde6541b5f89d9d83c7fcba31c5f3b
by kparzysz[Hexagon] Handle stack realignment in hexagon-vextract
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 | llvm/lib/Target/Hexagon/HexagonVExtract.cpp |
Commit
e3eb10c5419d89171bc97ca21aba7c381827c45e
by kparzysz[Hexagon] Convert stack object offsets to int64, NFC This will print [SP-56] instead of [SP+4294967240].
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 | llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp |
Commit
592dd459242946593920911936aea47461e0faaa
by kparzysz[Hexagon] Fix vector spill expansion to use proper alignment 1. Add pseudos PS_vloadrv_ai and PS_vstorerv_ai: those are now used for single vector registers in loadRegFromStackSlot (and store...). 2. Remove pseudos PS_vloadrwu_ai and PS_vstorerwu_ai. The alignment is now checked when expanding spill pseudos (both in frame lowering and in expand-post-ra-pseudos), and a proper instruction is generated. 3. Update MachineMemOperands when dealigning vector spill slots. 4. Return vector predicate registers in getCallerSavedRegs.
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 | llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir |
 | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp |
 | llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll |
 | llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp |
 | llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp |
 | llvm/lib/Target/Hexagon/HexagonPseudo.td |