1. [DebugInfo][test] Change two MIR tests to use (details)
  2. [XRay] Set hasSideEffects flag of PATCHABLE_FUNCTION_{ENTER,EXIT} (details)
  3. [CodeGen] Move fentry-insert, xray-instrumentation and (details)
Commit 26ba1f77b55e7a961acc05d94bfa4b677a9e5d83 by maskray
[DebugInfo][test] Change two MIR tests to use
-start-before=livedebugvalues instead of -start-after=patchable-function
To break order dependency between livedebugvalues and
The file was modifiedllvm/test/DebugInfo/X86/debug-loc-asan.mir
The file was modifiedllvm/test/DebugInfo/ARM/cfi-eof-prologue.mir
Commit a72d15e37c5e066f597f13a8ba60aff214ac992d by maskray
[XRay] Set hasSideEffects flag of PATCHABLE_FUNCTION_{ENTER,EXIT}
Otherwise they may be picked as the delay slot by
mips-delay-slot-filler, if we move patchable-function before
The file was modifiedllvm/include/llvm/Target/
Commit 9a24488cb67a90f889529987275c5e411ce01dda by maskray
[CodeGen] Move fentry-insert, xray-instrumentation and
patchable-function before addPreEmitPass()
This intention is to move patchable-function before
(configured in AArch64PassConfig::addPreEmitPass) so that we emit BTI
before NOPs
This also allows addPreEmitPass() passes to know the precise instruction
sizes if they want.
Tried x86-64 Debug/Release builds of ccls with -fxray-instrument
-fxray-instruction-threshold=1. No output difference with this commit
and the previous commit.
The file was modifiedllvm/test/CodeGen/X86/O0-pipeline.ll
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/AArch64/O0-pipeline.ll
The file was modifiedllvm/test/CodeGen/X86/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was addedllvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll