Changes

[VE] setcc isel patterns
Summary: SETCC isel patterns and tests for i32/64 and fp32/64 comparison
Reviewers: arsenm, rengolin, craig.topper, k-ishizaka
Reviewed By: arsenm
Subscribers: merge_guards_bot, wdng, hiraditya, llvm-commits
Tags: #ve, #llvm
Differential Revision: https://reviews.llvm.org/D73171

[InstCombine] fneg(X + C) --> -C - X
This is 1 of the potential folds uncovered by extending D72521.
We don't seem to do this in the backend either (unless I'm not seeing
some target-specific transform).
icc and gcc (appears to be target-specific) do this transform.
Differential Revision: https://reviews.llvm.org/D73057

Unconditionally enable lvalue function designators; NFC
We previously had to guard against older MSVC and GCC versions which had
rvalue references but not support for marking functions with ref
qualifiers. However, having bumped our minimum required version to MSVC
2017 and GCC 5.1 mean we can unconditionally enable this feature. Rather
than keeping the macro around, this replaces use of the macro with the
actual ref qualifier.

AMDGPU/GlobalISel: Add pre-legalize combiner pass
Just copy the AArch64 pass as-is for now, except for removing the memcpy
handling.

AMDGPU: Do binop of select of constant fold in AMDGPUCodeGenPrepare
DAGCombiner does this, but divisions expanded here miss this 
optimization. Since 67aa18f165640374cf0e0a6226dc793bbda6e74f, divisions
have been expanded here and missed out on this optimization. Avoids test
regressions in a future patch.

AMDGPU: Look through casted selects to constant fold bin ops
The promotion of the uniform select to i32 interfered with this fold.

AMDGPU: Fix typo

[VE] select and selectcc patterns
Summary: select and selectcc isel patterns and tests for i32/i64 and
fp32/fp64. Includes optimized selectcc patterns for fmin/fmax/maxs/mins.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D73195

[lldb/Target] Sort CMakeLists (NFC)
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>

AMDGPU/GlobalISel: Fold constant offset vector extract indexes
Handle dynamic vector extracts that use an index that's an add of a 
constant offset into moving the base subregister of the indexing 
operation.
Force the add into the loop in regbankselect, which will be recognized 
when selected.

[mlir] Swap use of to_vector() with lookupValues() in LLVMIRIntrinsicGen
Summary: llvm::to_vector() accepts a Range value and not the pair of
arguments we are currently passing. Also we probably want the lowered
LLVM values in the vector, while operand_begin()/operand_end() on MLIR
ops returns MLIR types. lookupValues() seems the correct way to collect 
such values.
Reviewers: rriddle, andydavis1, antiagainst, nicolasvasilache, ftynse
Subscribers: jdoerfert, mehdi_amini, jpienaar, burmako, shauheen,
arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73137

AMDGPU/GlobalISel: Fix RegBankSelect for G_INSERT_VECTOR_ELT
The result and source vector are going to be tied, so these need to be 
the same bank.
The inserted value also needs to be broken down based on the result 
bank, not the inserted value itself.

AMDGPU/GlobalISel: Select G_INSERT_VECTOR_ELT

[compiler-rt] [builtins] Fix clear_cache_test to work with MPROTECT
Fix clear_cache_test to work on NetBSD with PaX MPROTECT enabled, that 
is when creating W+X mmaps is prohibited.  Use the recommended solution: 
create two mappings for the same memory area, make one of them RW, while 
the other RX.  Copy the function into the RW area but run it from the RX 
area.
In order to implement this, I've split the pointer variables to
'write_buffer' and 'execution_buffer'.  Both are separate pointers on
NetBSD, while they have the same value on other systems.
I've also split the memcpy_f() into two: new memcpy_f() that only takes 
care of copying memory and discards the (known) result of memcpy(), and
realign_f() that applies ARM realignment to the given pointer. Again,
there should be no difference on non-NetBSD systems but on NetBSD 
copying is done on write_buffer, while realignment on pointer to the
execution_buffer.
I have tested this change on NetBSD and Linux.
Differential Revision: https://reviews.llvm.org/D72578

[gn build] (manually) port a174f0da62f

AMDGPU/GlobalISel: Fold add of constant into G_INSERT_VECTOR_ELT
Move the subregister base like in the extract case.

[X86][SSE] combineExtractWithShuffle -
extract(bictcast(scalar_to_vector(x))) --> x
Removes some unnecessary gpr<-->fpu traffic

[RISCV] Support ABI checking with per function target-features
1. if users don't specific -mattr, the default target-feature come from
IR attribute. 2. fixed bug and re-land this patch
Reviewers: lenary, asb
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70837

AMDGPU/GlobalISel: Keep G_BITCAST out of waterfall loop
The waterfall utility function blindly inserts a phi for every def in 
the loop. We don't need this one to be preserved for every iteration.
Saves an extra phi and copy inside the loop body.

AMDGPU: Fix element size assertion
The GlobalISel usage called this with bits, but the DAG usage was 
incorrectly using bytes.

[AArch64] Add test for DWARF return address signing
Summary: Patch by LukeCheeseman and pbarrio
Reviewers: samparker, chill
Subscribers: kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72835

[PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst.
Summary: Without the BFI update, some hot blocks are incorrectly treated
as cold code.
This fixes a FDO perf regression in the TSVC benchmark from D71288.
Reviewers: davidxl
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73146

AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp8

AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp
This is deprecated, but easy to support.

Regenerate test/CodeGen/ARM/vext.ll. NFC.
This is to pre-commit whitespace only changes before D73132.

Precommit NFC part of DAGCombiner change. NFC.
This is NFC part of DAGCombiner::visitEXTRACT_SUBVECTOR() change in the
D73132.

[NFC][XCOFF] Refactor Csect creation into TargetLoweringObjectFile
Summary: We create a number of standard types of control sections in
multiple places for things like the function descriptors, external
references and the TOC anchor among others, so it is possible for  their
properties to be defined inconsistently in different places. This
refactor moves their creation and properties into functions in the
TargetLoweringObjectFile class hierarchy, where functions for retrieving
various special types of sections typically seem to reside.
Note: There is one case in PPCISelLowering which is specific to function
entry points which we don't address since we don't have access to the
TLOF there.
Reviewers: DiggerLin, jasonliu, hubert.reinterpretcast
Reviewed By: jasonliu, hubert.reinterpretcast
Subscribers: wuzish, nemanjai, hiraditya, kbarton, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72347

AMDGPU/GlobalISel: Handle 16-bank LDS llvm.amdgcn.interp.p1.f16
The pattern is also mishandled by the generated matcher, so workaround 
this as in the DAG path.
The existing DAG tests aren't particularly targeted to just this one 
intrinsic. These also end up differing in scheduling from SGPR->VGPR 
operand constraint copies.

[AArch64] Don't rename registers with pseudo defs in Ld/St opt.
If the root def of for renaming is a noop-pseudo instruction like kill, 
we would end up without a correct def for the renamed register, causing 
miscompiles.
This patch conservatively bails out on any pseudo instruction.
This fixes
https://bugs.chromium.org/p/chromium/issues/detail?id=1037912#c70

[gn build] [win] produce symbolized stack frames in release builds too

Revert "Unconditionally enable lvalue function designators; NFC"
This reverts commit 968561bcdc34c7d74482fe3bb69a045abf08d2c1

[scudo][standalone] Reduce Android region sizes to 128MB
Summary: Unity is making irresponsible assumptions as to how clumped up
memory should be. With larger regions, we break those, resulting in
errors like:
"Using memoryadresses from more that 16GB of memory"
This is unfortunately one of those situations where we have to bend to 
existing code because we doubt it's going to change any time soon.
128MB should be enough, but we could be flirting with OOMs in the higher
class sizes.
Reviewers: cferris, eugenis, hctim, morehouse, pcc
Subscribers: #sanitizers, llvm-commits
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D73143

[Flang] add some cmake code to allow for out-of-tree building of MLIR
and LLVM
Differential Revision: https://reviews.llvm.org/D72418

Revert "[gn build] [win] produce symbolized stack frames in release
builds too"
This reverts commit fd98eccf984f203e39452da238a142f83f61d368. Seems to
have no effect, need to try it locally for a bit first.

Revert "[DA][TTI][AMDGPU] Add option to select GPUDA with TTI"
This reverts commit a90a6502ab35d3c15c7d56772e409c5632ce6cfb. Broke
tests on Windows:
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/13808

[ARM] Mark MVE loads/store as not having side effects
The hasSideEffect parameter is usually automatically inferred from 
instruction patterns. For some of our MVE instructions, we do not have 
patterns though, such as for the pre/post inc loads and stores. This 
instead specifies the flag manually on the base MVE_VLDRSTR_base 
tablegen class, making sure we get this correct.
This can help with scheduling multiple loads more optimally. Here I've 
added a unittest as a more direct form of testing.
Differential Revision: https://reviews.llvm.org/D73117

[X86][SSE] combineExtractWithShuffle - extract(bitcast(broadcast(x)))
--> x
Removes some unnecessary gpr<-->fpu traffic

[CMake][Fuchsia] Disable in-process cc1
The in-process cc1 currently breaks Goma client and therefore prevents 
the use of tip-of-tree Clang with Goma, so we disable the in-process cc1 
in our toolchain until this issue is resolved.

Add a comment about when we can remove this construct; NFC.

[Concepts] Fix bug when referencing function parameters in instantiated
function template requires clause
Fixes bug #44613 - incorrect instantiated parameters were being added
when checking instantiated function constraints

[gn build] reformat all build files again
Run `git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format` 
after recent fixes to formatting of comments after single-element lists.

Add LLVM_VALUE_FUNCTION to Optional::map(); NFC
This is for future-proofing when compiling with MSVC once we drop
support for 2017.

AMDGPU/R600: Emit rodata in text segment
R600 relies on this behaviour. Fixes:
6e18266aa4dd78953557b8614cb9ff260bad7c65 ('Partially revert D61491
"AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET
is 0"') Fixes ~100 piglit regressions since 6e18266
Differential Revision: https://reviews.llvm.org/D72991

[mlir] Add baseAttr to TypedArrayAttrBase.
Element type is useful in code generators but it is lost after
construction.
Differential Revision: https://reviews.llvm.org/D72888

[LoopDeletion] Teach LoopDeletion to preserve MemorySSA if available.
If MemorySSA analysis is analysis, LoopDeletion now preserves it.

Add a bit of documentation on attribute spellings that were missing.

Extend misc-misplaced-const to detect using declarations as well as
typedef