Changes

Summary

  1. [VE] setcc isel patterns (details)
  2. [InstCombine] fneg(X + C) --> -C - X (details)
  3. Unconditionally enable lvalue function designators; NFC (details)
  4. AMDGPU/GlobalISel: Add pre-legalize combiner pass (details)
  5. AMDGPU: Do binop of select of constant fold in AMDGPUCodeGenPrepare (details)
  6. AMDGPU: Look through casted selects to constant fold bin ops (details)
  7. AMDGPU: Fix typo (details)
  8. [VE] select and selectcc patterns (details)
  9. [lldb/Target] Sort CMakeLists (NFC) (details)
  10. AMDGPU/GlobalISel: Fold constant offset vector extract indexes (details)
  11. [mlir] Swap use of to_vector() with lookupValues() in LLVMIRIntrinsicGen (details)
  12. AMDGPU/GlobalISel: Fix RegBankSelect for G_INSERT_VECTOR_ELT (details)
  13. AMDGPU/GlobalISel: Select G_INSERT_VECTOR_ELT (details)
  14. [compiler-rt] [builtins] Fix clear_cache_test to work with MPROTECT (details)
  15. [gn build] (manually) port a174f0da62f (details)
  16. AMDGPU/GlobalISel: Fold add of constant into G_INSERT_VECTOR_ELT (details)
  17. [X86][SSE] combineExtractWithShuffle - (details)
  18. [RISCV] Support ABI checking with per function target-features (details)
  19. AMDGPU/GlobalISel: Keep G_BITCAST out of waterfall loop (details)
  20. AMDGPU: Fix element size assertion (details)
  21. [AArch64] Add test for DWARF return address signing (details)
  22. [PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst. (details)
  23. AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp8 (details)
  24. AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp (details)
  25. Regenerate test/CodeGen/ARM/vext.ll. NFC. (details)
  26. Precommit NFC part of DAGCombiner change. NFC. (details)
  27. [NFC][XCOFF] Refactor Csect creation into TargetLoweringObjectFile (details)
  28. AMDGPU/GlobalISel: Handle 16-bank LDS llvm.amdgcn.interp.p1.f16 (details)
  29. [AArch64] Don't rename registers with pseudo defs in Ld/St opt. (details)
  30. [gn build] [win] produce symbolized stack frames in release builds too (details)
  31. Revert "Unconditionally enable lvalue function designators; NFC" (details)
  32. [scudo][standalone] Reduce Android region sizes to 128MB (details)
  33. [Flang] add some cmake code to allow for out-of-tree building of MLIR (details)
  34. Revert "[gn build] [win] produce symbolized stack frames in release (details)
  35. Revert "[DA][TTI][AMDGPU] Add option to select GPUDA with TTI" (details)
  36. [ARM] Mark MVE loads/store as not having side effects (details)
  37. [X86][SSE] combineExtractWithShuffle - extract(bitcast(broadcast(x))) (details)
  38. [CMake][Fuchsia] Disable in-process cc1 (details)
  39. Add a comment about when we can remove this construct; NFC. (details)
  40. [Concepts] Fix bug when referencing function parameters in instantiated (details)
  41. [gn build] reformat all build files again (details)
  42. Add LLVM_VALUE_FUNCTION to Optional::map(); NFC (details)
  43. AMDGPU/R600: Emit rodata in text segment (details)
  44. [mlir] Add baseAttr to TypedArrayAttrBase. (details)
  45. [LoopDeletion] Teach LoopDeletion to preserve MemorySSA if available. (details)
  46. Add a bit of documentation on attribute spellings that were missing. (details)
  47. Extend misc-misplaced-const to detect using declarations as well as (details)
Commit dc69265eea888e8c6255aebcdd6650420dd00cfb by simon.moll
[VE] setcc isel patterns
Summary: SETCC isel patterns and tests for i32/64 and fp32/64 comparison
Reviewers: arsenm, rengolin, craig.topper, k-ishizaka
Reviewed By: arsenm
Subscribers: merge_guards_bot, wdng, hiraditya, llvm-commits
Tags: #ve, #llvm
Differential Revision: https://reviews.llvm.org/D73171
The file was addedllvm/test/CodeGen/VE/setccf32.ll
The file was addedllvm/test/CodeGen/VE/setcci32i.ll
The file was modifiedllvm/lib/Target/VE/VEISelLowering.cpp
The file was addedllvm/test/CodeGen/VE/setccf64i.ll
The file was addedllvm/test/CodeGen/VE/setcci64.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was addedllvm/test/CodeGen/VE/setccf64.ll
The file was addedllvm/test/CodeGen/VE/setcci64i.ll
The file was addedllvm/test/CodeGen/VE/setccf32i.ll
The file was addedllvm/test/CodeGen/VE/setcci32.ll
Commit 0ade2abdb01f4a16b1f08d1a78d664b9e9d5f3b5 by spatel
[InstCombine] fneg(X + C) --> -C - X
This is 1 of the potential folds uncovered by extending D72521.
We don't seem to do this in the backend either (unless I'm not seeing
some target-specific transform).
icc and gcc (appears to be target-specific) do this transform.
Differential Revision: https://reviews.llvm.org/D73057
The file was modifiedllvm/test/Transforms/InstCombine/fneg.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
Commit 968561bcdc34c7d74482fe3bb69a045abf08d2c1 by aaron
Unconditionally enable lvalue function designators; NFC
We previously had to guard against older MSVC and GCC versions which had
rvalue references but not support for marking functions with ref
qualifiers. However, having bumped our minimum required version to MSVC
2017 and GCC 5.1 mean we can unconditionally enable this feature. Rather
than keeping the macro around, this replaces use of the macro with the
actual ref qualifier.
The file was modifiedllvm/include/llvm/ADT/Optional.h
The file was modifiedllvm/include/llvm/ADT/PointerIntPair.h
The file was modifiedllvm/unittests/ADT/OptionalTest.cpp
The file was modifiedclang/include/clang/StaticAnalyzer/Core/PathSensitive/ExplodedGraph.h
The file was modifiedllvm/include/llvm/Support/Compiler.h
Commit a174f0da62f1cad36d21c040bf37bfdd291b28cf by arsenm2
AMDGPU/GlobalISel: Add pre-legalize combiner pass
Just copy the AArch64 pass as-is for now, except for removing the memcpy
handling.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/CMakeLists.txt
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
The file was addedllvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was addedllvm/lib/Target/AMDGPU/AMDGPUCombine.td
Commit bcd91778fe7e6fc66cdccc5ddc3ff3fc48909f6b by arsenm2
AMDGPU: Do binop of select of constant fold in AMDGPUCodeGenPrepare
DAGCombiner does this, but divisions expanded here miss this
optimization. Since 67aa18f165640374cf0e0a6226dc793bbda6e74f, divisions
have been expanded here and missed out on this optimization. Avoids test
regressions in a future patch.
The file was addedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/dagcombine-select.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
Commit 2fe500ab5bb4d50a5ac6ed9600f9900b46e55802 by arsenm2
AMDGPU: Look through casted selects to constant fold bin ops
The promotion of the uniform select to i32 interfered with this fold.
The file was modifiedllvm/test/CodeGen/AMDGPU/dagcombine-select.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
Commit e93e1b621c4dc5c05614ccef3a19748683751f9a by arsenm2
AMDGPU: Fix typo
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
Commit 83b67526d5c2ba070996697e73e8954776986303 by simon.moll
[VE] select and selectcc patterns
Summary: select and selectcc isel patterns and tests for i32/i64 and
fp32/fp64. Includes optimized selectcc patterns for fmin/fmax/maxs/mins.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D73195
The file was addedllvm/test/CodeGen/VE/selectcci64.ll
The file was addedllvm/test/CodeGen/VE/selectccf64.ll
The file was addedllvm/test/CodeGen/VE/selectcci32c.ll
The file was addedllvm/test/CodeGen/VE/selectccf64i.ll
The file was addedllvm/test/CodeGen/VE/selectcci32.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was addedllvm/test/CodeGen/VE/select.ll
The file was addedllvm/test/CodeGen/VE/selectccf64c.ll
The file was addedllvm/test/CodeGen/VE/min.ll
The file was addedllvm/test/CodeGen/VE/selectccf32i.ll
The file was addedllvm/test/CodeGen/VE/max.ll
The file was addedllvm/test/CodeGen/VE/selectcci64i.ll
The file was addedllvm/test/CodeGen/VE/selectccf32.ll
The file was addedllvm/test/CodeGen/VE/selectccf32c.ll
The file was addedllvm/test/CodeGen/VE/selectcci32i.ll
The file was addedllvm/test/CodeGen/VE/selectcci64c.ll
Commit 9dc9f7ca145e7fd5fafbdf071a2e5b5914918c04 by medismail.bennani
[lldb/Target] Sort CMakeLists (NFC)
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/source/Target/CMakeLists.txt
Commit e3d352c54119b5d30821b4857dec77ac0af688c8 by arsenm2
AMDGPU/GlobalISel: Fold constant offset vector extract indexes
Handle dynamic vector extracts that use an index that's an add of a
constant offset into moving the base subregister of the indexing
operation.
Force the add into the loop in regbankselect, which will be recognized
when selected.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 04a151710e8b04ca4c8e74782ceaadfe7ceca90c by hayarms
[mlir] Swap use of to_vector() with lookupValues() in LLVMIRIntrinsicGen
Summary: llvm::to_vector() accepts a Range value and not the pair of
arguments we are currently passing. Also we probably want the lowered
LLVM values in the vector, while operand_begin()/operand_end() on MLIR
ops returns MLIR types. lookupValues() seems the correct way to collect
such values.
Reviewers: rriddle, andydavis1, antiagainst, nicolasvasilache, ftynse
Subscribers: jdoerfert, mehdi_amini, jpienaar, burmako, shauheen,
arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73137
The file was modifiedmlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
The file was modifiedmlir/test/mlir-tblgen/llvm-intrinsics.td
Commit 3524d4412cffd5ad2c05c017964719e9f96d4382 by arsenm2
AMDGPU/GlobalISel: Fix RegBankSelect for G_INSERT_VECTOR_ELT
The result and source vector are going to be tied, so these need to be
the same bank.
The inserted value also needs to be broken down based on the result
bank, not the inserted value itself.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
Commit d1dbb5e4718a8f845abf0783513a33a55429470b by arsenm2
AMDGPU/GlobalISel: Select G_INSERT_VECTOR_ELT
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
Commit 3215f7c7a81ffc7e6c0e49b21a4d4a01a2d945be by mgorny
[compiler-rt] [builtins] Fix clear_cache_test to work with MPROTECT
Fix clear_cache_test to work on NetBSD with PaX MPROTECT enabled, that
is when creating W+X mmaps is prohibited.  Use the recommended solution:
create two mappings for the same memory area, make one of them RW, while
the other RX.  Copy the function into the RW area but run it from the RX
area.
In order to implement this, I've split the pointer variables to
'write_buffer' and 'execution_buffer'.  Both are separate pointers on
NetBSD, while they have the same value on other systems.
I've also split the memcpy_f() into two: new memcpy_f() that only takes
care of copying memory and discards the (known) result of memcpy(), and
realign_f() that applies ARM realignment to the given pointer. Again,
there should be no difference on non-NetBSD systems but on NetBSD
copying is done on write_buffer, while realignment on pointer to the
execution_buffer.
I have tested this change on NetBSD and Linux.
Differential Revision: https://reviews.llvm.org/D72578
The file was modifiedcompiler-rt/test/builtins/Unit/clear_cache_test.c
Commit 349f6bb873df600b30b0cb2a51c940c0b9a46fb3 by thakis
[gn build] (manually) port a174f0da62f
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Commit 52ec7379adfa27b24f834551a2b3bf2b7249549c by arsenm2
AMDGPU/GlobalISel: Fold add of constant into G_INSERT_VECTOR_ELT
Move the subregister base like in the extract case.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit a14aa7dabde3e985c6ae3d89fd86c6be788c4b90 by llvm-dev
[X86][SSE] combineExtractWithShuffle -
extract(bictcast(scalar_to_vector(x))) --> x
Removes some unnecessary gpr<-->fpu traffic
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-v2i32.ll
The file was modifiedllvm/test/CodeGen/X86/scalar_widen_div.ll
The file was modifiedllvm/test/CodeGen/X86/oddsubvector.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/bitcast-vector-bool.ll
The file was modifiedllvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
Commit 0cb274de397a193fb37c60653b336d48a3a4f1bd by zakk.chen
[RISCV] Support ABI checking with per function target-features
1. if users don't specific -mattr, the default target-feature come from
IR attribute. 2. fixed bug and re-land this patch
Reviewers: lenary, asb
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70837
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit bb562d1af0e9f959eceb8b41cc5530202d55731a by arsenm2
AMDGPU/GlobalISel: Keep G_BITCAST out of waterfall loop
The waterfall utility function blindly inserts a phi for every def in
the loop. We don't need this one to be preserved for every iteration.
Saves an extra phi and copy inside the loop body.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 0bf434ccd5627c385af96ef7a456294f195cca43 by arsenm2
AMDGPU: Fix element size assertion
The GlobalISel usage called this with bits, but the DAG usage was
incorrectly using bytes.
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit a8ff6c0b09718a048ec9b9fc7db33fd39f6500cc by pablo.barrio
[AArch64] Add test for DWARF return address signing
Summary: Patch by LukeCheeseman and pbarrio
Reviewers: samparker, chill
Subscribers: kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72835
The file was addedllvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
Commit ddbc728828c70728473b47c9f7427aa9514f3d17 by yamauchi
[PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst.
Summary: Without the BFI update, some hot blocks are incorrectly treated
as cold code.
This fixes a FDO perf regression in the TSVC benchmark from D71288.
Reviewers: davidxl
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73146
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was modifiedllvm/test/CodeGen/X86/cmov-into-branch.ll
Commit dd09ec1208bd93a42cece7abd31fc5e31f1b76d8 by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp8
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp8.ll
Commit c05f23e409a7613a884de6ef89170e13931a697b by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp
This is deprecated, but easy to support.
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit fb8a3d18340e0b5c2266a84d6a5158f5cd8bc9a2 by Stanislav.Mekhanoshin
Regenerate test/CodeGen/ARM/vext.ll. NFC.
This is to pre-commit whitespace only changes before D73132.
The file was modifiedllvm/test/CodeGen/ARM/vext.ll
Commit 2d0fcf786c5c7f384e30a955d2e7da46d1f98949 by Stanislav.Mekhanoshin
Precommit NFC part of DAGCombiner change. NFC.
This is NFC part of DAGCombiner::visitEXTRACT_SUBVECTOR() change in the
D73132.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 45a4aaea7fdf21a139b35ad6d25f6c4a150e065f by daltenty
[NFC][XCOFF] Refactor Csect creation into TargetLoweringObjectFile
Summary: We create a number of standard types of control sections in
multiple places for things like the function descriptors, external
references and the TOC anchor among others, so it is possible for  their
properties to be defined inconsistently in different places. This
refactor moves their creation and properties into functions in the
TargetLoweringObjectFile class hierarchy, where functions for retrieving
various special types of sections typically seem to reside.
Note: There is one case in PPCISelLowering which is specific to function
entry points which we don't address since we don't have access to the
TLOF there.
Reviewers: DiggerLin, jasonliu, hubert.reinterpretcast
Reviewed By: jasonliu, hubert.reinterpretcast
Subscribers: wuzish, nemanjai, hiraditya, kbarton, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72347
The file was modifiedllvm/include/llvm/MC/MCObjectFileInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modifiedllvm/include/llvm/Target/TargetLoweringObjectFile.h
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
The file was modifiedllvm/lib/MC/MCObjectFileInfo.cpp
Commit 1192d7b254722932465461214b5491e7463d33cd by arsenm2
AMDGPU/GlobalISel: Handle 16-bank LDS llvm.amdgcn.interp.p1.f16
The pattern is also mishandled by the generated matcher, so workaround
this as in the DAG path.
The existing DAG tests aren't particularly targeted to just this one
intrinsic. These also end up differing in scheduling from SGPR->VGPR
operand constraint copies.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.p1.f16.ll
Commit 300997c41a00b705ca10264c15910dd8d691ab75 by florian_hahn
[AArch64] Don't rename registers with pseudo defs in Ld/St opt.
If the root def of for renaming is a noop-pseudo instruction like kill,
we would end up without a correct def for the renamed register, causing
miscompiles.
This patch conservatively bails out on any pseudo instruction.
This fixes
https://bugs.chromium.org/p/chromium/issues/detail?id=1037912#c70
The file was modifiedllvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
Commit fd98eccf984f203e39452da238a142f83f61d368 by thakis
[gn build] [win] produce symbolized stack frames in release builds too
The file was modifiedllvm/utils/gn/build/BUILD.gn
Commit dfe9f130e07c929d21f8122272077495de531a38 by aaron
Revert "Unconditionally enable lvalue function designators; NFC"
This reverts commit 968561bcdc34c7d74482fe3bb69a045abf08d2c1
The file was modifiedllvm/include/llvm/Support/Compiler.h
The file was modifiedllvm/unittests/ADT/OptionalTest.cpp
The file was modifiedclang/include/clang/StaticAnalyzer/Core/PathSensitive/ExplodedGraph.h
The file was modifiedllvm/include/llvm/ADT/PointerIntPair.h
The file was modifiedllvm/include/llvm/ADT/Optional.h
Commit 990acd450cf198cc6a82a28e011fa602e44512ad by kostyak
[scudo][standalone] Reduce Android region sizes to 128MB
Summary: Unity is making irresponsible assumptions as to how clumped up
memory should be. With larger regions, we break those, resulting in
errors like:
"Using memoryadresses from more that 16GB of memory"
This is unfortunately one of those situations where we have to bend to
existing code because we doubt it's going to change any time soon.
128MB should be enough, but we could be flirting with OOMs in the higher
class sizes.
Reviewers: cferris, eugenis, hctim, morehouse, pcc
Subscribers: #sanitizers, llvm-commits
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D73143
The file was modifiedcompiler-rt/lib/scudo/standalone/allocator_config.h
Commit 5114d55dde49a02e0721448107d6391e0275ee71 by aminim
[Flang] add some cmake code to allow for out-of-tree building of MLIR
and LLVM
Differential Revision: https://reviews.llvm.org/D72418
The file was addedmlir/cmake/modules/AddMLIR.cmake
The file was addedmlir/cmake/modules/CMakeLists.txt
The file was modifiedmlir/CMakeLists.txt
Commit bfcfa53c3df6857b6bcf4bfa7f811ab84444e6bb by thakis
Revert "[gn build] [win] produce symbolized stack frames in release
builds too"
This reverts commit fd98eccf984f203e39452da238a142f83f61d368. Seems to
have no effect, need to try it locally for a bit first.
The file was modifiedllvm/utils/gn/build/BUILD.gn
Commit cd470717d15854fb778f2c96667ba36672af6cf5 by thakis
Revert "[DA][TTI][AMDGPU] Add option to select GPUDA with TTI"
This reverts commit a90a6502ab35d3c15c7d56772e409c5632ce6cfb. Broke
tests on Windows:
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/13808
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/include/llvm/Analysis/LegacyDivergenceAnalysis.h
The file was modifiedllvm/lib/Analysis/LegacyDivergenceAnalysis.cpp
Commit 58991ba773774f7dbdf2844a737845298e9e71bb by david.green
[ARM] Mark MVE loads/store as not having side effects
The hasSideEffect parameter is usually automatically inferred from
instruction patterns. For some of our MVE instructions, we do not have
patterns though, such as for the pre/post inc loads and stores. This
instead specifies the flag manually on the base MVE_VLDRSTR_base
tablegen class, making sure we get this correct.
This can help with scheduling multiple loads more optimally. Here I've
added a unittest as a more direct form of testing.
Differential Revision: https://reviews.llvm.org/D73117
The file was modifiedllvm/unittests/Target/ARM/MachineInstrTest.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
Commit 5340434c94c4c48abf755d12b2c3a19ca46fabaa by llvm-dev
[X86][SSE] combineExtractWithShuffle - extract(bitcast(broadcast(x)))
--> x
Removes some unnecessary gpr<-->fpu traffic
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/bitcast-vector-bool.ll
Commit 635cbef5056e069679a25b75faf25ed27adf6a48 by phosek
[CMake][Fuchsia] Disable in-process cc1
The in-process cc1 currently breaks Goma client and therefore prevents
the use of tip-of-tree Clang with Goma, so we disable the in-process cc1
in our toolchain until this issue is resolved.
The file was modifiedclang/cmake/caches/Fuchsia-stage2.cmake
Commit 1e4764e1032447d9340468b28cae325385ddcd44 by aaron
Add a comment about when we can remove this construct; NFC.
The file was modifiedllvm/include/llvm/Support/Compiler.h
Commit c2a250e1c43c05925fe040dc9624403af7879453 by saar
[Concepts] Fix bug when referencing function parameters in instantiated
function template requires clause
Fixes bug #44613 - incorrect instantiated parameters were being added
when checking instantiated function constraints
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/test/SemaTemplate/instantiate-requires-clause.cpp
Commit 8f21acbf52bb7412df3a68e3868ef11abfaf7385 by thakis
[gn build] reformat all build files again
Run `git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format`
after recent fixes to formatting of comments after single-element lists.
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/test/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang/test/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/lld/test/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/compiler-rt/test/hwasan/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/test/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/test/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/utils/benchmark/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Commit 90cfbb81674ecd38030e2656acaed4f3c39b5e62 by aaron
Add LLVM_VALUE_FUNCTION to Optional::map(); NFC
This is for future-proofing when compiling with MSVC once we drop
support for 2017.
The file was modifiedllvm/include/llvm/ADT/Optional.h
Commit 1b8eab179db46f25a267bb73c657009c0bb542cc by jano.vesely
AMDGPU/R600: Emit rodata in text segment
R600 relies on this behaviour. Fixes:
6e18266aa4dd78953557b8614cb9ff260bad7c65 ('Partially revert D61491
"AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET
is 0"') Fixes ~100 piglit regressions since 6e18266
Differential Revision: https://reviews.llvm.org/D72991
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/global-constant.ll
Commit eec36909c18b8788773abc95d199e6acde6eb42c by aminim
[mlir] Add baseAttr to TypedArrayAttrBase.
Element type is useful in code generators but it is lost after
construction.
Differential Revision: https://reviews.llvm.org/D72888
The file was modifiedmlir/include/mlir/IR/OpBase.td
Commit efb130fc93059bdf02d3a83950ddabc5d119f9de by asbirlea
[LoopDeletion] Teach LoopDeletion to preserve MemorySSA if available.
If MemorySSA analysis is analysis, LoopDeletion now preserves it.
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedllvm/include/llvm/Transforms/Utils/LoopUtils.h
The file was modifiedllvm/lib/Transforms/Scalar/LoopDeletion.cpp
Commit 8edf037aebdf473c225dffe23d5f96c6de429294 by aaron
Add a bit of documentation on attribute spellings that were missing.
The file was modifiedclang/docs/InternalsManual.rst
Commit 84c5f196370065388779cd96d033c84d31031543 by aaron
Extend misc-misplaced-const to detect using declarations as well as
typedef
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/misc-misplaced-const.cpp
The file was modifiedclang-tools-extra/clang-tidy/misc/MisplacedConstCheck.cpp
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/misc-misplaced-const.rst
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/misc-misplaced-const.c