Changes

Summary

[DAGCombine] visitEXTRACT_VECTOR_ELT - add SimplifyDemandedBits multi use support (details)
[clang][analyzer] Modify include AllocationState.h in PutenvWithAutoChecker.cpp (details)
[X86] Add DAG combines to form CVTPH2PS/CVTPS2PH from vXf16->vXf32/vXf64 fp_extends and vXf32->vXf16 fp_round. (details)
[AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations (details)
[x86] add vector tests for splatted memory ops; NFC (details)
[AArch64] Move isOverflowIntrOpRes help function to the ISD namespace in SelectionDAG.h. NFC (details)
[X86] Rewrite LowerBRCOND to remove dead code and handle ISD::SETCC and overflow ops directly. (details)
[libc++] Fix unintended ADL inside ref(reference_wrapper<T>) and cref(reference_wrapper<T>) (details)
[libc++] Fix unqualified call to 'ref' inside shared_ptr(unique_ptr<U, D>) (details)
[clang-tidy] rename_check.py: maintain alphabetical order in Renamed checks section (details)
[X86] Fix a -Wparentheses warning. NFC (details)
[clang] Fix search path logic for C_INCLUDE_DIRS (details)
Add target.xml support for qXfer request. (details)
[lldb] Fix version string when using LLDB_REVISION but not LLDB_REPOSITORY (details)
[DAGCombiner] Use SDValue::getConstantOperandAPInt helper where possible. NFC. (details)
[macho][NFC] Extract all CPU_(SUB_)TYPE logic to libObject (details)
[mlir] Refactor the structure of the 'verifyConstructionInvariants' methods. (details)
Revert "[macho][NFC] Extract all CPU_(SUB_)TYPE logic to libObject" (details)
[PowerPC][NFC] Cleanup some of the Darwin mentions in the README.txt. (details)
[x86] allow peeking through an extract_subvector to find a splatted operand (details)
[libc] Add Initial Support for Signals (details)

Commit fc2b4a02b1a82c40ac1459cd15b9911ebfc78acc by llvm-dev [DAGCombine] visitEXTRACT_VECTOR_ELT - add SimplifyDemandedBits multi use support Similar to what we already do with SimplifyDemandedVectorElts, call SimplifyDemandedBits across all the extracted elements of the source vector, treating it as single use. There's a minor regression in store-weird-sizes.ll which will be addressed in an upcoming SimplifyDemandedBits patch.
	llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
	llvm/test/CodeGen/X86/psadbw.ll
	llvm/test/CodeGen/X86/vector-reduce-mul.ll
	llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
	llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
	llvm/test/CodeGen/AMDGPU/idot4s.ll
	llvm/test/CodeGen/AMDGPU/idot4u.ll
	llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
	llvm/test/CodeGen/AMDGPU/idot8s.ll
Commit cb54c13c217b3e5fcda5c97bab229c1f9c3934b7 by usx [clang][analyzer] Modify include AllocationState.h in PutenvWithAutoChecker.cpp Summary: PutenvWithAutoChecker.cpp used to include "AllocationState.h" that is present in project root. This makes build systems like blaze unhappy. Made it include the header relative to source file. Reviewers: kadircet Subscribers: xazax.hun, baloghadamsoftware, szepet, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, Charusso, martong, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D74906
	clang/lib/StaticAnalyzer/Checkers/cert/PutenvWithAutoChecker.cpp
Commit 12cc105f806f5a7e7c14350c5ba54654e263c972 by craig.topper [X86] Add DAG combines to form CVTPH2PS/CVTPS2PH from vXf16->vXf32/vXf64 fp_extends and vXf32->vXf16 fp_round. Only handle power of 2 element count for simplicity. Not sure what to do with vXf64->vXf16 fp_round to avoid double rounding Differential Revision: https://reviews.llvm.org/D74886
	llvm/test/CodeGen/X86/half.ll
	llvm/test/CodeGen/X86/vector-half-conversions.ll
	llvm/lib/Target/X86/X86ISelLowering.cpp
Commit ce70e2899879e092b153a4078b993833b6696713 by danilo.carvalho.grael [AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations Summary: Add intrinsics for the following operations: - eor3, bcax - bsl, bsl1n, bsl2n, nbsl Reviewers: kmclaughlin, c-rhodes, sdesmalen, efriedma, rengolin Reviewed By: efriedma Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74785
	llvm/include/llvm/IR/IntrinsicsAArch64.td
	llvm/lib/Target/AArch64/SVEInstrFormats.td
	llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
	llvm/test/CodeGen/AArch64/sve2-bitwise-ternary.ll
Commit 914a97a4e6184234ea231321c3073e021e0c60c7 by spatel [x86] add vector tests for splatted memory ops; NFC These correspond to patterns seen in PR42024: https://bugs.llvm.org/show_bug.cgi?id=42024
	llvm/test/CodeGen/X86/x86-interleaved-access.ll
Commit 9bbf271fc9d5b84f9e657805dfff0fb8a1607af4 by craig.topper [AArch64] Move isOverflowIntrOpRes help function to the ISD namespace in SelectionDAG.h. NFC Enables sharing with an upcoming X86 change.
	llvm/include/llvm/CodeGen/SelectionDAGNodes.h
	llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 3543ac9ab52df77af55a2ebdeeddfb76aba15d29 by craig.topper [X86] Rewrite LowerBRCOND to remove dead code and handle ISD::SETCC and overflow ops directly. There's a lot of old leftover code in LowerBRCOND. Especially the detecting or AND or OR of X86ISD::SETCC nodes. Those were needed before LegalizeDAG was changed to visit nodes before their operands. It also relied on reversing the output of LowerSETCC to find the flags producing node to use for the X86ISD::BRCOND node. Rather than using LowerSETCC this patch uses emitFlagsForSetcc to handle the integer ISD::SETCC case. This gives the flag producer and the comparison code to use directly. I've removed the addTest flag and just produce a X86ISD::BRCOND and return immediately. Floating point ISD::SETCC case is just an X86ISD::FCMP with special care for OEQ and UNE derived from the previous code. I've left f128 out so it will emit a test. And LowerSETCC will be called later to produce a libcall and X86ISD::SETCC. We have combines that can merge the test and X86ISD::SETCC. We need to handle two cases for overflow ops. Either they are used directly or they have a seteq 0 or setne 1 to invert the overflow. The old code did not handle the setne 1 case, but I think some other combines were making up for it. If we fail to find a condition, we'll wrap an AND with 1 on the original condition and tell emitFlagsForSetcc to emit a compare with 0. This will pickup the LowerAndToBT and or the EmitTest case. I kept the isTruncWithZeroHighBitsInput call, but we might be able to fold that in to emitFlagsForSetcc. Differential Revision: https://reviews.llvm.org/D74750
	llvm/lib/Target/X86/X86ISelLowering.cpp
Commit e442f38395f71b680bc1174568e461b5ff1f7ebf by Louis Dionne [libc++] Fix unintended ADL inside ref(reference_wrapper<T>) and cref(reference_wrapper<T>) This patch qualifies calls to ref and cref inside ref(reference_wrapper<T>) and cref(reference_wrapper<T>), respectively. These previously unqualified calls could break in the presence of user functions called ref/cref inside associated namespaces: https://gcc.godbolt.org/z/8VfprT Fixes PR44398. Differential Revision: https://reviews.llvm.org/D74287
	libcxx/test/std/utilities/function.objects/refwrap/refwrap.helpers/cref_2.pass.cpp
	libcxx/include/__functional_base
	libcxx/test/std/utilities/function.objects/refwrap/refwrap.helpers/ref_2.pass.cpp
Commit 092a57f5082146b6770f89839666b7545a0d27f0 by Louis Dionne [libc++] Fix unqualified call to 'ref' inside shared_ptr(unique_ptr<U, D>) This prevents unintended ADL: https://gcc.godbolt.org/z/EHw3Gy This issue was mentioned as an addendum in PR44398. Differential Revision: https://reviews.llvm.org/D74289
	libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.shared/util.smartptr.shared.const/unique_ptr.pass.cpp
	libcxx/include/memory
Commit db8911aad726d050fb36f17f2978bd35f69165cc by n.james93 [clang-tidy] rename_check.py: maintain alphabetical order in Renamed checks section Summary: Also use //check// in add_new_check.py for terminology consistency. PS My GitHub ID is [[ https://github.com/EugeneZelenko \| EugeneZelenko ]], if it's necessary for attribution. Reviewers: alexfh, hokein, aaron.ballman, njames93, MyDeveloperDay Reviewed By: njames93 Subscribers: Andi, xazax.hun, cfe-commits Tags: #clang-tools-extra, #clang Differential Revision: https://reviews.llvm.org/D73580
	clang-tools-extra/clang-tidy/rename_check.py
	clang-tools-extra/clang-tidy/add_new_check.py
	clang-tools-extra/docs/ReleaseNotes.rst
Commit 0ed7a61543840ddfe4dcc71307dd77b032dcca6c by craig.topper [X86] Fix a -Wparentheses warning. NFC
	llvm/lib/Target/X86/X86ISelLowering.cpp
Commit 6fa3894c4e771c773712b1ae777f78c1c922a908 by Louis Dionne [clang] Fix search path logic for C_INCLUDE_DIRS For each absolute path given to C_INCLUDE_DIRS, we want it to be added as-is to the include search path. Relative paths should be prefixed with the sysroot. Thanks to Marco Hinz for the patch. Differential Revision: https://reviews.llvm.org/D69221
	clang/lib/Driver/ToolChains/Solaris.cpp
	clang/lib/Driver/ToolChains/Linux.cpp
	clang/lib/Driver/ToolChains/Hurd.cpp
	clang/lib/Driver/ToolChains/WebAssembly.cpp
	clang/lib/Driver/ToolChains/Darwin.cpp
	clang/lib/Driver/ToolChains/Fuchsia.cpp
Commit af64b31959f634031e5ddbcf8df1fab69689bfee by omair.javaid Add target.xml support for qXfer request. Summary: Requesting registers one by one takes a while in our project. We want to get rid of it by using target.xml. Reviewers: jarin, labath, omjavaid Reviewed By: labath, omjavaid Subscribers: omjavaid, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D74217
	lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.h
	lldb/packages/Python/lldbsuite/test/tools/lldb-server/registers-target-xml-reading/Makefile
	lldb/packages/Python/lldbsuite/test/tools/lldb-server/registers-target-xml-reading/TestGdbRemoteTargetXmlPacket.py
	lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
	lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
	lldb/packages/Python/lldbsuite/test/tools/lldb-server/registers-target-xml-reading/main.cpp
Commit 0ffa6e1a7e1c5de36276375486f49277c6f95d0e by rupprecht [lldb] Fix version string when using LLDB_REVISION but not LLDB_REPOSITORY Summary: lldb's format string (line one) is: `lldb version $clang_version ($lldb_repo revision $lldb_revision)` When only using $lldb_revision and not $lldb_repo, this might look like: `lldb version 11 ( revision 12345)` which looks pretty ugly. Aside: I'm not sure we really need all the different versions since we've moved to the monorepo layout -- I don't think anyone is using different llvm/clang/lldb revisions, are they? We could likely tidy this up further if we knew how people consumed the output of lldb --version. Reviewers: labath, JDevlieghere, friss Subscribers: lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D74859
	lldb/source/lldb.cpp
Commit f9c326364e76ea734ce87c9fab5ac8b08ef8e7bb by llvm-dev [DAGCombiner] Use SDValue::getConstantOperandAPInt helper where possible. NFC.
	llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 726c342ce27ada28efe90cb04ffb69c75065710a by francisvm [macho][NFC] Extract all CPU_(SUB_)TYPE logic to libObject This moves all the logic of converting LLVM Triples to MachO::CPU_(SUB_)TYPE from the specific target (Target)AsmBackend to more convenient functions in libObject. This also gets rid of the separate two X86AsmBackend classes. Differential Revision: https://reviews.llvm.org/D74808
	llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
	llvm/lib/Object/MachOObjectFile.cpp
	llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
	llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
	llvm/include/llvm/Object/MachO.h
	llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
	llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
	llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
Commit 70d8fec7c947996e857aa136aa22c22a555b02fa by riddleriver [mlir] Refactor the structure of the 'verifyConstructionInvariants' methods. Summary: The current structure suffers from several problems, but the main one is that a construction failure is impossible to debug when using the 'get' methods. This is because we only optionally emit errors, so there is no context given to the user about the problem. This revision restructures this so that errors are always emitted, and the 'get' methods simply pass in an UnknownLoc to emit to. This allows for removing usages of the more constrained "emitOptionalLoc", as well as removing the need for the context parameter. Fixes [PR#44964](https://bugs.llvm.org/show_bug.cgi?id=44964) Differential Revision: https://reviews.llvm.org/D74876
	mlir/include/mlir/Dialect/SPIRV/TargetAndABI.h
	mlir/include/mlir/IR/Location.h
	mlir/include/mlir/IR/Attributes.h
	mlir/docs/DefiningAttributesAndTypes.md
	mlir/lib/IR/Types.cpp
	mlir/lib/Dialect/SPIRV/TargetAndABI.cpp
	mlir/include/mlir/IR/StandardTypes.h
	mlir/include/mlir/IR/StorageUniquerSupport.h
	mlir/include/mlir/Dialect/QuantOps/QuantTypes.h
	mlir/lib/IR/StandardTypes.cpp
	mlir/lib/IR/MLIRContext.cpp
	mlir/include/mlir/IR/Types.h
	mlir/lib/Dialect/QuantOps/IR/QuantTypes.cpp
	mlir/lib/IR/Attributes.cpp
Commit 3f785212e9ceb85251183b1fcf5902715df923fb by francisvm Revert "[macho][NFC] Extract all CPU_(SUB_)TYPE logic to libObject" This reverts commit 726c342ce27ada28efe90cb04ffb69c75065710a. This breaks the windows bots with linker errors.
	llvm/include/llvm/Object/MachO.h
	llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
	llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
	llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
	llvm/lib/Object/MachOObjectFile.cpp
	llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
	llvm/lib/Target/AArch64/MCTargetDesc/AArch64MachObjectWriter.cpp
	llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Commit da181d4ba0cdbae487ba1571917adb8677456e55 by sd.fertile [PowerPC][NFC] Cleanup some of the Darwin mentions in the README.txt.
	llvm/lib/Target/PowerPC/README.txt
Commit 064cd2ecdb3d0c52be5b6cf4fc67125baa714d3a by spatel [x86] allow peeking through an extract_subvector to find a splatted operand The motivating case is seen in "splat4_v8f32_load_store" and based on code in PR42024: https://bugs.llvm.org/show_bug.cgi?id=42024 (I haven't stepped through the v8i32 sibling test yet to see why that diverged.) There are other potential improvements visible like allowing scalarization or vector narrowing. Differential Revision: https://reviews.llvm.org/D74909
	llvm/test/CodeGen/X86/avx-splat.ll
	llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
	llvm/test/CodeGen/X86/insertelement-var-index.ll
	llvm/test/CodeGen/X86/masked_gather.ll
	llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
	llvm/lib/Target/X86/X86ISelLowering.cpp
	llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
	llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
	llvm/test/CodeGen/X86/x86-interleaved-access.ll
	llvm/test/CodeGen/X86/pr34653.ll
	llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
	llvm/test/CodeGen/X86/extractelement-load.ll
	llvm/test/CodeGen/X86/fma.ll
Commit 5d2baa956ac3784e3956e35f610e118cacc7128b by alexbrachetmialot [libc] Add Initial Support for Signals Summary: This patch adds signal support on Linux. The current implementation gets the SIG* macros and types like `sigset_t` from <linux/signals.h> This patch also adds raise(3), and internal routines `block_all_signals` and `restore_signals` Reviewers: sivachandra, MaskRay, gchatelet Reviewed By: sivachandra Subscribers: libc-commits, mgorny, tschuett Differential Revision: https://reviews.llvm.org/D74528
	libc/include/signal.h.def
	libc/spec/linux.td
	libc/test/src/signal/raise_test.cpp
	libc/src/signal/linux/CMakeLists.txt
	libc/test/src/CMakeLists.txt
	libc/src/signal/linux/raise.cpp
	libc/config/linux/api.td
	libc/src/signal/CMakeLists.txt
	libc/test/src/signal/CMakeLists.txt
	libc/spec/stdc.td
	libc/include/CMakeLists.txt
	libc/src/signal/linux/signal.h
	libc/lib/CMakeLists.txt
	libc/src/signal/raise.h
	libc/config/linux/signal.h.in
	libc/src/CMakeLists.txt