Started 1 yr 4 mo ago
Took 3 hr 18 min

Build clang-d399583-ga7c6471a8538-t24154-b24154.tar.gz (Sep 22, 2021 5:52:09 AM)


No known issues detected

Build Log

  1. [ARM] Add additional tests for VMOVL in tail predicated loops. (details)
  2. [AMDGPU] Divergence-driven instruction selection for mul i32 (details)
  3. [AMDGPU] Convert mac/fmac to mad/fma when folding output modifiers (details)
  4. [AArch64][SVE] Add missing load/store patterns for unpacked bfloat vectors. (details)
  5. [VectorCombine] Switch to using a worklist. (details)
  6. [LoopVectorize][X86] Add operands to make it more obvious what line the CHECK concerns (details)
  7. [SelectionDAG] Make WidenVecRes_Convert work for scalable vectors. (details)
  8. [hwasan] also omit safe mem[cpy|mov|set]. (details)
  9. Don't fold (select C, (gep Ptr, Idx), Ptr) if C is vector but Idx is scalar (details)
  10. Unbreak module builds by making InstructionWorklist.h non-modular (details)
  11. [ARM] Allow smaller VMOVL in tail predicated loops (details)
  12. [lldb] [Windows] Fix continuing from breakpoints and singlestepping on ARM/AArch64 (details)
  13. [Matrix] Emit assumption that matrix indices are valid. (details)
  14. Revert "[CodeGen] regenerate test checks; NFC" (details)
  15. Revert "[InstCombine] fold cast of right-shift if high bits are not demanded" (details)
  16. [Passes] Run vector-combine early with -fenable-matrix. (details)

Started by upstream project relay-lnt-ctmark build number 13167
originally caused by:

This run spent:

  • 3 hr 4 min waiting;
  • 3 hr 18 min build duration;
  • 3 hr 18 min total from scheduled to completion.
Revision: 9d4301d25f098f5efcf2a56c9c5d16645e3957d5
  • refs/remotes/origin/main
Revision: a7c6471a85380f5af644e50daf2951b41c82f1b2
Repository: http://labmaster3.local/git/llvm-project.git
  • detached
Revision: b4db71089b2ab669e4071dc6cdc3c60959ddc1d5
  • refs/remotes/origin/main
Revision: b983131b7e46d34f0eb2be399baf6c2e48d5734c
  • refs/remotes/origin/main