Changes

Summary

  1. [lld/ELF] PR44498: Support input filename in double quote (details)
  2. [lldb/DWARF] Remove one more auto-dwo method (details)
  3. Remove extra ';' to fix Wpedantic. NFCI. (details)
  4. [X86][SSE] combineExtractWithShuffle - pull out repeated extract index (details)
  5. [mlir] Enable specifying verify on OpInterface (details)
  6. [mlir][spirv] Add lowering for composite std.constant. (details)
  7. Extend misc-misplaced-const to detect using declarations as well as (details)
  8. [llvm-mca][NFC] Regenerate tests @HEAD. (details)
  9. Use SelectionDAG::getShiftAmountConstant(). NFCI. (details)
  10. [SelectionDAG] getShiftAmountConstant - assert the type is an integer. (details)
  11. [InstCombine] add tests for fneg+fadd; NFC (details)
  12. AMDGPU: Fix missing immarg on llvm.amdgcn.interp.mov (details)
  13. AMDGPU/GlobalISel: RegBankSelect interp intrinsics (details)
  14. Revert "Extend misc-misplaced-const to detect using declarations as well (details)
  15. [ASTImporter] Properly delete decls from SavedImportPaths (details)
  16. AMDGPU: Fix interaction of tfe and d16 (details)
  17. AMDGPU/GlobalISel: Handle atomic_inc/atomic_dec (details)
  18. AMDGPU/GlobalISel: Fix RegbankSelect for llvm.amdgcn.fmul.legacy (details)
  19. [MachineScheduler] Allow clustering mem ops with complex addresses (details)
  20. [AArch64][SVE] Add patterns for unpredicated load/store to (details)
  21. [ARM] MVE Gather Scatter cost model tests. NFC (details)
  22. [ARM] Basic gather scatter cost model (details)
  23. [VE] setcc isel patterns (details)
  24. [InstCombine] fneg(X + C) --> -C - X (details)
  25. Unconditionally enable lvalue function designators; NFC (details)
  26. AMDGPU/GlobalISel: Add pre-legalize combiner pass (details)
  27. AMDGPU: Do binop of select of constant fold in AMDGPUCodeGenPrepare (details)
  28. AMDGPU: Look through casted selects to constant fold bin ops (details)
  29. AMDGPU: Fix typo (details)
  30. [VE] select and selectcc patterns (details)
  31. [lldb/Target] Sort CMakeLists (NFC) (details)
  32. AMDGPU/GlobalISel: Fold constant offset vector extract indexes (details)
  33. [mlir] Swap use of to_vector() with lookupValues() in LLVMIRIntrinsicGen (details)
  34. AMDGPU/GlobalISel: Fix RegBankSelect for G_INSERT_VECTOR_ELT (details)
  35. AMDGPU/GlobalISel: Select G_INSERT_VECTOR_ELT (details)
  36. [compiler-rt] [builtins] Fix clear_cache_test to work with MPROTECT (details)
  37. [gn build] (manually) port a174f0da62f (details)
  38. AMDGPU/GlobalISel: Fold add of constant into G_INSERT_VECTOR_ELT (details)
  39. [X86][SSE] combineExtractWithShuffle - (details)
  40. [RISCV] Support ABI checking with per function target-features (details)
  41. AMDGPU/GlobalISel: Keep G_BITCAST out of waterfall loop (details)
  42. AMDGPU: Fix element size assertion (details)
  43. [AArch64] Add test for DWARF return address signing (details)
  44. [PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst. (details)
  45. AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp8 (details)
  46. AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp (details)
  47. Regenerate test/CodeGen/ARM/vext.ll. NFC. (details)
  48. Precommit NFC part of DAGCombiner change. NFC. (details)
  49. [NFC][XCOFF] Refactor Csect creation into TargetLoweringObjectFile (details)
  50. AMDGPU/GlobalISel: Handle 16-bank LDS llvm.amdgcn.interp.p1.f16 (details)
Commit c42fe24754f4a2173d16b799085cec88cad6f24c by thomasp
[lld/ELF] PR44498: Support input filename in double quote
Summary: Linker scripts allow filenames to be put in double quotes to
prevent characters in filenames that are part of the linker script
syntax from having their special meaning. Case in point the * wildcard
character.
Availability of double quoting filenames also allows to fix a failure in
ELF/linkerscript/filename-spec.s when the path contain a @ which the
lexer consider as a special characters and thus break up a filename
containing it. This may happens under Jenkins which createspath such as
pipeline@2.
To avoid the need for escaping GlobPattern metacharacters in filename in
double quotes, GlobPattern::create is augmented with a new parameter to
request literal matching instead of relying on the presence of a
wildcard character in the pattern.
Reviewers: jhenderson, MaskRay, evgeny777, espindola, alexshap
Reviewed By: MaskRay
Subscribers: peter.smith, grimar, ruiu, emaste, arichardson, hiraditya,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72517
The file was modifiedlld/ELF/SymbolTable.cpp
The file was modifiedlld/test/ELF/linkerscript/filename-spec.s
The file was modifiedlld/ELF/LinkerScript.h
The file was modifiedlld/Common/Strings.cpp
The file was modifiedlld/include/lld/Common/Strings.h
The file was modifiedlld/ELF/ScriptParser.cpp
Commit 3d7177acd751704d42278ea78e5353943187045d by pavel
[lldb/DWARF] Remove one more auto-dwo method
Summary: Our DWARFUnit was automatically forwarding the requests to the
split unit when looking for a DIE by offset. llvm::DWARFUnit does not do
that, and is not likely to start doing it any time soon.
This patch deletes the this logic and updates the callers to request the
correct unit instead. While doing that, I've found a bit of duplicated
code for lookup up a function and block by address, so I've extracted
that into a helper function.
Reviewers: JDevlieghere, aprantl, clayborg, jdoerfert
Subscribers: lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D73112
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
Commit 201c646b2b9988cdebf6e95d523283009ae2e5ba by llvm-dev
Remove extra ';' to fix Wpedantic. NFCI.
The file was modifiedclang-tools-extra/clang-tidy/bugprone/ReservedIdentifierCheck.cpp
Commit 963f26818693afe8edd7826c9e4266a4cfc86dae by llvm-dev
[X86][SSE] combineExtractWithShuffle - pull out repeated extract index
code. NFCI.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 178562fb352d12b5235c63f75297b8a456b53a0f by jpienaar
[mlir] Enable specifying verify on OpInterface
Summary: Add method in ODS to specify verification for operations
implementing a OpInterface. Use this with infer type op interface to
verify that the inferred type matches the return type and remove special
case in TestPatterns.
This could also have been achieved by using OpInterfaceMethod but verify
seems pretty common and it is not an arbitrary method that just happened
to be named verifyTrait, so having it be defined in special way seems
appropriate/better documenting.
Differential Revision: https://reviews.llvm.org/D73122
The file was modifiedmlir/docs/OpDefinitions.md
The file was modifiedmlir/include/mlir/TableGen/OpInterfaces.h
The file was modifiedmlir/test/mlir-tblgen/return-types.mlir
The file was modifiedmlir/include/mlir/Analysis/InferTypeOpInterface.h
The file was modifiedmlir/include/mlir/Analysis/InferTypeOpInterface.td
The file was modifiedmlir/lib/Analysis/InferTypeOpInterface.cpp
The file was modifiedmlir/tools/mlir-tblgen/OpInterfacesGen.cpp
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/lib/TableGen/OpInterfaces.cpp
The file was modifiedmlir/test/lib/TestDialect/TestPatterns.cpp
Commit 4460cb5bcd739156c1dd67110c3456ba8322a76e by antiagainst
[mlir][spirv] Add lowering for composite std.constant.
Add lowering for constant operation with ranked tensor type to
spv.constant with spv.array type.
Differential Revision: https://reviews.llvm.org/D73022
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
The file was modifiedmlir/test/Conversion/StandardToSPIRV/std-to-spirv.mlir
The file was modifiedmlir/lib/Dialect/SPIRV/SPIRVLowering.cpp
Commit ecc7dae50c41bc8a129a158ecf0ae0270126505c by aaron
Extend misc-misplaced-const to detect using declarations as well as
typedef
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/misc-misplaced-const.rst
The file was modifiedclang-tools-extra/clang-tidy/misc/MisplacedConstCheck.cpp
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/misc-misplaced-const.cpp
Commit 2accdb6ae19093e2a571072b4f19b5f58c0c9349 by courbet
[llvm-mca][NFC] Regenerate tests @HEAD.
For Zen2.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-4.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse3.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-x86_64.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-avx2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-ssse3.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse41.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-5.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-sha.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-aes.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-x87.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse42.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-adx.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-mwaitx.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-cmov.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-avx1.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-clzero.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse2.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-7.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-fsgsbase.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-lzcnt.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-x86_32.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-fma.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-sse4a.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-3.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-6.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-mmx.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/resources-popcnt.s
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-2.s
Commit c784e5451b29545e2fb450cc590410c0914bb849 by llvm-dev
Use SelectionDAG::getShiftAmountConstant(). NFCI.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 80656fd7aef05bce5fe7ee0ab61220c01455018f by llvm-dev
[SelectionDAG] getShiftAmountConstant - assert the type is an integer.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit c0f53ed80662fb9d5facbf0b05284f906a355c83 by spatel
[InstCombine] add tests for fneg+fadd; NFC
The file was modifiedllvm/test/Transforms/InstCombine/fneg.ll
Commit 64e95282012a81bf7a2a93473b85420a440839ee by arsenm2
AMDGPU: Fix missing immarg on llvm.amdgcn.interp.mov
The first operand maps to an immediate field, so this should be immarg.
The file was modifiedllvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsAMDGPU.td
Commit b94d3b9b77a0ee2e55a38133d69a458158ef4073 by arsenm2
AMDGPU/GlobalISel: RegBankSelect interp intrinsics
Note this assumes the future use of immediates for immarg, not the
current G_CONSTANT which will be emitted.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
Commit e3b15ed376f3753d2a4e16281f8230e4ffed41ba by aaron
Revert "Extend misc-misplaced-const to detect using declarations as well
as typedef"
This reverts commit ecc7dae50c41bc8a129a158ecf0ae0270126505c due to
breaking bots:
http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/22157
http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/43297
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/misc-misplaced-const.cpp
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/misc-misplaced-const.rst
The file was modifiedclang-tools-extra/clang-tidy/misc/MisplacedConstCheck.cpp
Commit 4481eefbe8425c63289186dd13319aaa7043e67f by Raphael Isemann
[ASTImporter] Properly delete decls from SavedImportPaths
Summary: We see a significant regression (~40% slower on large
codebases) in expression evaluation after
https://reviews.llvm.org/rL364771. A sampling profile shows the extra
time is spent in SavedImportPathsTy::operator[] when called from
ASTImporter::Import. I believe this is because ASTImporter::Import adds
an element to the SavedImportPaths map for each decl unconditionally
(see
https://github.com/llvm/llvm-project/blob/7b81c3f8793d30a4285095a9b67dcfca2117916c/clang/lib/AST/ASTImporter.cpp#L8256).
To fix this, we call SavedImportPathsTy::erase on the declaration rather
than clearing its value vector. That way we do not accidentally
introduce new empty elements.  (With this patch the performance is
restored, and we do not see SavedImportPathsTy::operator[] in the
profile anymore.)
Reviewers: martong, teemperor, a.sidorin, shafik
Reviewed By: martong
Subscribers: rnkovacs, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73166
The file was modifiedclang/lib/AST/ASTImporter.cpp
Commit 9c928649a085646c4c779bac095643b50b464d83 by arsenm2
AMDGPU: Fix interaction of tfe and d16
This using the wrong result register, and dropping the result entirely
for v2f16. This would fail to select on the scalar case. I believe it
was also mishandling packed/unpacked subtargets.
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
Commit a722cbf77cc638064592c508ea0c1be13775ee31 by arsenm2
AMDGPU/GlobalISel: Handle atomic_inc/atomic_dec
The intermediate instruction drops the extra volatile argument. We are
missing an atomic ordering on these.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.atomic.inc.mir
The file was removedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.atomic.dec.mir
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 70096ca111ee2848fb2e29a7cb3e4fb7e3ba9ef9 by arsenm2
AMDGPU/GlobalISel: Fix RegbankSelect for llvm.amdgcn.fmul.legacy
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit e0f0d0e55cc7d389ad0692fbc9678e7895978355 by jay.foad
[MachineScheduler] Allow clustering mem ops with complex addresses
The generic BaseMemOpClusterMutation calls into TargetInstrInfo to
analyze the address of each load/store instruction, and again to decide
whether two instructions should be clustered. Previously this had to
represent each address as a single base operand plus a constant byte
offset. This patch extends it to support any number of base operands.
The old target hook getMemOperandWithOffset is now a convenience
function for callers that are only prepared to handle a single base
operand. It calls the new more general target hook
getMemOperandsWithOffset.
The only requirements for the base operands returned by
getMemOperandsWithOffset are:
- they can be sorted by MemOpInfo::Compare, such that clusterable ops
get sorted next to each other, and
- shouldClusterMemOps knows what they mean.
One simple follow-on is to enable clustering of AMDGPU FLAT instructions
with both vaddr and saddr (base register + offset register). I've left a
FIXME in the code for this case.
Differential Revision: https://reviews.llvm.org/D71655
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiInstrInfo.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonInstrInfo.h
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.h
The file was modifiedllvm/lib/CodeGen/TargetInstrInfo.cpp
The file was modifiedllvm/lib/Target/Lanai/LanaiInstrInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/MachineScheduler.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
Commit 4cf16efe49766d454eda74927a547a0cf587f540 by sander.desmalen
[AArch64][SVE] Add patterns for unpredicated load/store to
frame-indices.
This patch also fixes up a number of cases in DAGCombine and
SelectionDAGBuilder where the size of a scalable vector is used in a
fixed-width context (thus triggering an assertion failure).
Reviewers: efriedma, c-rhodes, rovka, cameron.mcinally
Reviewed By: efriedma
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71215
The file was modifiedllvm/lib/Analysis/Loads.cpp
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was addedllvm/test/CodeGen/AArch64/spillfill-sve.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/include/llvm/Analysis/MemoryLocation.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit 0b83e14804c46aaf8ba40863bb6d1a3cf175b997 by david.green
[ARM] MVE Gather Scatter cost model tests. NFC
The file was addedllvm/test/Analysis/CostModel/ARM/mve-gather-scatter-cost.ll
Commit e9c198278e2193a8ba78686ef8acc49c587dd40e by david.green
[ARM] Basic gather scatter cost model
This is a very basic MVE gather/scatter cost model, based roughly on the
code that we will currently produce. It does not handle truncating
scatters or extending gathers correctly yet, as it is difficult to tell
that they are going to be correctly extended/truncated from the limited
information in the cost function.
This can be improved as we extend support for these in the future.
Based on code originally written by David Sherwood.
Differential Revision: https://reviews.llvm.org/D73021
The file was modifiedllvm/test/Analysis/CostModel/ARM/mve-gather-scatter-cost.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
Commit dc69265eea888e8c6255aebcdd6650420dd00cfb by simon.moll
[VE] setcc isel patterns
Summary: SETCC isel patterns and tests for i32/64 and fp32/64 comparison
Reviewers: arsenm, rengolin, craig.topper, k-ishizaka
Reviewed By: arsenm
Subscribers: merge_guards_bot, wdng, hiraditya, llvm-commits
Tags: #ve, #llvm
Differential Revision: https://reviews.llvm.org/D73171
The file was addedllvm/test/CodeGen/VE/setccf64.ll
The file was addedllvm/test/CodeGen/VE/setcci32.ll
The file was modifiedllvm/lib/Target/VE/VEISelLowering.cpp
The file was addedllvm/test/CodeGen/VE/setccf64i.ll
The file was addedllvm/test/CodeGen/VE/setccf32.ll
The file was addedllvm/test/CodeGen/VE/setcci32i.ll
The file was addedllvm/test/CodeGen/VE/setccf32i.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was addedllvm/test/CodeGen/VE/setcci64.ll
The file was addedllvm/test/CodeGen/VE/setcci64i.ll
Commit 0ade2abdb01f4a16b1f08d1a78d664b9e9d5f3b5 by spatel
[InstCombine] fneg(X + C) --> -C - X
This is 1 of the potential folds uncovered by extending D72521.
We don't seem to do this in the backend either (unless I'm not seeing
some target-specific transform).
icc and gcc (appears to be target-specific) do this transform.
Differential Revision: https://reviews.llvm.org/D73057
The file was modifiedllvm/test/Transforms/InstCombine/fneg.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
Commit 968561bcdc34c7d74482fe3bb69a045abf08d2c1 by aaron
Unconditionally enable lvalue function designators; NFC
We previously had to guard against older MSVC and GCC versions which had
rvalue references but not support for marking functions with ref
qualifiers. However, having bumped our minimum required version to MSVC
2017 and GCC 5.1 mean we can unconditionally enable this feature. Rather
than keeping the macro around, this replaces use of the macro with the
actual ref qualifier.
The file was modifiedllvm/include/llvm/Support/Compiler.h
The file was modifiedllvm/unittests/ADT/OptionalTest.cpp
The file was modifiedclang/include/clang/StaticAnalyzer/Core/PathSensitive/ExplodedGraph.h
The file was modifiedllvm/include/llvm/ADT/Optional.h
The file was modifiedllvm/include/llvm/ADT/PointerIntPair.h
Commit a174f0da62f1cad36d21c040bf37bfdd291b28cf by arsenm2
AMDGPU/GlobalISel: Add pre-legalize combiner pass
Just copy the AArch64 pass as-is for now, except for removing the memcpy
handling.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
The file was addedllvm/lib/Target/AMDGPU/AMDGPUCombine.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGISel.td
The file was addedllvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
The file was modifiedllvm/lib/Target/AMDGPU/CMakeLists.txt
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
Commit bcd91778fe7e6fc66cdccc5ddc3ff3fc48909f6b by arsenm2
AMDGPU: Do binop of select of constant fold in AMDGPUCodeGenPrepare
DAGCombiner does this, but divisions expanded here miss this
optimization. Since 67aa18f165640374cf0e0a6226dc793bbda6e74f, divisions
have been expanded here and missed out on this optimization. Avoids test
regressions in a future patch.
The file was addedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/dagcombine-select.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
Commit 2fe500ab5bb4d50a5ac6ed9600f9900b46e55802 by arsenm2
AMDGPU: Look through casted selects to constant fold bin ops
The promotion of the uniform select to i32 interfered with this fold.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/dagcombine-select.ll
Commit e93e1b621c4dc5c05614ccef3a19748683751f9a by arsenm2
AMDGPU: Fix typo
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
Commit 83b67526d5c2ba070996697e73e8954776986303 by simon.moll
[VE] select and selectcc patterns
Summary: select and selectcc isel patterns and tests for i32/i64 and
fp32/fp64. Includes optimized selectcc patterns for fmin/fmax/maxs/mins.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D73195
The file was addedllvm/test/CodeGen/VE/selectccf32c.ll
The file was addedllvm/test/CodeGen/VE/selectccf64i.ll
The file was addedllvm/test/CodeGen/VE/select.ll
The file was addedllvm/test/CodeGen/VE/selectccf64c.ll
The file was addedllvm/test/CodeGen/VE/selectcci64.ll
The file was addedllvm/test/CodeGen/VE/selectcci64i.ll
The file was addedllvm/test/CodeGen/VE/selectcci32.ll
The file was addedllvm/test/CodeGen/VE/selectcci64c.ll
The file was addedllvm/test/CodeGen/VE/min.ll
The file was addedllvm/test/CodeGen/VE/selectccf32i.ll
The file was addedllvm/test/CodeGen/VE/selectccf32.ll
The file was modifiedllvm/lib/Target/VE/VEInstrInfo.td
The file was addedllvm/test/CodeGen/VE/selectcci32c.ll
The file was addedllvm/test/CodeGen/VE/max.ll
The file was addedllvm/test/CodeGen/VE/selectccf64.ll
The file was addedllvm/test/CodeGen/VE/selectcci32i.ll
Commit 9dc9f7ca145e7fd5fafbdf071a2e5b5914918c04 by medismail.bennani
[lldb/Target] Sort CMakeLists (NFC)
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
The file was modifiedlldb/source/Target/CMakeLists.txt
Commit e3d352c54119b5d30821b4857dec77ac0af688c8 by arsenm2
AMDGPU/GlobalISel: Fold constant offset vector extract indexes
Handle dynamic vector extracts that use an index that's an add of a
constant offset into moving the base subregister of the indexing
operation.
Force the add into the loop in regbankselect, which will be recognized
when selected.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit 04a151710e8b04ca4c8e74782ceaadfe7ceca90c by hayarms
[mlir] Swap use of to_vector() with lookupValues() in LLVMIRIntrinsicGen
Summary: llvm::to_vector() accepts a Range value and not the pair of
arguments we are currently passing. Also we probably want the lowered
LLVM values in the vector, while operand_begin()/operand_end() on MLIR
ops returns MLIR types. lookupValues() seems the correct way to collect
such values.
Reviewers: rriddle, andydavis1, antiagainst, nicolasvasilache, ftynse
Subscribers: jdoerfert, mehdi_amini, jpienaar, burmako, shauheen,
arpith-jacob, mgester, lucyrfox, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73137
The file was modifiedmlir/test/mlir-tblgen/llvm-intrinsics.td
The file was modifiedmlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
Commit 3524d4412cffd5ad2c05c017964719e9f96d4382 by arsenm2
AMDGPU/GlobalISel: Fix RegBankSelect for G_INSERT_VECTOR_ELT
The result and source vector are going to be tied, so these need to be
the same bank.
The inserted value also needs to be broken down based on the result
bank, not the inserted value itself.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
Commit d1dbb5e4718a8f845abf0783513a33a55429470b by arsenm2
AMDGPU/GlobalISel: Select G_INSERT_VECTOR_ELT
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
Commit 3215f7c7a81ffc7e6c0e49b21a4d4a01a2d945be by mgorny
[compiler-rt] [builtins] Fix clear_cache_test to work with MPROTECT
Fix clear_cache_test to work on NetBSD with PaX MPROTECT enabled, that
is when creating W+X mmaps is prohibited.  Use the recommended solution:
create two mappings for the same memory area, make one of them RW, while
the other RX.  Copy the function into the RW area but run it from the RX
area.
In order to implement this, I've split the pointer variables to
'write_buffer' and 'execution_buffer'.  Both are separate pointers on
NetBSD, while they have the same value on other systems.
I've also split the memcpy_f() into two: new memcpy_f() that only takes
care of copying memory and discards the (known) result of memcpy(), and
realign_f() that applies ARM realignment to the given pointer. Again,
there should be no difference on non-NetBSD systems but on NetBSD
copying is done on write_buffer, while realignment on pointer to the
execution_buffer.
I have tested this change on NetBSD and Linux.
Differential Revision: https://reviews.llvm.org/D72578
The file was modifiedcompiler-rt/test/builtins/Unit/clear_cache_test.c
Commit 349f6bb873df600b30b0cb2a51c940c0b9a46fb3 by thakis
[gn build] (manually) port a174f0da62f
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Commit 52ec7379adfa27b24f834551a2b3bf2b7249549c by arsenm2
AMDGPU/GlobalISel: Fold add of constant into G_INSERT_VECTOR_ELT
Move the subregister base like in the extract case.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Commit a14aa7dabde3e985c6ae3d89fd86c6be788c4b90 by llvm-dev
[X86][SSE] combineExtractWithShuffle -
extract(bictcast(scalar_to_vector(x))) --> x
Removes some unnecessary gpr<-->fpu traffic
The file was modifiedllvm/test/CodeGen/X86/scalar_widen_div.ll
The file was modifiedllvm/test/CodeGen/X86/vector-idiv-v2i32.ll
The file was modifiedllvm/test/CodeGen/X86/bitcast-vector-bool.ll
The file was modifiedllvm/test/CodeGen/X86/oddsubvector.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
Commit 0cb274de397a193fb37c60653b336d48a3a4f1bd by zakk.chen
[RISCV] Support ABI checking with per function target-features
1. if users don't specific -mattr, the default target-feature come from
IR attribute. 2. fixed bug and re-land this patch
Reviewers: lenary, asb
Reviewed By: lenary
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70837
The file was modifiedllvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Commit bb562d1af0e9f959eceb8b41cc5530202d55731a by arsenm2
AMDGPU/GlobalISel: Keep G_BITCAST out of waterfall loop
The waterfall utility function blindly inserts a phi for every def in
the loop. We don't need this one to be preserved for every iteration.
Saves an extra phi and copy inside the loop body.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
Commit 0bf434ccd5627c385af96ef7a456294f195cca43 by arsenm2
AMDGPU: Fix element size assertion
The GlobalISel usage called this with bits, but the DAG usage was
incorrectly using bytes.
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit a8ff6c0b09718a048ec9b9fc7db33fd39f6500cc by pablo.barrio
[AArch64] Add test for DWARF return address signing
Summary: Patch by LukeCheeseman and pbarrio
Reviewers: samparker, chill
Subscribers: kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72835
The file was addedllvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
Commit ddbc728828c70728473b47c9f7427aa9514f3d17 by yamauchi
[PGO][PGSO] Update BFI in CodeGenPrepare::optimizeSelectInst.
Summary: Without the BFI update, some hot blocks are incorrectly treated
as cold code.
This fixes a FDO perf regression in the TSVC benchmark from D71288.
Reviewers: davidxl
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73146
The file was modifiedllvm/test/CodeGen/X86/cmov-into-branch.ll
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
Commit dd09ec1208bd93a42cece7abd31fc5e31f1b76d8 by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp8
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp8.ll
Commit c05f23e409a7613a884de6ef89170e13931a697b by arsenm2
AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp
This is deprecated, but easy to support.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
Commit fb8a3d18340e0b5c2266a84d6a5158f5cd8bc9a2 by Stanislav.Mekhanoshin
Regenerate test/CodeGen/ARM/vext.ll. NFC.
This is to pre-commit whitespace only changes before D73132.
The file was modifiedllvm/test/CodeGen/ARM/vext.ll
Commit 2d0fcf786c5c7f384e30a955d2e7da46d1f98949 by Stanislav.Mekhanoshin
Precommit NFC part of DAGCombiner change. NFC.
This is NFC part of DAGCombiner::visitEXTRACT_SUBVECTOR() change in the
D73132.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 45a4aaea7fdf21a139b35ad6d25f6c4a150e065f by daltenty
[NFC][XCOFF] Refactor Csect creation into TargetLoweringObjectFile
Summary: We create a number of standard types of control sections in
multiple places for things like the function descriptors, external
references and the TOC anchor among others, so it is possible for  their
properties to be defined inconsistently in different places. This
refactor moves their creation and properties into functions in the
TargetLoweringObjectFile class hierarchy, where functions for retrieving
various special types of sections typically seem to reside.
Note: There is one case in PPCISelLowering which is specific to function
entry points which we don't address since we don't have access to the
TLOF there.
Reviewers: DiggerLin, jasonliu, hubert.reinterpretcast
Reviewed By: jasonliu, hubert.reinterpretcast
Subscribers: wuzish, nemanjai, hiraditya, kbarton, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72347
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
The file was modifiedllvm/lib/MC/MCObjectFileInfo.cpp
The file was modifiedllvm/include/llvm/Target/TargetLoweringObjectFile.h
The file was modifiedllvm/include/llvm/MC/MCObjectFileInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Commit 1192d7b254722932465461214b5491e7463d33cd by arsenm2
AMDGPU/GlobalISel: Handle 16-bank LDS llvm.amdgcn.interp.p1.f16
The pattern is also mishandled by the generated matcher, so workaround
this as in the DAG path.
The existing DAG tests aren't particularly targeted to just this one
intrinsic. These also end up differing in scheduling from SGPR->VGPR
operand constraint copies.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.p1.f16.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h